operations 05 - immediate 06 - jmp 07 - load 0A - store 0D - cmp 0F - jnz 10 - jz 11 - sub 14 - add 17 - and 1A - or 1D - xor control lines: (2) register select (5) register enable (1) read/write (1) memory enable (1) increment (3) alu operation (1) branch (1) condition (1) load state (1) clear state alu operations: 000 - nothing 001 - subtract 010 - add 011 - and 100 - or 101 - xor register select: 00 - accumulator 01 - instruction pointer 10 - alu output 11 - data registers en1 - accumulator en2 - opcode en3 - ip en4 - alu input en5 - mem data en6 - mem addr r/w 0 - write 1 - read fetch: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 # ip -> addr 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 # increment; read mem 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 # data -> opcode 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 # ip -> addr 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 # increment; read mem 5 immediate: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 # data -> acc 6 jmp: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 # data -> ip 7 load: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 # data -> addr 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 # mem read 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 # data -> acc 10 store: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 # data -> addr 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 # acc -> data 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 # mem store 13 cmp: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 # data -> alu in 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 # acc -> bus, alu = sub 15 jz: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 # if z == 0: data -> ip 16 jnz: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 # if z == 1: data -> ip 17 sub: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 # data -> alu in 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 # acc -> bus; sub 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 # alu out -> acc 20 add: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 # data -> alu in 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 # acc -> bus; add 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 # alu out -> acc 23 and: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 # data -> alu in 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 # acc -> bus; and 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 # alu out -> acc 26 or: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 # data -> alu in 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 # acc -> bus; or 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 # alu out -> acc 29 xor: reg1 reg2 en1 en2 en3 en4 en5 en6 r/w mem inc alu1 alu2 alu3 bra cond 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 # data -> alu in 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 # acc -> bus; xor 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 # alu out -> acc