Project Settings |
---|
Project Name | retro1s_syn | Implementation Name | retro1s_Implmnt |
Top Module | [auto] | Pipelining | 1 |
Retiming | 0 | Resource Sharing | 1 |
Fanout Guide | 10000 | Disable I/O Insertion | 0 |
Disable Sequential Optimizations | 0 | Clock Conversion | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
25 |
5 |
0 |
- |
00m:02s |
- |
12/30/18 12:05 AM |
(premap) | Complete |
4 |
1 |
0 |
0m:00s |
0m:00s |
139MB |
12/30/18 12:05 AM |
(fpga_mapper) | Complete |
28 |
6 |
0 |
0m:09s |
0m:09s |
230MB |
12/30/18 12:05 AM |
Multi-srs Generator |
Complete | | | | | | | 12/30/18 12:05 AM |
Area Summary |
|
PADS | 5 |
FLOPS | 340 |
RAMS
(v_ram) | 4 |
CARRYS | 273 |
LUTS
(total_luts) | 2259 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
top|ext_osc | 36.6 MHz | 24.5 MHz | -6.715 |
System | 1.0 MHz | NA | NA |
Optimizations Summary |
Combined Clock Conversion | 1 / 0 |
| |
|