#Build: Synplify Pro L-2016.09L+ice40, Build 077R, Dec  2 2016
#install: /home/shaos/iCEcube2/synpbase
#OS: Linux 
#Hostname: shaos

# Sun Dec 30 00:05:27 2018

#Implementation: retro1s_Implmnt

Synopsys HDL Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@N: :  | Top-level is not specified. Trying to extract automatically... 
Synopsys VHDL Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Running on host :shaos
@N:CD720 : std.vhd(123) | Setting time resolution to ps
@N: : rs232_sender.vhd(12) | Top entity is set to rs232_sender.
VHDL syntax check successful!

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)


Process completed successfully.
# Sun Dec 30 00:05:27 2018

###########################################################]
Synopsys Verilog Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Running on host :shaos
@I::"/home/shaos/iCEcube2/synpbase/lib/generic/sb_ice40.v" (library work)
@I::"/home/shaos/iCEcube2/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/home/shaos/iCEcube2/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/home/shaos/iCEcube2/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/home/shaos/iCEcube2/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/home/shaos/iCEcube2/examples/retro1s/top.v" (library work)
@I::"/home/shaos/iCEcube2/examples/retro1s/retro.v" (library work)
@I::"/home/shaos/iCEcube2/examples/retro1s/rom.v" (library work)
Verilog syntax check successful!

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)


Process completed successfully.
# Sun Dec 30 00:05:27 2018

###########################################################]
@N: : top.v(2) | Top-level module is set to work.top
Running on host :shaos
@I::"/home/shaos/iCEcube2/synpbase/lib/generic/sb_ice40.v" (library work)
@I::"/home/shaos/iCEcube2/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/home/shaos/iCEcube2/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/home/shaos/iCEcube2/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/home/shaos/iCEcube2/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/home/shaos/iCEcube2/examples/retro1s/top.v" (library work)
@I::"/home/shaos/iCEcube2/examples/retro1s/retro.v" (library work)
@I::"/home/shaos/iCEcube2/examples/retro1s/rom.v" (library work)
Verilog syntax check successful!
File /home/shaos/iCEcube2/examples/retro1s/top.v changed - recompiling
@N:CG364 : retro.v(21) | Synthesizing module retro in library work.

@N:CG179 : retro.v(247) | Removing redundant assignment.
@N:CG179 : retro.v(272) | Removing redundant assignment.
@W:CG532 : retro.v(664) | Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
@W:CL169 : retro.v(55) | Pruning unused register errop. Make sure that there are no unused intermediate registers.
@W:CL271 : retro.v(55) | Pruning unused bits 31 to 24 of inst[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CL134 : retro.v(55) | Found RAM regs, depth=32, width=32
@N:CL134 : retro.v(55) | Found RAM regs, depth=32, width=32
@N:CG364 : rom.v(1) | Synthesizing module rom in library work.

@N:CG364 : sb_ice40.v(4120) | Synthesizing module SB_RGBA_DRV in library work.

@N:CG364 : top.v(1) | Synthesizing module top in library work.

@N:CG794 : top.v(49) | Using module rs232_sender from library work
@W:CL169 : top.v(15) | Pruning unused register frequency_counter_i[27:0]. Make sure that there are no unused intermediate registers.
@N:CL201 : retro.v(55) | Trying to extract state machine for register op.

At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 107MB)


Process completed successfully.
# Sun Dec 30 00:05:29 2018

###########################################################]
Running on host :shaos
@N:CD720 : std.vhd(123) | Setting time resolution to ps
@N: : rs232_sender.vhd(12) | Top entity is set to rs232_sender.

File Dependency file is up to date.  It will not be rewritten.

VHDL syntax check successful!
@N: :  | Setting default value for generic system_speed to 12000000; 
@N: :  | Setting default value for generic baudrate to 115200; 
@N:CD630 : rs232_sender.vhd(12) | Synthesizing work.rs232_sender.rtl.
@N:CD233 : rs232_sender.vhd(28) | Using sequential encoding for type state_type.
Post processing for work.rs232_sender.rtl
@N:CL201 : rs232_sender.vhd(45) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL249 : rs232_sender.vhd(45) | Initial value is not supported on state machine state

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)


Process completed successfully.
# Sun Dec 30 00:05:29 2018

###########################################################]
Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016
@N: :  | Running in 64-bit mode 

=======================================================================================
For a summary of linker messages for components that did not bind, please see log file:
Linked File: retro1s_comp.linkerlog
=======================================================================================


At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sun Dec 30 00:05:29 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime

Process completed successfully.
# Sun Dec 30 00:05:29 2018

###########################################################]
Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016
@N: :  | Running in 64-bit mode 
File /home/shaos/iCEcube2/examples/retro1s/retro1s_Implmnt/synwork/retro1s_comp.srs changed - recompiling
@N:NF107 : top.v(1) | Selected library: work cell: top view verilog as top level
@N:NF107 : top.v(1) | Selected library: work cell: top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sun Dec 30 00:05:30 2018

###########################################################]
Pre-mapping Report

# Sun Dec 30 00:05:30 2018

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1612R, Built Dec  5 2016 09:30:53
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

@A:MF827 :  | No constraint file specified. 
Linked File: retro1s_scck.rpt
Printing clock  summary report in "/home/shaos/iCEcube2/examples/retro1s/retro1s_Implmnt/retro1s_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 105MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=30  set on top level netlist top

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB)



Clock Summary
*****************

Start           Requested     Requested     Clock        Clock                     Clock
Clock           Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------
System          1.0 MHz       1000.000      system       system_clkgroup           0    
top|ext_osc     4.0 MHz       250.590       inferred     Autoconstr_clkgroup_0     376  
========================================================================================

@W:MT529 : retro.v(55) | Found inferred clock top|ext_osc which controls 376 sequential elements including cpu.extaddr[31:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file /home/shaos/iCEcube2/examples/retro1s/retro1s_Implmnt/retro1s.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)

Encoding state machine state[0:3] (in view: work.work_rs232_sender_rtl_12000000_115200_1_system_speedbaudrate(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : rs232_sender.vhd(45) | There are no possible illegal states for state machine state[0:3] (in view: work.work_rs232_sender_rtl_12000000_115200_1_system_speedbaudrate(rtl)); safe FSM implementation is not required.
None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 139MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Dec 30 00:05:31 2018

###########################################################]
Map & Optimize Report

# Sun Dec 30 00:05:31 2018

Synopsys Lattice Technology Mapper, Version maplat, Build 1612R, Built Dec  5 2016 09:30:53
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 136MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

@W:FX107 : retro.v(55) | RAM regs_1[31:0] (in view: work.retro(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W:FX107 : retro.v(55) | RAM regs[31:0] (in view: work.retro(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:MO231 : retro.v(55) | Found counter in view:work.retro(verilog) instance extaddr[31:0] 
@N:MO231 : retro.v(649) | Found counter in view:work.retro(verilog) instance pc[31:0] 
@N:MF179 : retro.v(107) | Found 32 by 32 bit equality operator ('==') pc213 (in view: work.retro(verilog))
Encoding state machine state[0:3] (in view: work.work_rs232_sender_rtl_12000000_115200_1_system_speedbaudrate(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : rs232_sender.vhd(45) | There are no possible illegal states for state machine state[0:3] (in view: work.work_rs232_sender_rtl_12000000_115200_1_system_speedbaudrate(rtl)); safe FSM implementation is not required.
@N:MF794 :  | RAM regs_1[31:0] required 44 registers during mapping  
@N:MF794 :  | RAM regs[31:0] required 41 registers during mapping  

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 170MB peak: 171MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 153MB peak: 171MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 153MB peak: 172MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 154MB peak: 172MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 157MB peak: 172MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 156MB peak: 172MB)

@N:MO106 : rom.v(6) | Found ROM .delname. (in view: work.top(verilog)) with 136 words by 8 bits.
@N:MF794 :  | RAM regs_1[31:0] required 44 registers during mapping  
@N:MF794 :  | RAM regs[31:0] required 41 registers during mapping  
@N:MF794 :  | RAM regs_1[31:0] required 44 registers during mapping  
@N:MF794 :  | RAM regs[31:0] required 41 registers during mapping  

Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 157MB peak: 172MB)


Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:06s; Memory used current: 172MB peak: 230MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:06s		    -8.63ns		2361 /       331
   2		0h:00m:06s		    -8.63ns		2242 /       331
   3		0h:00m:06s		    -7.23ns		2243 /       331
   4		0h:00m:06s		    -6.04ns		2245 /       331
   5		0h:00m:06s		    -5.83ns		2248 /       331
   6		0h:00m:06s		    -5.83ns		2250 /       331
@N:FX271 : retro.v(55) | Replicating instance arg2_ret_6 (in view: work.retro(verilog)) with 65 loads 3 times to improve timing.
@N:FX271 : retro.v(55) | Replicating instance arg1_ret_64 (in view: work.retro(verilog)) with 65 loads 3 times to improve timing.
@N:FX271 : retro.v(55) | Replicating instance arg2_ret_64 (in view: work.retro(verilog)) with 72 loads 3 times to improve timing.
Timing driven replication report
Added 9 Registers via timing driven replication
Added 6 LUTs via timing driven replication

   7		0h:00m:07s		    -5.83ns		2265 /       340
   8		0h:00m:07s		    -5.83ns		2264 /       340


   9		0h:00m:08s		    -5.83ns		2263 /       340
Re-levelizing using alternate method
Assigned 0 out of 3089 signals to level zero using alternate method
@N:FX1016 : top.v(1) | SB_GB_IO inserted on the port ext_osc.
@N:FX1017 :  | SB_GB inserted on the net un1_hold_6_0_0. 
@N:FX1017 : retro.v(55) | SB_GB inserted on the net un1_hold_1_reto.
@N:FX1017 : retro.v(55) | SB_GB inserted on the net arg2_1_sqmuxa_reto.
@N:FX1017 :  | SB_GB inserted on the net un1_hold_4_0. 

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 182MB peak: 230MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 184MB peak: 230MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 348 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

============================== Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID     Driving Element        Drive Element Type     Fanout     Sample Instance  
--------------------------------------------------------------------------------------------
ClockId0001        ext_osc_ibuf_gb_io     SB_GB_IO               348        TX.bit_counter[0]
============================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 151MB peak: 230MB)

Writing Analyst data base /home/shaos/iCEcube2/examples/retro1s/retro1s_Implmnt/synwork/retro1s_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 181MB peak: 230MB)

Writing EDIF Netlist and constraint files
@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  
@N:FX1056 :  | Writing EDF file: /home/shaos/iCEcube2/examples/retro1s/retro1s_Implmnt/retro1s.edf 
@W:FX708 :  | Found invalid parameter 0  
@W:FX708 :  | Found invalid parameter 0  
L-2016.09L+ice40

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:09s; Memory used current: 182MB peak: 230MB)


Start final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 178MB peak: 230MB)

@W:MT246 : top.v(62) | Blackbox SB_RGBA_DRV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT420 :  | Found inferred clock top|ext_osc with period 27.31ns. Please declare a user-defined clock on object "p:ext_osc" 


##### START OF TIMING REPORT #####[
# Timing Report written on Sun Dec 30 00:05:40 2018
#


Top view:               top
Requested Frequency:    36.6 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -6.715

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
top|ext_osc        36.6 MHz      24.5 MHz      27.307        40.737        -6.715     inferred     Autoconstr_clkgroup_0
System             1.0 MHz       NA            1000.000      NA            NA         system       system_clkgroup      
========================================================================================================================
@N:MT582 :  | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack 





Clock Relationships
*******************

Clocks                    |    rise  to  rise    |    fall  to  fall    |    rise  to  fall    |    fall  to  rise  
--------------------------------------------------------------------------------------------------------------------
Starting     Ending       |  constraint  slack   |  constraint  slack   |  constraint  slack   |  constraint  slack 
--------------------------------------------------------------------------------------------------------------------
top|ext_osc  System       |  27.307      26.511  |  No paths    -       |  No paths    -       |  No paths    -     
top|ext_osc  top|ext_osc  |  27.307      -4.819  |  27.307      16.660  |  13.654      -3.196  |  13.654      -6.715
====================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: top|ext_osc
====================================



Starting Points with Worst Slack
********************************

                       Starting                                                    Arrival           
Instance               Reference       Type         Pin     Net                    Time        Slack 
                       Clock                                                                         
-----------------------------------------------------------------------------------------------------
cpu.pc[0]              top|ext_osc     SB_DFFNE     Q       pc[0]                  0.796       -6.715
cpu.pc[3]              top|ext_osc     SB_DFFNE     Q       pc[3]                  0.796       -6.612
cpu.pc[1]              top|ext_osc     SB_DFFNE     Q       pc[1]                  0.796       -6.612
cpu.pc[5]              top|ext_osc     SB_DFFNE     Q       pc[5]                  0.796       -6.539
cpu.pc[2]              top|ext_osc     SB_DFFNE     Q       pc[2]                  0.796       -6.539
cpu.arg2_ret_40        top|ext_osc     SB_DFF       Q       arg2_2_sqmuxa_reto     0.796       -4.819
cpu.arg2_ret_41[0]     top|ext_osc     SB_DFF       Q       arg2_reto_0[0]         0.796       -4.777
cpu.arg2_ret_1[0]      top|ext_osc     SB_DFF       Q       data_in_reto[4]        0.796       -4.736
cpu.arg2_ret_32        top|ext_osc     SB_DFF       Q       un1_pc_reto[0]         0.796       -4.643
cpu.arg2_ret_41[1]     top|ext_osc     SB_DFF       Q       arg2_reto_0[1]         0.796       -4.577
=====================================================================================================


Ending Points with Worst Slack
******************************

                Starting                                            Required           
Instance        Reference       Type        Pin     Net             Time         Slack 
                Clock                                                                  
---------------------------------------------------------------------------------------
cpu.res[26]     top|ext_osc     SB_DFFE     D       res_140[26]     13.498       -6.715
cpu.res[14]     top|ext_osc     SB_DFFE     D       res_140[14]     13.498       -6.684
cpu.res[10]     top|ext_osc     SB_DFFE     D       res_140[10]     13.498       -6.674
cpu.res[6]      top|ext_osc     SB_DFFE     D       res_140[6]      13.498       -6.612
cpu.res[30]     top|ext_osc     SB_DFFE     D       res_140[30]     13.498       -6.612
cpu.res[9]      top|ext_osc     SB_DFFE     D       res_140[9]      13.498       -6.601
cpu.res[22]     top|ext_osc     SB_DFFE     D       res_140[22]     13.498       -6.539
cpu.res[18]     top|ext_osc     SB_DFFE     D       res_140[18]     13.498       -6.539
cpu.res[17]     top|ext_osc     SB_DFFE     D       res_140[17]     13.498       -6.498
cpu.res[12]     top|ext_osc     SB_DFFE     D       res_140[12]     13.498       -4.827
=======================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      13.654
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         13.498

    - Propagation time:                      20.213
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -6.715

    Number of logic level(s):                9
    Starting point:                          cpu.pc[0] / Q
    Ending point:                            cpu.res[26] / D
    The start point is clocked by            top|ext_osc [falling] on pin C
    The end   point is clocked by            top|ext_osc [rising] on pin C

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
cpu.pc[0]                     SB_DFFNE     Q        Out     0.796     0.796       -         
pc[0]                         Net          -        -       1.599     -           78        
cpu.extaddr_RNICINS1[0]       SB_LUT4      I2       In      -         2.395       -         
cpu.extaddr_RNICINS1[0]       SB_LUT4      O        Out     0.558     2.953       -         
address[0]                    Net          -        -       1.371     -           56        
prog.data_1_7_0_.m63          SB_LUT4      I0       In      -         4.324       -         
prog.data_1_7_0_.m63          SB_LUT4      O        Out     0.661     4.986       -         
m63                           Net          -        -       1.371     -           2         
prog.data_1_7_0_.m70_am       SB_LUT4      I1       In      -         6.357       -         
prog.data_1_7_0_.m70_am       SB_LUT4      O        Out     0.558     6.915       -         
m70_am                        Net          -        -       1.371     -           1         
prog.data_1_7_0_.m80_ns_1     SB_LUT4      I0       In      -         8.286       -         
prog.data_1_7_0_.m80_ns_1     SB_LUT4      O        Out     0.661     8.947       -         
m80_ns_1                      Net          -        -       1.371     -           1         
prog.data_1_7_0_.m80_ns       SB_LUT4      I3       In      -         10.318      -         
prog.data_1_7_0_.m80_ns       SB_LUT4      O        Out     0.465     10.783      -         
m80_ns                        Net          -        -       1.371     -           1         
prog.data_1_7_0_.m85          SB_LUT4      I2       In      -         12.154      -         
prog.data_1_7_0_.m85          SB_LUT4      O        Out     0.558     12.712      -         
data[2]                       Net          -        -       1.371     -           13        
cpu.res_RNO_4[26]             SB_LUT4      I0       In      -         14.083      -         
cpu.res_RNO_4[26]             SB_LUT4      O        Out     0.661     14.745      -         
res_RNO_4[26]                 Net          -        -       1.371     -           1         
cpu.res_RNO_1[26]             SB_LUT4      I0       In      -         16.116      -         
cpu.res_RNO_1[26]             SB_LUT4      O        Out     0.661     16.777      -         
res_RNO_1[26]                 Net          -        -       1.371     -           1         
cpu.res_RNO[26]               SB_LUT4      I2       In      -         18.148      -         
cpu.res_RNO[26]               SB_LUT4      O        Out     0.558     18.706      -         
res_140[26]                   Net          -        -       1.507     -           1         
cpu.res[26]                   SB_DFFE      D        In      -         20.213      -         
============================================================================================
Total path delay (propagation time + setup) of 20.368 is 6.294(30.9%) logic and 14.074(69.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      13.654
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         13.498

    - Propagation time:                      20.183
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -6.684

    Number of logic level(s):                9
    Starting point:                          cpu.pc[0] / Q
    Ending point:                            cpu.res[14] / D
    The start point is clocked by            top|ext_osc [falling] on pin C
    The end   point is clocked by            top|ext_osc [rising] on pin C

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
cpu.pc[0]                       SB_DFFNE     Q        Out     0.796     0.796       -         
pc[0]                           Net          -        -       1.599     -           78        
cpu.extaddr_RNICINS1[0]         SB_LUT4      I2       In      -         2.395       -         
cpu.extaddr_RNICINS1[0]         SB_LUT4      O        Out     0.558     2.953       -         
address[0]                      Net          -        -       1.371     -           56        
prog.data_1_7_0_.m62            SB_LUT4      I0       In      -         4.324       -         
prog.data_1_7_0_.m62            SB_LUT4      O        Out     0.661     4.986       -         
m62                             Net          -        -       1.371     -           1         
prog.data_1_7_0_.m152_am_ns     SB_LUT4      I0       In      -         6.357       -         
prog.data_1_7_0_.m152_am_ns     SB_LUT4      O        Out     0.661     7.018       -         
m152_am_ns                      Net          -        -       1.371     -           1         
prog.data_1_7_0_.m152_ns        SB_LUT4      I0       In      -         8.389       -         
prog.data_1_7_0_.m152_ns        SB_LUT4      O        Out     0.661     9.051       -         
m152_ns                         Net          -        -       1.371     -           1         
prog.data_1_7_0_.m160_ns_1      SB_LUT4      I3       In      -         10.421      -         
prog.data_1_7_0_.m160_ns_1      SB_LUT4      O        Out     0.424     10.845      -         
m160_ns_1                       Net          -        -       1.371     -           1         
prog.data_1_7_0_.m160_ns        SB_LUT4      I3       In      -         12.216      -         
prog.data_1_7_0_.m160_ns        SB_LUT4      O        Out     0.465     12.681      -         
m160_ns                         Net          -        -       1.371     -           1         
prog.data_1_7_0_.m164           SB_LUT4      I2       In      -         14.052      -         
prog.data_1_7_0_.m164           SB_LUT4      O        Out     0.558     14.611      -         
data[6]                         Net          -        -       1.371     -           12        
cpu.res_RNO_0[14]               SB_LUT4      I0       In      -         15.982      -         
cpu.res_RNO_0[14]               SB_LUT4      O        Out     0.661     16.643      -         
res_RNO_0[14]                   Net          -        -       1.371     -           1         
cpu.res_RNO[14]                 SB_LUT4      I0       In      -         18.014      -         
cpu.res_RNO[14]                 SB_LUT4      O        Out     0.661     18.675      -         
res_140[14]                     Net          -        -       1.507     -           1         
cpu.res[14]                     SB_DFFE      D        In      -         20.183      -         
==============================================================================================
Total path delay (propagation time + setup) of 20.338 is 6.264(30.8%) logic and 14.074(69.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      13.654
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         13.498

    - Propagation time:                      20.172
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -6.674

    Number of logic level(s):                9
    Starting point:                          cpu.pc[0] / Q
    Ending point:                            cpu.res[10] / D
    The start point is clocked by            top|ext_osc [falling] on pin C
    The end   point is clocked by            top|ext_osc [rising] on pin C

Instance / Net                           Pin      Pin               Arrival     No. of    
Name                        Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------
cpu.pc[0]                   SB_DFFNE     Q        Out     0.796     0.796       -         
pc[0]                       Net          -        -       1.599     -           78        
cpu.extaddr_RNICINS1[0]     SB_LUT4      I2       In      -         2.395       -         
cpu.extaddr_RNICINS1[0]     SB_LUT4      O        Out     0.558     2.953       -         
address[0]                  Net          -        -       1.371     -           56        
prog.data_1_7_0_.m166       SB_LUT4      I0       In      -         4.324       -         
prog.data_1_7_0_.m166       SB_LUT4      O        Out     0.661     4.986       -         
m166                        Net          -        -       1.371     -           2         
prog.data_1_7_0_.m173_1     SB_LUT4      I1       In      -         6.357       -         
prog.data_1_7_0_.m173_1     SB_LUT4      O        Out     0.558     6.915       -         
m173_1                      Net          -        -       1.371     -           1         
prog.data_1_7_0_.m173       SB_LUT4      I3       In      -         8.286       -         
prog.data_1_7_0_.m173       SB_LUT4      O        Out     0.465     8.751       -         
m173                        Net          -        -       1.371     -           1         
prog.data_1_7_0_.m181       SB_LUT4      I2       In      -         10.122      -         
prog.data_1_7_0_.m181       SB_LUT4      O        Out     0.558     10.680      -         
data[7]                     Net          -        -       1.371     -           27        
cpu.unflag_RNISHM9          SB_LUT4      I0       In      -         12.051      -         
cpu.unflag_RNISHM9          SB_LUT4      O        Out     0.661     12.712      -         
res40_0                     Net          -        -       1.371     -           11        
cpu.res_RNO_2[10]           SB_LUT4      I0       In      -         14.083      -         
cpu.res_RNO_2[10]           SB_LUT4      O        Out     0.661     14.745      -         
res_RNO_2[10]               Net          -        -       1.371     -           1         
cpu.res_RNO_0[10]           SB_LUT4      I1       In      -         16.116      -         
cpu.res_RNO_0[10]           SB_LUT4      O        Out     0.589     16.705      -         
N_1379                      Net          -        -       1.371     -           1         
cpu.res_RNO[10]             SB_LUT4      I1       In      -         18.076      -         
cpu.res_RNO[10]             SB_LUT4      O        Out     0.589     18.665      -         
res_140[10]                 Net          -        -       1.507     -           1         
cpu.res[10]                 SB_DFFE      D        In      -         20.172      -         
==========================================================================================
Total path delay (propagation time + setup) of 20.327 is 6.253(30.8%) logic and 14.074(69.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      13.654
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         13.498

    - Propagation time:                      20.141
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -6.643

    Number of logic level(s):                9
    Starting point:                          cpu.pc[0] / Q
    Ending point:                            cpu.res[26] / D
    The start point is clocked by            top|ext_osc [falling] on pin C
    The end   point is clocked by            top|ext_osc [rising] on pin C

Instance / Net                              Pin      Pin               Arrival     No. of    
Name                           Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------
cpu.pc[0]                      SB_DFFNE     Q        Out     0.796     0.796       -         
pc[0]                          Net          -        -       1.599     -           78        
cpu.extaddr_RNICINS1[0]        SB_LUT4      I2       In      -         2.395       -         
cpu.extaddr_RNICINS1[0]        SB_LUT4      O        Out     0.558     2.953       -         
address[0]                     Net          -        -       1.371     -           56        
prog.data_1_7_0_.m70_bm_x0     SB_LUT4      I0       In      -         4.324       -         
prog.data_1_7_0_.m70_bm_x0     SB_LUT4      O        Out     0.661     4.986       -         
m70_bm_x0                      Net          -        -       1.371     -           1         
prog.data_1_7_0_.m70_bm_ns     SB_LUT4      I1       In      -         6.357       -         
prog.data_1_7_0_.m70_bm_ns     SB_LUT4      O        Out     0.589     6.946       -         
m70_bm_ns                      Net          -        -       1.371     -           1         
prog.data_1_7_0_.m80_ns_1      SB_LUT4      I1       In      -         8.317       -         
prog.data_1_7_0_.m80_ns_1      SB_LUT4      O        Out     0.558     8.875       -         
m80_ns_1                       Net          -        -       1.371     -           1         
prog.data_1_7_0_.m80_ns        SB_LUT4      I3       In      -         10.246      -         
prog.data_1_7_0_.m80_ns        SB_LUT4      O        Out     0.465     10.711      -         
m80_ns                         Net          -        -       1.371     -           1         
prog.data_1_7_0_.m85           SB_LUT4      I2       In      -         12.082      -         
prog.data_1_7_0_.m85           SB_LUT4      O        Out     0.558     12.640      -         
data[2]                        Net          -        -       1.371     -           13        
cpu.res_RNO_4[26]              SB_LUT4      I0       In      -         14.011      -         
cpu.res_RNO_4[26]              SB_LUT4      O        Out     0.661     14.673      -         
res_RNO_4[26]                  Net          -        -       1.371     -           1         
cpu.res_RNO_1[26]              SB_LUT4      I0       In      -         16.044      -         
cpu.res_RNO_1[26]              SB_LUT4      O        Out     0.661     16.705      -         
res_RNO_1[26]                  Net          -        -       1.371     -           1         
cpu.res_RNO[26]                SB_LUT4      I2       In      -         18.076      -         
cpu.res_RNO[26]                SB_LUT4      O        Out     0.558     18.634      -         
res_140[26]                    Net          -        -       1.507     -           1         
cpu.res[26]                    SB_DFFE      D        In      -         20.141      -         
=============================================================================================
Total path delay (propagation time + setup) of 20.296 is 6.222(30.7%) logic and 14.074(69.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      13.654
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         13.498

    - Propagation time:                      20.141
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -6.643

    Number of logic level(s):                9
    Starting point:                          cpu.pc[0] / Q
    Ending point:                            cpu.res[10] / D
    The start point is clocked by            top|ext_osc [falling] on pin C
    The end   point is clocked by            top|ext_osc [rising] on pin C

Instance / Net                           Pin      Pin               Arrival     No. of    
Name                        Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------
cpu.pc[0]                   SB_DFFNE     Q        Out     0.796     0.796       -         
pc[0]                       Net          -        -       1.599     -           78        
cpu.extaddr_RNICINS1[0]     SB_LUT4      I2       In      -         2.395       -         
cpu.extaddr_RNICINS1[0]     SB_LUT4      O        Out     0.558     2.953       -         
address[0]                  Net          -        -       1.371     -           56        
prog.data_1_7_0_.m166       SB_LUT4      I0       In      -         4.324       -         
prog.data_1_7_0_.m166       SB_LUT4      O        Out     0.661     4.986       -         
m166                        Net          -        -       1.371     -           2         
prog.data_1_7_0_.m173_1     SB_LUT4      I1       In      -         6.357       -         
prog.data_1_7_0_.m173_1     SB_LUT4      O        Out     0.558     6.915       -         
m173_1                      Net          -        -       1.371     -           1         
prog.data_1_7_0_.m173       SB_LUT4      I3       In      -         8.286       -         
prog.data_1_7_0_.m173       SB_LUT4      O        Out     0.465     8.751       -         
m173                        Net          -        -       1.371     -           1         
prog.data_1_7_0_.m181       SB_LUT4      I2       In      -         10.122      -         
prog.data_1_7_0_.m181       SB_LUT4      O        Out     0.558     10.680      -         
data[7]                     Net          -        -       1.371     -           27        
cpu.unflag_RNISHM9          SB_LUT4      I0       In      -         12.051      -         
cpu.unflag_RNISHM9          SB_LUT4      O        Out     0.661     12.712      -         
res40_0                     Net          -        -       1.371     -           11        
cpu.res_RNO_3[10]           SB_LUT4      I0       In      -         14.083      -         
cpu.res_RNO_3[10]           SB_LUT4      O        Out     0.661     14.745      -         
res_RNO_3[10]               Net          -        -       1.371     -           1         
cpu.res_RNO_0[10]           SB_LUT4      I2       In      -         16.116      -         
cpu.res_RNO_0[10]           SB_LUT4      O        Out     0.558     16.674      -         
N_1379                      Net          -        -       1.371     -           1         
cpu.res_RNO[10]             SB_LUT4      I1       In      -         18.045      -         
cpu.res_RNO[10]             SB_LUT4      O        Out     0.589     18.634      -         
res_140[10]                 Net          -        -       1.507     -           1         
cpu.res[10]                 SB_DFFE      D        In      -         20.141      -         
==========================================================================================
Total path delay (propagation time + setup) of 20.296 is 6.222(30.7%) logic and 14.074(69.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 179MB peak: 230MB)


Finished timing report (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 179MB peak: 230MB)

---------------------------------------
Resource Usage Report for top 

Mapping to part: ice40up5ksg48
Cell usage:
GND             3 uses
SB_CARRY        273 uses
SB_DFF          63 uses
SB_DFFE         242 uses
SB_DFFESR       1 use
SB_DFFNE        32 uses
SB_DFFSR        2 uses
SB_GB           4 uses
SB_RAM256x16    4 uses
SB_RGBA_DRV     1 use
VCC             3 uses
SB_LUT4         2259 uses

I/O ports: 5
I/O primitives: 2
SB_GB_IO       1 use
SB_IO          1 use

I/O Register bits:                  0
Register bits not including I/Os:   340 (6%)

RAM/ROM usage summary
Block Rams : 4 of 30 (13%)

Total load per clock:
   top|ext_osc: 1

@S |Mapping Summary:
Total  LUTs: 2259 (42%)

Distribution of All Consumed LUTs = LUT4 
Distribution of All Consumed Luts 2259 = 2259 

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 32MB peak: 230MB)

Process took 0h:00m:09s realtime, 0h:00m:09s cputime
# Sun Dec 30 00:05:40 2018

###########################################################]