Project Settings
Project Name retro1t_syn Implementation Name retro1t_Implmnt
Top Module [auto] Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 10000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 15 3 0 - 00m:02s - 12/12/18
9:48 PM
(premap)Complete 3 1 0 0m:00s 0m:00s 139MB 12/12/18
9:48 PM
(fpga_mapper)Complete 26 8 0 0m:13s 0m:13s 229MB 12/12/18
9:48 PM
Multi-srs Generator Complete12/12/18
9:48 PM

Area Summary
PADS 28 FLOPS 336
RAMS (v_ram) 4 CARRYS 310
LUTS (total_luts) 2183

Timing Summary
Clock NameReq FreqEst FreqSlack
top|frequency_counter_i_derived_clock[23]1.0 MHz0.9 MHz-2.555
top|int_osc_inferred_clock48.0 MHz32.9 MHz-9.557
System1.0 MHzNANA

Optimizations Summary
Combined Clock Conversion 0 / 2