3. STEbus Interface

The SCPC88 has an STEbus interface (IEEE 1000 1987). Here is a summary of the features of the bus with some notes on their implementation on the SCPC88 board. The pinout of the bus is given in Appendix B.

Table 1. STEbus Interface on the SCPC88

Signal In/Out type description implementation
A0-19 O 3s 20-bit memory address Latched from the CPU 20-bit address.
A0-11 O 3s 12-bit I/O address As above.
A0-2 O 3s 3-bit acknowledge address The SCPC88 does not handle bus-vectored interrupts, so it does not generate acknowledge cycles. It does respond to non-vectored interrupts on lines ATNRQ0*-ATNRQ5*.
D0-7 I/O 3s 8-bit data bus Driven by the CPU on write cycles, or by the slave on read cycles.
ADRSTB* O 3s Address strobe Addresses, data and command modifiers are valid before the falling edge of ADRSTB* and DATSTB*. Both strobes are active at the same time on the SCPC88.
DATSTB* O 3s Data strobe On the write cycle, valid data and CM0 are present before this is asserted. On a read cycle, CM0 high is present before it is asserted and DATSTB* then indicates to the slave that the CPU is ready to accept data.
DATACK* I o/c Data acknowledge The slave addressed by the master asserts this line to indicate that it has accepted data from a write cycle, or that its data are valid during a read cycle.
CM2—0 O 3s   Command modifiers indicating the type of bus cycle, according to the following table:
CM2,1,0
  1 1 1 memory read
  1 1 0   " write
  1 0 1 I/O read
  1 0 0  " write
  0 1 1 acknowledge
  0 1 0 )
  0 0 1 )reserved
  0 0 0 )

(Note: the acknowledge cycle is not generated by the SCPC88, therefore the SCPC88 cannot service bus-vectored interrupts)

BUSRQ0-1* O o/c Bus request Potential (temporary) bus masters request the bus from the arbiter on either of these lines. BUSRQ0* has a higher priority than BUSRQ1*.
These are not used by the SCPC88 which is a permanent bus master only.
BUSAK0-1* I in Bus acknowledge The arbiter acknowledges a request from one of two potential masters on these lines. A potential master may drive the bus only after it has received an acknowledge on the line corresponding to its request.
The SCPC88 ignores these, as it is a permanent bus master only.
TRFERR* I o/c Handshake If data from the slave are wrong ( for example a parity error ) the slave asserts TRFERR* instead of DATACK*. The SCPUB responds identically to both signals, as if no error had occurred. This signal exists in the specification for compatibility with future advances in system design.
ATNRQ0~7* I o/c Interrupts Attention request lines.
ATNRQ0-5* are used for interrupts, ATNRQ0* having highest priority. ATNRQ6* is used for disk DMA requests. ATNRQ0-5* are sent to the FE2010A interrupt lines IRQ2-7 respectively
SYSCLK O tp Clock 16 MHz system clock.
May be generated by the SCPUB, or taken from the bus.
SYSRST* O o/c Reset System reset. The SCPC88 may either generate this signal or take it from the bus.

Key:

* = signal is active low

3s = tristate

tp = totempole

oc = open-collector

Note that although the STEbus specification calls for most signals to be tristate, the PC has no specification for multiprocessing, so these are permanently enabled on the SCPC88 which must be the only master on the STEbus.

It is quite easy to use the SCPC88 on the STEbus. You will need a terminated backplane, and one or more slave boards, such as AD converters, for example. In order to comply fully with the specification the impedance of each backplane line should be 60 ohms ±10%. However, a short backplane is not likely to cause any malfunction even if its impedance varies considerably from this. A terminator is necessary because some of the lines are open-collector, and timing is critical on the strobes.

The SCPC88 configured as standard will generate all necessary bus signals. All that is required to generate a bus access is that you try to read from or write to a memory or IO location which the onboard logic defines as on the bus. See the “Memory Map” and "IO Devices" sections for details on which addresses are onboard and which are not.

To maintain compatibility with PC software, the SCPC88 will not hang if a DATACK* is absent, but will timeout after 15 processor clock cycles (3.14 microseconds when running at 4.77 MHz, 2 microseconds at 7.16 MHz) and return the data present on the STEbus (usually this will be pulled up to 0FFH).

DMA cycles generated by the PC logic chip do not use two separate read and write cycles. Instead the memory and I/O cycles are done simultaneously, which requires the use of a ribbon cable to carry the DMA control signals for the SPDC disk controller board. DMA is only used for onboard DRAM refresh, and disk transfers. There are no DMA channels available to the user.