FARADAY ELECTRONICS INC 84 DE 34386347 0000201 6
3486347 FARADAY ELECTRONICS CORP 84D 00201 D
T-52-33-03
T-52-33-15

FE2010
PC BUS CPU & PERIPHERAL CONTROLLER IC

The Faraday XT CPU controller integrated Circuit (FE2010) is a highly integrated chip that allows designers to easily build a IBM compatible PC or XT single board computer. The FE2010 has been designed for OEMs who would like to reduce cost, lower power requirements, increase reliability, and reduce board size over that of a functionally equivalent IBM PC or XT motherboard. The FE2010 replaces a total of 71 components, while reducing the size of a typical PC/XT motherboard by 77% (Appendix A).

The FE2010 replaces functionally five Intel peripheral controller ICs in a motherboard (8284 Clock Generator, 8288 Bus Controller, 8259A Interrupt controller, 8237A DMA controller & 8253 Timer). In addition, it supports both 64K and 256K memory types and has an internal configuration register to replace external switches in the board design.

The FE2010 is a 2 micron CMOS gate-array packaged in an 84 Pin J-type Leaded Surface Mount Plastic Chip Carrier (mating socket Burndy part number Q1LE84P10).


DATA BUS <=> DATA BUS BUFFER   PARITY GENERATOR --> PARITY OUT
<-- PARITY IN
 
IRQ2-7 ==>INTERRUPT CONTROLPARITY CONTROL
APNMI -->
I/O CHK -->
NMI CONTROLSPEAKER LOGIC
IO DECODE KEYBOARD
|
V
I/O RDY -->
READY <--
WAIT STATE GENERATORKEYBOARD SCAN CODE
AND INTERRUPT LOGIC
--> KEYBOARD
 
S0, S1, S2 ==>BUS CONTROLSYSTEM CONFIGURATION REGISTER <-- DISPLAY TYPE
 
4-CHANNEL DMA <-- DRQ 1, 2, 3
==> NDACK 0, 1, 2, 3
--> EOP
3-CHANNEL TIMER
 
XTAL -->
NREST -->
CLOCK GENERATOR --> OSC
--> CLEAR
--> CLOCK

FE2010 block diagram


FE2010 pinout

VDD --> -- -- -- -- -- -- -- -- -- -- -- +                
VSS --- -- -- -- -- -- -- -- -- -- -- + | + -- -- -- -- -- -- -- -- -- -- --> RS1
RS2 <-- -- -- -- -- -- -- -- -- -- + | | | + -- -- -- -- -- -- -- -- -- --> RS0
RS3 <-- -- -- -- -- -- -- -- -- + | | | | | + -- -- -- -- -- -- -- -- --> CAS
NRAMS <-- -- -- -- -- -- -- -- + | | | | | | | + -- -- -- -- -- -- -- <-- IRQ7
NEPSL <-- -- -- -- -- -- -- + | | | | | | | | | + -- -- -- -- -- -- <-- IRQ6
NBIOCS <-- -- -- -- -- -- + | | | | | | | | | | | + -- -- -- -- -- <-- IRQ5
SLAD <-- -- -- -- -- + | | | | | | | | | | | | | + -- -- -- -- <-- IRQ4
NUSCS <-- -- -- -- + | | | | | | | | | | | | | | | + -- -- -- <-- IRQ3
INT <-- -- -- + | | | | | | | | | | | | | | | | | + -- -- <-- IRQ2
A64K --> -- + | | | | | | | | | | | | | | | | | | | + -- <-- S0
    11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75    
VID0 <-> 12 FE2010
FARADAY
08014900
74 <-- S1
VID1 <-> 13 73 <-- S2
SPEAKR <-- 14 72 --> DTR
NREST --> 15 71 --> NDEN
UNUSED --> 16 70 --> ALE
READY <-- 17 69 --> BALE
CLEAR <-- 18 68 --> NMEMW
CLOCK <-- 19 67 --> NMEMR
OSC <-- 20 66 --> NIOW
X2 <-- 21 65 --> NIOR
VSS --- 22 64 -- VSS
X1 --> 23 63 --> NDAK0
NRQGT <-> 24 62 --> NDAK1
KBCLK <-> 25 61 --> NDAK2
KBDA <-> 26 60 --> NDAK3
NIOCK --> 27 59 --> EOP
IORDY --> 28 58 <-- DRQ1
APNMI --> 29 57 <-- DRQ2
AEN <-- 30 56 <-- DRQ3
NMI <-- 31 55 <-> A19
PTYIN --> 32 54 <-> A18
      33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53    
PTYOUT -- -- + | | | | | | | | | | | | | | | | | | | + -- <-> A17
AD0 <-> -- -- + | | | | | | | | | | | | | | | | | + -- -- <-> A16
AD1 <-> -- -- -- + | | | | | | | | | | | | | | | + -- -- -- <-> A15
AD2 <-> -- -- -- -- + | | | | | | | | | | | | | + -- -- -- -- <-> A14
AD3 <-> -- -- -- -- -- + | | | | | | | | | | | + -- -- -- -- -- <-> A13
AD4 <-> -- -- -- -- -- -- + | | | | | | | | | + -- -- -- -- -- -- <-> A12
AD5 <-> -- -- -- -- -- -- -- + | | | | | | | + -- -- -- -- -- -- -- <-> A11
AD6 <-> -- -- -- -- -- -- -- -- + | | | | | + -- -- -- -- -- -- -- -- <-> A10
AD7 <-> -- -- -- -- -- -- -- -- -- + | | | + -- -- -- -- -- -- -- -- -- <-> A9
VSS -- -- -- -- -- -- -- -- -- -- -- + | + -- -- -- -- -- -- -- -- -- -- <-> A8
                          + -- -- -- -- -- -- -- -- -- -- -- -- VDD

PIN DESCRIPTION:

PINTYPESYMBOLFUNCTION
1-VDDPOWER: +5 volts supply
2-VSSGROUND
3ORS2RAS 2
RAS signal for RAM bank 2
Active high
4ORS3RAS 3
RAS signal for RAM bank 3
5ONRAMS RAM DECODE
Decode for on board RAM
RAM size can be:
4 banks of 64K RAMS (256K total memory)
4 banks of 256K RAMS (640K total memory)
1 bank of 256K RAMS (256K total memory
Active low
6ONEPSLPROM DECODE
Top 64K decode (F0000 to FFFFF)
Active low
7ONBIOCSBIOS ROM chip enable
Top 8K decode (FE000 to FFFFF)
Active low
8OSLADADDRESS SELECT
Select signal for dynamic RAM address multiplexer
Low = lower address bits
High = higher address bits
Active high
9ONUSCSUSER PROM SELECT
F0000 to F5FFF
Active low
10OINTINTERRUPT TO CPU (8088)Active high
11IA64KRAM TYPE SELECT
Jumper for RAM type
Low = 256K RAMS
High = 64K RAMS
12I/OVID0VIDEO TYPE 0
Video type jumper 0
13I/OVID1VIDEO TYPE 1
Video type jumper 1
VID1	VID0	Video type
0	0	None
0	1	4O × 25 Color
1	0	80 × 25 Color
1	1	Monochrone or
		Monochrome and Color
14OSPEAKERDATA TO SPEAKER
15INRESTRESET IN
External reset in to generate reset to system
Active low
16I---UNUSED
Should be left open
17OREADYREADY TO CPU (8088)Active high
18OCLEARRESET TO CPU (8088) AND EXPANSION BUSActive high
19OCLOCKCLOCK TO CPU (8088) AND EXPANSION BUS
4.77 MHz clock
20OOSCOSC TO EXPANSION BUS
14.31818 MHz clock
21OX2CRYSTAL OUTPUT
22-VSSGROUND
23IX1CRYSTAL INPUT
24I/ONRQGTREQUEST/GRANT TO CPU (8088) FOR BUSActive low
25I/OKBCLKKEYBOARD CLOCK
Clock to and from keyboard
26I/OKBDAKEYBOARD DATA
Data to and from keyboard
Active high
27INIOCKERROR FROM EXPANSION BUSActive low
28IIORDYREADY FROM EXPANSION BUSActive high
29IAPNMINMI FROM CO-PROCESSOR (8087)Active high
30OAENDMA CYCLE
Signal to indicate that the current bus cycle is a DMA cycle
Active high
31ONMINON MASKABLE INTERRUPT TO CPU (8088)
NMI generated by 8087, memory parity error or error from bus (NIOCK)
Active high
32IPTYINPARITY BIT FROM PARITY RAM
33PPTYOUTPARITY BIT TO PARITY RAM
34I/OAD-0ADDRESS/DATA BUS
35I/OAD-1
36I/OAD-2
37I/OAD-3
38I/OAD-4
39I/OAD-5
40I/OAD-6
41I/OAD-7
42-VSSGROUND
43-VDDPOWER: + 5 volts supply
44I/OA-8ADDRESS BUS
45I/OA-9
46I/OA-10
47I/OA-11
48I/OA-12
49I/OA-13
50I/OA-14
51I/OA-15
52I/OA-16
53I/OA-17
54I/OA-18
55I/OA-19
56IDRQ3DMA REQUEST LINE 3Active high
57IDRQ2DMA REQUEST LINE 2Active high
58IDRQ1DMA REQUEST LINE 1Active high
59OEOPEND OF PROCESS INDICATOR FOR DMAActive high
60ONDAK3DMA ACKNOWLEDGE FOR CHANNEL 3Active low
61ONDAK2DMA ACKNOWLEDGE FOR CHANNEL 2Active low
62ONDAK1DMA ACKNOWLEDGE FOR CHANNEL 1Active low
63ONDAK0DMA ACKNOWLEDGE FOR CHANNEL 0
Indicates a refresh cycle
Active low
64-CSSGROUND
65ONIORI/O READ COMMANDActive low
66ONIOWI/O WRITE COMMANDActive low
67ONMEMRMEMORY READ COMMANDActive low
68ONMEMWMEMORY WRITE COMMANDActive low
69OBALEADDRESS LATCH ENABLE
Address latch signal to expansion bus
Active high
70OALEADDRESS LATCH ENABLE
Address latch signal to address latches
Active high
71ONDEN DATA ENABLE TO TRANSCEIVERS FOR LOCAL OR SYSTEM BUS
Signal to enable data transceiver
Active low
72ODTR DATA TRANSMIT OR RECEIVE
Signal to data transceiver to indicate a write cycle
Active high
73IS2CPU (8088) STATUS BITS
74IS1
75IS0
76IIRQ2INTERRUPT REQUEST INPUT 2Active high
77IIRQ3INTERRUPT REQUEST INPUT 3Active high
78IIRQ4INTERRUPT REQUEST INPUT 4Active high
79IIRQ5INTERRUPT REQUEST INPUT 5Active high
80IIRQ6INTERRUPT REQUEST INPUT 6Active high
81IIRQ7INTERRUPT REQUEST INPUT 7Active high
82OCASRAM CAS
CAS signal for RAM memory
Active high
83ORS0RAS 0
RAS signal for RAM bank 0
Active high
84ORS1RAS 1
RAS signal for RAM bank 1
Active high

FUNCTIONAL DESCRIPTION - FE2010

INTERRUPT CONTROLLER

The interrupt controller is the equivalent of an 8259A interrupt controller. Interrupt 0 is tied to the keyboard port and interrupt 1 is tied to timer 0.

WAIT STATE GENERATOR

The wait state generator generates 1 wait state on all CPU I/O and DMA operations. It also synchronizes the external ready that may be used to generate wait states.

BUS CONTROL

The bus controller is the equivalent of an 8288 for CPU bus operations, and generates the bus controls for DMA operations. Memory decodes including RAS, CAS generation are provided by this block.

CLOCK GENERATOR

The clock generator is the equivalent of a 8284A clock generator. It also generates the clock for the timer.

PARTY GENERATOR

The parity generator checks and generates parity for RAM memory.

KEYBOARD PORT

The keyboard port connects to an IBM compatible keyboard.

DMA

The DMA is the equivalent of an 8237 DMA controller. Channel 0 is reserved for the refresh of RAM memory.

TIMER

The timer is the equivalent of a 8253 timer. Channel 0 is tied to interrupt 0, channel 1 is used to generate refresh, and channel 2 is used for the speaker port.

PIO

The PIO is used to for system configuration, to control the keyboard and speaker ports, and to enable error checks.


1	CLOCK HIGH PERIOD					 83 ns
2	CLOCK LOW PERIOD					127 ns
3	CLOCK RISE TIME						<10 ns
4	CLOCK FATT, TIME					<10 ns
5	OSC RISE TIME						<10 ns
6	OSC EALL TIME						<10 ns
7	CLOCK \_ CLEAR \_					 22 ns
8	CLOCK _/ READY \_					 81 ns
9	CLOCK _/ READY _/					 67 ns
10	READY _/ CLOCK _/					143 ns
11	OSC   \_ CLOCK _/					 15 ns
12	OSC   \_ CLOCK \_					 28 ns
13	AD(7:O) =x= PTYOUT =x=					 64 ns
14	NIOR \_ AD(7:0) =x= INVALID				454 ns
15	NIOR _/ AD(7:0) =x= INVALID				 40 ns
16	CLOCK \_ NIOR, NIOW, NMEMR, NMEMW _/ (AEN=O)		 24 ns
17	CLOCK \_ NIOR, NIOW, NMEMR, NMEMW \_ (AEN=0)		 32 ns
18	CLOCK \_ NDAK0, NDAK1, NDAK2, NDAK3 _/			 42 ns
19	CLOCK \_ NDAK0, NDAK1, NDAK2, NDAK3 \_			 59 ns
20	CLOCK _/ EOP  _/					136 ns
21	CLOCK _/ EOP  \_					145 ns
22	CLOCK _/ BALE \_					 26 ns
23	RAS0,1,2,3 _/ SLAD _/					 31 ns
24	ALE   \_ AD(7:0) =x= INVALID (AEN=1)			 24 ns
25	BALE  \_ ALE \_						  7 ns
26	CLOCK _/ DTR _/						 17 ns
27	CLOCK _/ NDEN _/ (READ)					 21 ns
28	CLOCK _/ NDEN _/ (WRITE)				 99 ns
29	X1 _/ CLOCK _/						 47 ns

Absolute Maximum Ratings

TA = +25°C

Power supply voltageVDD-0.5 V to +7.0V
Power dissipationPDMAXW
Input voltageVI-0.5 V to VDD +0.3V
Output voltageVO-0.5 V to VDD +0.3V
Operating temperatureTOPT°C
Storage temperatureTSTG-65 to +150°C

Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational sections of this specification. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance

ParameterLimits
SymbolMinMaxUnit
Input capacitanceCI15pF
I/O capacitanceCIO15pF

Test Conditions: TA=+25 °C, VDD = 0 V, fc = 1 MHz, Unmeasured pins returned to 0 V


DC Characteristics

TA = 0 to 70 °C, VDD = 5 V ± 5%

PARAMETER CONDITION MIN MAX PINS
VIL VDD=5V+/-5% VSS 0.8 029=APNMI, 011=A64K, 058=DRQ1, 057=DRQ2, 056=DRQ3, 028=IORDY, 076=IRQ2, 077=IRQ3, 078=IRQ4, 079=IRQ5, 080=IRQ6, 081=IRQ7, 027=NIOCK, 016=NTSTCR, 032=PTYIN, 075=S‑0, 074=S‑1, 073=S‑2, 012=VID0, 013=VID1
VIL VDD=5V+/-5% VSS 0.8 034=AD‑0, 035=AD‑1, 036=AD‑2, 037 AD‑3, 038=AD‑4, 039=AD‑5, 040=AD‑6, 041=AD‑7, 049=AH‑0, 050=AH‑1, 051=AH‑2, 052=AH‑3, 053=AH‑4, 054=AH‑5, 055=AH‑6, 044=AL‑0, 045=AL‑1, 024=NRQGT
VIL VDD=5V+/-5% VSS 0.3*VDD 023=X1
VIL VDD=5V+/-5% VSS 015=NREST
VIL VDD=5V+/-5% VSS 1.0 025=KBCLK, 026=KBDA
VIH VDD=5V+/-5% 2.0 VDD 029=APNMI, 011=64K, 058=DRQ1, 057=DRQ2, 056=DRQ3, 028=IORDY, 076=IRQ2, 077=IRQ3, 078=IRQ4, 079=IRQ5, 080=IRQ6, 081=IRQ7, 027=NIOCK, 016=NTSTCR, 032=PTYIN, 075=S‑0, 074=S‑1, 073=S‑2, 012=VID0, 013=VID1
VIH VDD=5V+/-5% 2.0 VDD 034=AD‑0, 035=AD‑1, 036=AD‑2, 037=AD‑3, 038=AD‑4, 039=AD‑5, 040=AD‑6, 041=AD‑7, 049=AH‑0, 050=AH‑1, 051=AH‑2, 052=AH‑3, 053=AH‑4, 054=AH‑5, 055=AH‑6, 044=AL‑0, 045=AL‑1, 024=NRQGT
VIH VDD=5V+/-5% 0.7*VDD VDD 023=X1
VIH VDD=5V+/-5% VDD 015=NREST
VIH VDD=5V+/-5% 4.0 VDD 025=KBCLK, 026=KBDA
IIL VIN=0.0V -10µA -300µA 029=APNMI, 011=A64K 058=DRQ1, 057=DRQ2, 056=DRQ3, 028=IORDY, 076=IRQ2, 077=IRQ3, 078=IRQ4, 079=IRQ5, 080=IRQ6, 081=IRQ7, 027=NIOCK, 016=NTSTCR, 032=PTYIN, 075=S‑0, 074=S‑1, 073=S‑2, 012=VID0, 013=VID1
IIL VIN=0.0V -10µA 034=AD‑0, 035=AD‑1, 036=AD‑2, 037=AD‑3, 038=AD‑4, 039=AD‑5, 040=AD‑6, 014=AD‑7, 049=AH‑1, 050=AH‑1, 051=AH‑2, 052=AH‑3, 053=AH‑4, 054=AH‑5, 055=AH‑6, 044=AL‑0, 045=AL‑1, 024=NRQGT
IIL VIN=0.0V -10µA 023=X1
IIL VIN=0.0V -10µA 025=KBCLK, 026=KBDA
IIH VIN=VDD 40µA 029=APNMI, 011=A64K, 058=DRQ1, 057=DRQ2, O56=DRQ3, 028=IORDY, O76=IRQ2, 077=IRQ3, 078=IRQ4, 079=IRQ5, 080=IRQ6, 081=IRQ7, 027=NIOCK, 016=NTSTCR, 032=PTYIN, 075=S‑0, 074=S‑1, 073=S‑2, 012=VIDO, 013=VID1
IIH VIN=VDD 10µA O34=AD‑0, 035=AD‑1 O36=AD‑2, 037=AD‑3, 038=AD‑4, 039=AD‑5, 04.0=AD‑6, 041=AD‑7, 049=AD‑0, 050=AH‑1, 051=AH‑2, 052=AH‑3, 053=AH‑4, 054=AH‑5, 055=AH‑6, 044=AL‑0, 045=AL‑1, 024=NRQGT
IIH VIN=VDD 10µA 023=X1
IIH VIN=VDD 10µA 025=KBCLK, 026=KBDA
VOL IOL=2.0mA 0.4V 030=AEN, 070=ALE, 069=BALE, 018=CLEAR, 072=DTR, 059=EOP, 010=INT, 007=NBIOCS, 063=NDAK0, 062=NDAK1, 061=NDAK2, 060=NDAK3, 071=NDEN, 006=NEPSL, 065=NIOR, 066=NIOW, 067=NMEMR, 068=NMEMW, 031=NMI, 005=NRAMS, 009=NUSCS, 033=PTYOUT, 017=READY
VOL IOL=4.0mA 0.4V 082=CAS, 019=CLOCK, 020=OSC, 083=RSO, 084=RS1, 003=RS2, 004=RS3 , 008= SLAD, 014= SPEAKR
VOL IOL=4.0mA 0.4V O46=AM‑0, 047=AM‑1, 048=AM‑2
VOL IOL=4.0mA 0.4V 025=KBCLK, 026=KBDA, 024=NRQGT
VOL IOL=8.0mA 0.4V 021=X2
VOL IOL=4.0mA 0.4V 034=AD‑0, 035=AD‑1, 036=13‑2, 037=AD‑3, 038=AD‑4, 039=AD‑5, 04‑0=AD‑6, 041=AD‑7, 049=AH‑0, 050=AH‑1, 051=AH‑2, 052=AH‑3, 053=AH‑4, 054=AH‑5, 055=AH‑6, 044=AL‑0, 045=AL‑1
VOH IOH=-2mA 2.4V 030=AEN, 070=ALE, 069=BALE, 018=CLEAR, 072=DTR, 059=EOP, 010=INT, 007=NBIOCS, 063=NDAKO, 062=NDAK1, 061=NDAK2, 060=NDAK3, 071=NDEN, 006=NEPSL, 065=NIOR, 066=NIOW, 067=NMEMR, 068=NMEMW, 03=NMI, 005=NRAMS, 009=NUSCS, 033=PTYOUT, 017=READY
VOH IOH=-4mA 2.4V 082=CAS, 019=CLOCK, 020=OSC, 083=RSO, 084=RSI, 003=RS2, 004=RS3, 008=SLAD, 014=SPEAKR
VOH IOH=-4mA 2.4V 046=AM‑0, 047=AM‑1, 048=AM‑2
VOH N/A N/A 025=KBCLK, 026=KBDA, 024=NRQGT
VOH IOH=-8mA 2.4V 021=X2
VOH IOH=-12mA 2.4V 034=AD‑0, 035=AD‑1, 036=AD‑2, 037=AD‑3, 038=AD‑4, 039=AD‑5, 040=AD‑6, 041=AD‑7, 049=AH‑0, 050=AH‑1, 051=AH‑2, 052=AH‑3, 053=AH‑4, 054=AH‑5, 055=AH‑6, 044=AL‑0, 045=AL‑1
IOZ 0V<VOUT<VDD -10µA 10µA 045=AM‑0, 047=AM‑1, 048=AM‑2, 025=KBCLK, 026=KBDA, 024=NRQGT
IOZ 0V<VOUT<VDD -90µA -1.0µA 034=AD‑0, 035=AD‑1, 036=AD‑2, 037=AD‑3, 038=AD‑4, 039=AD‑5, 04‑0=AD‑6, 041=AD‑7, 049=AH‑0, 050=AH‑1, 051=AH‑2, 052=AH‑3, 053=AH‑4, 054=AH‑5, 055=AH‑6, 044=AL‑0, 045=AL‑1
IDD VDD=5.25V

PROGRAMMING

The FE2010 accepts I/O read/write commands from the CPU.

I/O Address Map

Address		Use
000-00F		DMA controller
020-021		Interrupt controller
040-043		Timer
060-063		PIO
081-083		DMA page registers
0A0		NMI mask register
100-1FF		Reserved

The timer is programmed the same as the 8253 timer, the DMA controller is programmed the same as the 8237 DMA controller, and the interrupt controller is programmed the same as the 8259 interrupt controller.

PIO

The PIO is the equivalent of the 8255 PIO, but it is configured in a fixed way for system configuration, controlling the speaker port, and as a keyboard port.

Address	Use
060 (read)	Keyboard Data Register 
O61		Control Register
O62		Switch Register 
063 (write)	Configuration Register

Keyboard Data Register

The Keyboard Data Register is a read only register that is used to read data from the keyboard. When a character is in the register, interrupt 1 will be sent to the interrupt controller. The register may be cleared by setting bit 7 of the control register.

Control Register (061)

Data Bit	Use
0		Gate speaker timer channel
1		Gate speaker data
2		Switch register select
3		Not used
4		Disable parity check
5		Disable I/O check
6		Enable keyboard clock
7		Clear Keyboard Data Register

Switch Register (Write) (062)

The switch register is used for system configuration. Bits 0-3, 6 and 7 are read/write. Bits 4 and 5 are the VID0 and VID1 pin.

Data Bit	Use
O		Not used
1		8087 installed
2-3		System memory
4-5		Video type
6-7		# of floppies

Switch Register (Read) (062)

When the switch register is read the data is multiplexed on bits 0-3 of the data bus. The muxtiplexing is controlled by bit 2 of the Control Register.

Control register bit 2		Switch Register Mux
	0			Bits 4-7
	1			Bits 0-3

Data Bit	Control Register bit 2 = 1	Control Register bit 2 = 0
O		Switch Register bit 0		Switch Register bit 4
2		Switch Register bit 1		Switch Register bit 5
2		Switch Register bit 2		Switch Register bit 6
3		Switch Register bit 3		Switch Register bit 7
4		Timer 2 Output			Timer 2 Output
5		Timer 2 Output			Timer 2 Output
6		I/O Check			I/O Check
7		Parity Check			Parity Error

Configuration Register (063)

The configuration register is a write only register that is used for configuartion. If bit 3 is written, this register and the Switch register are locked in that they may not be written to. This lock is removed by a system reset.

Data Bit	Use
0		Enable parity
1		8087 present (enable 8087 NMI)
2		256K RAMS
3		Lock register
4-7		Not used

Page Registers (081-083)

The page registers are write only registers used to generate address bits 16-19 during a DMA transfer

Address		Page Register
81		DMA Channel 2 
82		DMA Channel 3
83		DMA Channel 1

O		DMA Address 16
1		DMA Address 17 
2		DMA Address 18
3		DMA Address 19

NMI Mask Register (0A0)

The NMI Mask Register is used to enable the NMI to the CPU (8088).

Data Bit	Use
0-6		Not used
7		Enable NMI

APPENDIX A

Chip Replacement Chart FE2010

8288			74LS175 (2)		74LS74 (4)
8259A			74LS138 (3)		74LS30 (2)
8284A			74LS244 (2)		74LS00 (1)
8237A (5)		74LS670			74LS08 (3)
8253 (5)		74LS322			74LS158 (2)
8255A (5)		74LS125 (2)		74LS139
DELAY-LINE (1)		74LS10			74LS32
74S280			74LS11			74S08
74LS373 (2)		74LS04 (4)		74LS14
74LS245 (3)		74LS02 (1)		SWITCHES (2)
						RESISTORS (10)

No. of chips replaced = 71


APPLICATION NOTE
SBC DESIGN BASED ON FE2010

This application note describes an 8088 based PC BUS Single Board computer design. This SBC is one of Faraday's board level product called MICRO PC and utilizes the FE2010 I.C.

Configuration:

The block diagram of the SBC is shown in Fig AP-1 while Fig AP-2 shows the schematics of the board design.


Figure AP-1. Block diagram of PC bus SBC design


Figure AP-2


Figure AP-3