--13/12/2018 --K.SAI CHARAN --this module will be used for configuring the camera registers(fps,dsp,downsampling....) --further there might arise a need to add 2 other configuration registers(1. downsampling 2.qvga) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ENTITY i2c is port( clk_i2c: in std_logic;--400kHz clk sda: inout std_logic; scl: out std_logic); END i2c; ARCHITECTURE fsm OF i2c IS signal reg_data_1: std_logic_vector(7 downto 0) :="00100000"; --COM 7 for RGB output signal reg_data_2: std_logic_vector(7 downto 0) :="00001011"; --COM 15 FOR RGB 444 signal reg_data_3: std_logic_vector(7 downto 0) :="01000000"; --RGB444 FOR RGB 444 signal reg_address_1: std_logic_vector(7 downto 0) :="01001000"; -- registers signal reg_address_2: std_logic_vector(7 downto 0):="00000010"; -- registers signal reg_address_3: std_logic_vector(7 downto 0):="00110001"; -- registers signal state: integer range 0 to 16 :=0; signal slave_addwr: std_logic_vector(7 downto 0) :="01000010"; signal bit_counter: integer range 0 to 7 :=0; signal slave_ack: std_logic :='0'; signal state_count: integer range 0 to 40 := 0 ; BEGIN PROCESS(clk_i2c) BEGIN CASE state IS WHEN 0=> scl<='1'; --initial condition sda<='1'; state<=1; WHEN 1=> scl<='1'; -- start sending the slave address sda<='0'; state<=2; WHEN 2=> scl<='0'; sda<=slave_addwr(bit_counter); state<=3; WHEN 3=> scl<='1'; sda<=slave_addwr(bit_counter); IF (bit_counter<8) THEN bit_counter<=bit_counter+1; state<=2; ELSE bit_counter<=0; state<=4; END IF; WHEN 4=> scl<='0'; state<=5; WHEN 5=> scl<='1'; IF(sda='0')THEN --ACK state<=6; ELSE state<=0; END IF; --address transmission ends here ---------------------------------------------------------------------------------------------------- WHEN 6=> scl<='1'; -- start sending the register address sda<='0'; state<=7; WHEN 7=> scl<='0'; IF(state_count=0)THEN sda<=reg_address_1(bit_counter); ELSIF(state_count=1)THEN sda<=reg_address_2(bit_counter); ELSE sda<=reg_address_3(bit_counter); END IF; state<=8; WHEN 8=> scl<='1'; IF(state_count=0)THEN sda<=reg_address_1(bit_counter); ELSIF(state_count=1)THEN sda<=reg_address_2(bit_counter); ELSE sda<=reg_address_3(bit_counter); END IF; IF (bit_counter<8) THEN bit_counter<=bit_counter+1; state<=7; ELSE bit_counter<=0; state<=9; END IF; WHEN 9=> scl<='0'; state<=10; WHEN 10=> scl<='1'; IF(sda='0')THEN --ACK state<=11; ELSE state<=0; END IF; --address transmission ends here ---------------------------------------------------------------------------------------------------- WHEN 11=> scl<='0'; -- data transmission start IF(state_count=0)THEN sda<=reg_data_1(bit_counter); ELSIF(state_count=1)THEN sda<=reg_data_2(bit_counter); ELSE sda<=reg_data_3(bit_counter); END IF; state<=12; WHEN 12=> scl<='1'; IF(state_count=0)THEN sda<=reg_data_1(bit_counter); ELSIF(state_count=1)THEN sda<=reg_data_2(bit_counter); ELSE sda<=reg_data_3(bit_counter); END IF; IF(bit_counter<8)THEN bit_counter<= bit_counter+1; state<=11; ELSE bit_counter<=0; state<=13; END IF; WHEN 13=> scl<='0'; state<=14; WHEN 14=> scl<='1'; IF(sda='0')THEN --ACK state<=15; ELSE state<=0; END IF; --DATA transmission ends here WHEN 15=> scl<='1'; state<=16; state_count<= state_count+1; WHEN 16=> scl<='1'; sda<='1'; IF(state_count< 3)THEN state<=0; --prepares for next transmission ELSE state<=16; --stops transmission END IF; END CASE; END PROCESS; END fsm;