top Project Status (07/20/2016 - 00:33:37)
Project File: fpga_v1.xise Parser Errors: No Errors
Module Name: amplitude_offset Implementation State: Synthesized
Target Device: xc3s200a-4vq100
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Dateśr. lip 20 00:33:15 2016

Date Generated: 07/20/2016 - 00:33:37