System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
LD_LIBRARY_PATH /opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64 /opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64 /opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64 /opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64
PATH /opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games:
/opt/microchip/xc16/v1.25/bin:
/opt/microchip/xc16/v1.26/bin:
/opt/microchip/xc16/v1.30/bin:
/opt/microchip/xc8/v1.42/bin
/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games:
/opt/microchip/xc16/v1.25/bin:
/opt/microchip/xc16/v1.26/bin:
/opt/microchip/xc16/v1.30/bin:
/opt/microchip/xc8/v1.42/bin
/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games:
/opt/microchip/xc16/v1.25/bin:
/opt/microchip/xc16/v1.26/bin:
/opt/microchip/xc16/v1.30/bin:
/opt/microchip/xc8/v1.42/bin
/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games:
/opt/microchip/xc16/v1.25/bin:
/opt/microchip/xc16/v1.26/bin:
/opt/microchip/xc16/v1.30/bin:
/opt/microchip/xc8/v1.42/bin
XILINX /opt/Xilinx/14.7/ISE_DS/ISE/ /opt/Xilinx/14.7/ISE_DS/ISE/ /opt/Xilinx/14.7/ISE_DS/ISE/ /opt/Xilinx/14.7/ISE_DS/ISE/
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   top.prj  
-ifmt   mixed MIXED
-ofn   top  
-ofmt   NGC NGC
-p   xc3s200a-4-vq100  
-top   top  
-opt_mode Optimization Goal Speed SPEED
-opt_level Optimization Effort 1 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy Soft NO
-netlist_hierarchy Netlist Hierarchy As_Optimized as_optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets ALLCLOCKNETS
-read_cores Read Cores YES YES
-sd Cores Search Directories {"ipcore_dir" }  
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-mult_style   Auto AUTO
-iobuf   YES YES
-max_fanout   500 500
-bufg   24 24
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Yes YES
-use_sync_set   Yes YES
-use_sync_reset   Yes YES
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc3s200a-vq100-4 None
-sd Macro Search Path ipcore_dir None
-uc   ipcore_dir/pa_clk_dcm_arwz.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ol Place & Route Effort Level (Overall) high high
-xe Placer Extra Effort Map CONTINUE  
-ir Use RLOC Constraints OFF OFF
-ignore_keep_hierarchy Allow Logic Optimization Across Hierarchy TRUE FALSE
-t Starting Placer Cost Table (1-100) Map 1 0
-cm Optimization Strategy (Cover Mode) speed area
-intstyle   ise None
-o   top_map.ncd None
-pr Pack I/O Registers/Latches into IOBs b off
-p   xc3s200a-vq100-4 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-t   1 1
-xe   c None
-intstyle   ise  
-w   true false
-pl Placer Effort Level (Overrides Overall Level) high std
-rl Router Effort Level (Overrides Overall Level) high std
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz/2491.843 MHz Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz/2488.835 MHz Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz/2480.757 MHz Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz/2539.195 MHz
Host michal-X555LJ michal-X555LJ michal-X555LJ michal-X555LJ
OS Name LinuxMint LinuxMint LinuxMint LinuxMint
OS Release Linux Mint 17.3 Rosa Linux Mint 17.3 Rosa Linux Mint 17.3 Rosa Linux Mint 17.3 Rosa