mux Project Status (05/11/2019 - 08:56:09) | |||
Project File: | Blitz.xise | Parser Errors: | No Errors |
Module Name: | mux | Implementation State: | Fitted |
Target Device: | xc9572xl-5VQ64 |
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No Errors |
Product Version: | ISE 14.7 |
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5 Warnings (3 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sat May 11 08:56:02 2019 | 0 | 5 Warnings (3 new) | 1 Info (1 new) | |
Translation Report | Current | Sat May 11 08:56:05 2019 | 0 | 0 | 0 | |
CPLD Fitter Report (Text) | Current | Sat May 11 08:56:06 2019 | 0 | 2 Warnings (1 new) | 0 | |
Power Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
IBIS Model | Out of Date | Fri Apr 19 09:40:02 2019 | |
Post-Fit Simulation Model Report | Out of Date | Fri Apr 19 09:40:01 2019 |