Design Name | mux |
Device, Speed (SpeedFile Version) | XC9572XL, -5 (3.0) |
Date Created | Sat May 11 08:56:08 2019 |
Created By | Timing Report Generator: version P.20131013 |
Copyright | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
---|---|
Min. Clock Period | 10.000 ns. |
Max. Clock Frequency (fSYSTEM) | 100.000 MHz. |
Limited by Clock Pulse Width for RW_N | |
Clock to Setup (tCYC) | 5.600 ns. |
Pad to Pad Delay (tPD) | 6.000 ns. |
Setup to Clock at the Pad (tSU) | 1.700 ns. |
Clock Pad to Output Pad Delay (tCO) | 11.000 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
TS1001 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 5.6 | 7 | 7 |
AUTO_TS_P2P | 0.0 | 11.0 | 249 | 249 |
AUTO_TS_P2F | 0.0 | 4.8 | 10 | 10 |
AUTO_TS_F2P | 0.0 | 9.9 | 28 | 28 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
cntr<0>.Q to cntr<1>.D | 0.000 | 5.600 | -5.600 |
cntr<0>.Q to cntr<2>.D | 0.000 | 5.600 | -5.600 |
cntr<0>.Q to cntr<3>.D | 0.000 | 5.600 | -5.600 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
CLK to DSACK0 | 0.000 | 11.000 | -11.000 |
RW_N to DSACK0 | 0.000 | 9.600 | -9.600 |
RW_N to DSACK1 | 0.000 | 9.600 | -9.600 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
AS to dram_config_sel.D | 0.000 | 4.800 | -4.800 |
ECS to dram_config_sel.D | 0.000 | 4.800 | -4.800 |
FC0 to dram_config_sel.D | 0.000 | 4.800 | -4.800 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
cntr<0>.Q to DSACK0 | 0.000 | 9.900 | -9.900 |
cntr<1>.Q to DSACK0 | 0.000 | 9.900 | -9.900 |
cntr<2>.Q to DSACK0 | 0.000 | 9.900 | -9.900 |
Clock | fEXT (MHz) | Reason |
---|---|---|
RW_N | 100.000 | Limited by Clock Pulse Width for RW_N |
CLK | 178.571 | Limited by Clock Pulse Width for CLK |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
AS | 1.700 | 0.000 |
ECS | 1.700 | 0.000 |
FC0 | 1.700 | 0.000 |
FC1 | 1.700 | 0.000 |
FC2 | 1.700 | 0.000 |
R_BTN | 1.700 | 0.000 |
a26 | 1.700 | 0.000 |
a27 | 1.700 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
DSACK0 | 9.600 |
DSACK1 | 9.600 |
DRAM_CONFIG | 8.900 |
DRAM_CS | 8.900 |
Destination Pad | Clock (edge) to Pad |
---|---|
DSACK0 | 11.000 |
DSACK1 | 7.900 |
I_ALE | 7.600 |
I_IOR | 7.600 |
I_IOW | 7.600 |
I_MEMR | 7.600 |
I_MEMW | 7.600 |
Source | Destination | Delay |
---|---|---|
dram_config_sel.Q | dram_config_sel.D | 5.600 |
Source | Destination | Delay |
---|---|---|
cntr<0>.Q | cntr<1>.D | 5.600 |
cntr<0>.Q | cntr<2>.D | 5.600 |
cntr<0>.Q | cntr<3>.D | 5.600 |
cntr<1>.Q | cntr<2>.D | 5.600 |
cntr<1>.Q | cntr<3>.D | 5.600 |
cntr<2>.Q | cntr<3>.D | 5.600 |
Source Pad | Destination Pad | Delay |
---|---|---|
a26 | DSACK1 | 6.000 |
AS | DSACK0 | 5.700 |
AS | IO_CS | 5.700 |
AS | I_ALE | 5.700 |
AS | I_IOR | 5.700 |
AS | I_IOW | 5.700 |
AS | I_MEMR | 5.700 |
AS | I_MEMW | 5.700 |
DRAM_DTACK | DSACK0 | 5.700 |
DRAM_DTACK | DSACK1 | 5.700 |
ECS | DSACK0 | 5.700 |
ECS | IO_CS | 5.700 |
ECS | I_ALE | 5.700 |
ECS | I_IOR | 5.700 |
ECS | I_IOW | 5.700 |
ECS | I_MEMR | 5.700 |
ECS | I_MEMW | 5.700 |
FC0 | DSACK0 | 5.700 |
FC0 | DSACK1 | 5.700 |
FC1 | DSACK0 | 5.700 |
FC1 | DSACK1 | 5.700 |
FC1 | I_IOR | 5.700 |
FC1 | I_MEMW | 5.700 |
FC2 | DSACK0 | 5.700 |
FC2 | DSACK1 | 5.700 |
FC2 | IO_CS | 5.700 |
FC2 | I_ALE | 5.700 |
FC2 | I_IOR | 5.700 |
FC2 | I_IOW | 5.700 |
FC2 | I_MEMR | 5.700 |
FC2 | I_MEMW | 5.700 |
I_IOCHRDY | DSACK0 | 5.700 |
RW_N | I_IOR | 5.700 |
RW_N | I_IOW | 5.700 |
RW_N | I_MEMR | 5.700 |
RW_N | I_MEMW | 5.700 |
R_BTN | DSACK0 | 5.700 |
R_BTN | IO_CS | 5.700 |
R_BTN | I_ALE | 5.700 |
R_BTN | I_IOR | 5.700 |
R_BTN | I_IOW | 5.700 |
R_BTN | I_MEMR | 5.700 |
R_BTN | I_MEMW | 5.700 |
a16 | DSACK0 | 5.700 |
a16 | DSACK1 | 5.700 |
a19 | DSACK0 | 5.700 |
a19 | DSACK1 | 5.700 |
a19 | IO_CS | 5.700 |
a20 | DSACK0 | 5.700 |
a20 | DSACK1 | 5.700 |
a20 | IO_CS | 5.700 |
a21 | IO_CS | 5.700 |
a21 | I_IOR | 5.700 |
a21 | I_IOW | 5.700 |
a21 | I_MEMR | 5.700 |
a21 | I_MEMW | 5.700 |
a26 | DSACK0 | 5.700 |
a26 | IO_CS | 5.700 |
a26 | I_ALE | 5.700 |
a26 | I_IOR | 5.700 |
a26 | I_IOW | 5.700 |
a26 | I_MEMR | 5.700 |
a26 | I_MEMW | 5.700 |
a27 | DSACK0 | 5.700 |
a27 | DSACK1 | 5.700 |
a27 | IO_CS | 5.700 |
a27 | I_ALE | 5.700 |
a27 | I_IOR | 5.700 |
a27 | I_IOW | 5.700 |
a27 | I_MEMR | 5.700 |
a27 | I_MEMW | 5.700 |
AS | DRAM_CONFIG | 5.000 |
AS | DRAM_CS | 5.000 |
AS | DSACK1 | 5.000 |
AS | ETHRNT | 5.000 |
AS | FLOPPY | 5.000 |
AS | IDE | 5.000 |
AS | I_DIR | 5.000 |
AS | KBD_CS | 5.000 |
AS | ROM | 5.000 |
AS | RW0 | 5.000 |
AS | RW1 | 5.000 |
AS | VGA_CS | 5.000 |
AS | nRW0 | 5.000 |
AS | nRW1 | 5.000 |
ECS | DRAM_CONFIG | 5.000 |
ECS | DRAM_CS | 5.000 |
ECS | DSACK1 | 5.000 |
ECS | ETHRNT | 5.000 |
ECS | FLOPPY | 5.000 |
ECS | IDE | 5.000 |
ECS | I_DIR | 5.000 |
ECS | KBD_CS | 5.000 |
ECS | ROM | 5.000 |
ECS | RW0 | 5.000 |
ECS | RW1 | 5.000 |
ECS | VGA_CS | 5.000 |
ECS | nRW0 | 5.000 |
ECS | nRW1 | 5.000 |
FC0 | DRAM_CONFIG | 5.000 |
FC0 | DRAM_CS | 5.000 |
FC0 | ETHRNT | 5.000 |
FC0 | FLOPPY | 5.000 |
FC0 | FPU | 5.000 |
FC0 | IDE | 5.000 |
FC0 | IO_CS | 5.000 |
FC0 | I_ALE | 5.000 |
FC0 | I_DIR | 5.000 |
FC0 | I_IOR | 5.000 |
FC0 | I_IOW | 5.000 |
FC0 | I_MEMR | 5.000 |
FC0 | I_MEMW | 5.000 |
FC0 | KBD_CS | 5.000 |
FC0 | ROM | 5.000 |
FC0 | RW0 | 5.000 |
FC0 | RW1 | 5.000 |
FC0 | VGA_CS | 5.000 |
FC0 | nRW0 | 5.000 |
FC0 | nRW1 | 5.000 |
FC1 | DRAM_CONFIG | 5.000 |
FC1 | DRAM_CS | 5.000 |
FC1 | ETHRNT | 5.000 |
FC1 | FLOPPY | 5.000 |
FC1 | FPU | 5.000 |
FC1 | IDE | 5.000 |
FC1 | IO_CS | 5.000 |
FC1 | I_ALE | 5.000 |
FC1 | I_DIR | 5.000 |
FC1 | I_IOW | 5.000 |
FC1 | I_MEMR | 5.000 |
FC1 | KBD_CS | 5.000 |
FC1 | ROM | 5.000 |
FC1 | RW0 | 5.000 |
FC1 | RW1 | 5.000 |
FC1 | VGA_CS | 5.000 |
FC1 | nRW0 | 5.000 |
FC1 | nRW1 | 5.000 |
FC2 | DRAM_CONFIG | 5.000 |
FC2 | DRAM_CS | 5.000 |
FC2 | ETHRNT | 5.000 |
FC2 | FLOPPY | 5.000 |
FC2 | FPU | 5.000 |
FC2 | IDE | 5.000 |
FC2 | I_DIR | 5.000 |
FC2 | KBD_CS | 5.000 |
FC2 | ROM | 5.000 |
FC2 | RW0 | 5.000 |
FC2 | RW1 | 5.000 |
FC2 | VGA_CS | 5.000 |
FC2 | nRW0 | 5.000 |
FC2 | nRW1 | 5.000 |
RW_N | I_DIR | 5.000 |
RW_N | READ_n | 5.000 |
RW_N | RW0 | 5.000 |
RW_N | RW1 | 5.000 |
RW_N | nRW0 | 5.000 |
RW_N | nRW1 | 5.000 |
R_BTN | DRAM_CONFIG | 5.000 |
R_BTN | DRAM_CS | 5.000 |
R_BTN | DSACK1 | 5.000 |
R_BTN | ETHRNT | 5.000 |
R_BTN | FLOPPY | 5.000 |
R_BTN | HALT | 5.000 |
R_BTN | IDE | 5.000 |
R_BTN | I_DIR | 5.000 |
R_BTN | KBD_CS | 5.000 |
R_BTN | RESET | 5.000 |
R_BTN | ROM | 5.000 |
R_BTN | RW0 | 5.000 |
R_BTN | RW1 | 5.000 |
R_BTN | VGA_CS | 5.000 |
R_BTN | nRW0 | 5.000 |
R_BTN | nRW1 | 5.000 |
SIZ0 | BYTE0 | 5.000 |
SIZ0 | BYTE1 | 5.000 |
SIZ0 | BYTE2 | 5.000 |
SIZ1 | BYTE0 | 5.000 |
SIZ1 | BYTE1 | 5.000 |
SIZ1 | BYTE2 | 5.000 |
a0 | BYTE0 | 5.000 |
a0 | BYTE1 | 5.000 |
a0 | BYTE2 | 5.000 |
a0 | BYTE3 | 5.000 |
a1 | BYTE0 | 5.000 |
a1 | BYTE1 | 5.000 |
a1 | BYTE2 | 5.000 |
a1 | BYTE3 | 5.000 |
a16 | FPU | 5.000 |
a19 | ETHRNT | 5.000 |
a19 | FLOPPY | 5.000 |
a19 | IDE | 5.000 |
a19 | KBD_CS | 5.000 |
a19 | ROM | 5.000 |
a19 | VGA_CS | 5.000 |
a20 | ETHRNT | 5.000 |
a20 | FLOPPY | 5.000 |
a20 | IDE | 5.000 |
a20 | KBD_CS | 5.000 |
a20 | ROM | 5.000 |
a20 | VGA_CS | 5.000 |
a21 | DSACK0 | 5.000 |
a21 | DSACK1 | 5.000 |
a21 | ETHRNT | 5.000 |
a21 | FLOPPY | 5.000 |
a21 | IDE | 5.000 |
a21 | KBD_CS | 5.000 |
a21 | ROM | 5.000 |
a21 | RW0 | 5.000 |
a21 | RW1 | 5.000 |
a21 | VGA_CS | 5.000 |
a21 | nRW0 | 5.000 |
a21 | nRW1 | 5.000 |
a26 | DRAM_CONFIG | 5.000 |
a26 | DRAM_CS | 5.000 |
a26 | ETHRNT | 5.000 |
a26 | FLOPPY | 5.000 |
a26 | IDE | 5.000 |
a26 | I_DIR | 5.000 |
a26 | KBD_CS | 5.000 |
a26 | ROM | 5.000 |
a26 | RW0 | 5.000 |
a26 | RW1 | 5.000 |
a26 | VGA_CS | 5.000 |
a26 | nRW0 | 5.000 |
a26 | nRW1 | 5.000 |
a27 | DRAM_CONFIG | 5.000 |
a27 | DRAM_CS | 5.000 |
a27 | ETHRNT | 5.000 |
a27 | FLOPPY | 5.000 |
a27 | IDE | 5.000 |
a27 | I_DIR | 5.000 |
a27 | KBD_CS | 5.000 |
a27 | ROM | 5.000 |
a27 | RW0 | 5.000 |
a27 | RW1 | 5.000 |
a27 | VGA_CS | 5.000 |
a27 | nRW0 | 5.000 |
a27 | nRW1 | 5.000 |