mux Project Status (05/11/2019 - 08:56:09)
Project File: Blitz.xise Parser Errors: No Errors
Module Name: mux Implementation State: Fitted
Target Device: xc9572xl-5VQ64
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
5 Warnings (3 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat May 11 08:56:02 201905 Warnings (3 new)1 Info (1 new)
Translation ReportCurrentSat May 11 08:56:05 2019000
CPLD Fitter Report (Text)CurrentSat May 11 08:56:06 201902 Warnings (1 new)0
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
IBIS ModelOut of DateFri Apr 19 09:40:02 2019
Post-Fit Simulation Model ReportOut of DateFri Apr 19 09:40:01 2019

Date Generated: 05/11/2019 - 08:56:09