;
; Reverse-engineered source code for the timing generator
; Interak VDU-K board.
;
; Original disassembly by z80dasm 1.1.5
; command line: z80dasm -g 0x3000 -l Interak_VDU-K_timing_generator_1.bin
;
;
;
; Assmbles online at www.asm80.com
;
; Uses no external RAM, so no subroutines or RET opcodes.
;
; Video is 32 x 24 characters,
; characters are 8 x 10 pixels.
;
;
	.cpu	z80
	org	3000h	; seems the place where it expects to run
			; but note it occupies the entire memory map.
	.binfrom	$
	.binto		$+800h
;
; (hl) points to the timing state register in memory.
; As there is only one writable location in memory,
; the contents of HL do not matter.
; The !WR signal goes straight to U13, a six-bit latch.
; D4 and D5 are not connected, so a 4-bit latch would have done fine.
;
; D3,2,1,0 are V,H,R,S respectively.
;
; V resets the vertical picture line counter and the vertical character line counter.
; H is the dot edge synchronisation (U20A)
; R resets the horizontal character counter (U9, a 74LS393).
; S is the composite sync
;
	state_____	equ	000h
	state____S	equ	001h
	state___R_	equ	002h
	state___RS	equ	003h
	state__H_S	equ	005h
	state_V_R_	equ	00ah
	state_V_RS	equ	00bh
	character_columns		equ	32
	scan_lines_per_character	equ	10

;
; There has to be code at location 0000 but
; many labels are at 3000 hex upward.
;
; The code starts outputting data from registers h and l
; before they are initilised.
; Dodgy, but if initilised later then things should
; settle down after a few video lines or frames.
;
; There are four timing programs:
;
; loop_3000H_32x24_chars_interlaced
; loop_3100H_32x24_chars_non_interlaced
; loop_3400H_32x16_chars_interlaced
; loop_3600H_32x16_chars_non_interlaced
;
; A9 is controlled by S1-h, closed for interlaced.
;
; A10 is controlled by a track on the PCB.
; This is normally low.
; 0 = 24 character rows.
; 1 = 16 character rows.
;
; Each program occupies 512 bytes, repeated throughout the Z80 memory space.
;
; Each will be aliased at 0000, 0800, etc.
;
; jp 0 will sweep illegal code execution
; back to the start of programs.
; The address part, 0000, is seen as two nop codes.
;
; Register A is a scan line counter
; Register C is a counter
;
; Timing and the snow-free feature are heavily reliant on a 3 MHz video CPU clock.
;
;
;
loop_3000H_32x24_chars_interlaced:
	ld (hl),state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld a,scan_lines_per_character * 24
	ld (hl),state_V_RS	; composite sync rises
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3000H_32x24_chars_interlaced
loop_3027h:
	ld (hl),0		; all signals cleared
	ld (hl),b
	ld (hl),d		; state___RS
	nop
	nop
	nop
	nop
	ld (hl),state__H_S
	ld (hl),e		; state__H_S
	ld (hl),e		; state__H_S
	ld (hl),e		; state__H_S
	ld (hl),e		; state__H_S
	ld bc,21
	ld de,state___RS*256+state__H_S	; d and e are two different states
	ld hl,state_V_R_*256+state_V_RS	; h and l are two different states
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state____S
	dec a
	jp nz,loop_3027h
loop_3050h:
	ld (hl),state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld a,5
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3050h
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l		; state_V_RS
	ld (hl),state_V_RS
	ld a,5
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ccf
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	jp c,loop_309ah
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
loop_309ah:
	ld (hl),state_V_R_	; composite sync falls
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),state_V_RS	; composite sync rises
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec a
	jp nz,loop_309ah
	ld (hl),state_V_R_	; composite sync falls
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),l		; state_V_RS
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),l		; state_V_RS
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),l		; state_V_RS
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),l		; state_V_RS
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld a,4
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),l		; state_V_RS
	nop
loop_3102h:
	ld (hl),state_V_R_
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),state_V_RS	; composite sync rises
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec a
	jp nz,loop_3102h
	ld (hl),state_V_R_	; composite sync falls
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld c,43
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),state_V_RS	; composite sync rises
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	nop
	jp c,loop_3137h
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
loop_3137h:
	ld (hl),state_V_R_
	ld (hl),h		; state_V_R_
	ld (hl),l		; state_V_RS
	ld (hl),l		; state_V_RS
	ld a,scan_lines_per_character * 24
	ld (hl),state_V_RS	; composite sync rises
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3000H_32x24_chars_interlaced
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
loop_3100H_32x24_chars_non_interlaced:
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),l
	ld a,scan_lines_per_character * 24
	ld (hl),state_V_RS	; composite sync rises
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3100H_32x24_chars_non_interlaced
loop_3227h:
	ld (hl),0
	ld (hl),b
	ld (hl),d
	nop
	nop
	nop
	nop
	ld (hl),state__H_S
	ld (hl),e
	ld (hl),e
	ld (hl),e
	ld (hl),e
	ld bc,21
	ld de,state___RS*256+state__H_S	; d and e are two different states
	ld hl,state_V_R_*256+state_V_RS	; h and l are two different states
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state____S
	dec a
	jp nz,loop_3227h
loop_3250h:
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),l
	ld a,5	;
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3250h
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),state_V_RS
	ld a,5
	ld (hl),l
	ld (hl),l
	ld (hl),l
	scf
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	jp c,loop_329ah
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
loop_329ah:
	ld (hl),state_V_R_
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS	; composite sync rises
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec a
	jp nz,loop_329ah
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld a,4
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
loop_3302h:
	ld (hl),state_V_R_
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec a
	jp nz,loop_3302h
	ld (hl),state_V_R_
	ld (hl),l
	ld (hl),l
	ld c,43
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	nop
	jp c,loop_3337h
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
loop_3337h:
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),l
	ld a,scan_lines_per_character * 24
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3100H_32x24_chars_non_interlaced
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
loop_3400H_32x16_chars_interlaced:
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),l
	ld a,scan_lines_per_character * 16
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3400H_32x16_chars_interlaced
loop_3427h:
	ld (hl),0
	ld (hl),b
	ld (hl),d
	nop
	nop
	nop
	nop
	ld (hl),state__H_S
	ld (hl),e
	ld (hl),e
	ld (hl),e
	ld (hl),e
	ld bc,61
	ld de,state___RS*256+state__H_S	; d and e are two different states
	ld hl,state_V_R_*256+state_V_RS	; h and l are two different states
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state____S
	dec a
	jp nz,loop_3427h
loop_3450h:
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),l
	ld a,5
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3450h
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),state_V_RS
	ld a,5
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ccf
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	jp c,loop_349ah
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
loop_349ah:
	ld (hl),state_V_R_
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec a
	jp nz,loop_349ah
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld a,4
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
loop_3502h:
	ld (hl),state_V_R_
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec a
	jp nz,loop_3502h
	ld (hl),state_V_R_
	ld (hl),l
	ld (hl),l
	ld c,83
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	nop
	jp c,loop_3537h
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
loop_3537h:
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),l
	ld a,scan_lines_per_character * 24
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3400H_32x16_chars_interlaced
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
loop_3600H_32x16_chars_non_interlaced:
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),l
	ld a,scan_lines_per_character * 16
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3600H_32x16_chars_non_interlaced
loop_3627h:
	ld (hl),0
	ld (hl),b
	ld (hl),d
	nop
	nop
	nop
	nop
	ld (hl),state__H_S
	ld (hl),e
	ld (hl),e
	ld (hl),e
	ld (hl),e
	ld bc,61
	ld de,state___RS*256+state__H_S	; d and e are two different states
	ld hl,state_V_R_*256+state_V_RS	; h and l are two different states
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state__H_S
	ld (hl),state____S
	dec a
	jp nz,loop_3627h
loop_3650h:
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),l
	ld a,5
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3650h
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),state_V_RS
	ld a,5
	ld (hl),l
	ld (hl),l
	ld (hl),l
	scf
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	jp c,loop_369ah
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
loop_369ah:
	ld (hl),state_V_R_
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec a
	jp nz,loop_369ah
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld (hl),state_V_R_
	ld a,4
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),h
	ld (hl),l
	nop
loop_3702h:
	ld (hl),state_V_R_
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec a
	jp nz,loop_3702h
	ld (hl),state_V_R_
	ld (hl),l
	ld (hl),l
	ld c,83
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	nop
	jp c,loop_3737h
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),l
	ld (hl),state_V_RS
	ld (hl),state_V_RS
loop_3737h:
	ld (hl),state_V_R_
	ld (hl),h
	ld (hl),l
	ld (hl),l
	ld a,scan_lines_per_character * 24
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	ld (hl),state_V_RS
	dec c
	jp nz,loop_3600H_32x16_chars_non_interlaced
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
	jp 0
;
	.end