`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: Shashank V M // // Create Date: 06.03.2020 23:19:42 // Design Name: stack // Module Name: stack_design // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// parameter data_width = 9; parameter lifo_depth = 7; module stack_design( input logic clk, rst, RdPtrClr, WrPtrClr, RdDec, WrInc, rden, wren, [data_width-1:0] DataIn, output logic [data_width-1:0] DataOut, stack_overflow_flag, stack_underflow_flag ); logic [data_width-1:0] lifo_array[lifo_depth:0]; logic [lifo_depth:0] wrptr = {data_width{1'b0}}; logic [lifo_depth:0] rdptr = lifo_depth; always @(posedge(clk), rst) begin if (rst == 1'b1) begin wrptr = {lifo_depth+1{1'b0}}; for (wrptr = {lifo_depth+1{1'b0}}; wrptr < lifo_depth; wrptr = wrptr + 1) begin lifo_array[wrptr] = {data_width{1'b0}}; DataOut <= lifo_array[wrptr]; end rdptr = lifo_depth; end if ((RdDec == 1'b1) & (rdptr > {lifo_depth+1{1'b0}})) rdptr <= rdptr - 1; if (RdPtrClr) rdptr <= lifo_depth; if (rden) DataOut <= lifo_array[rdptr]; else DataOut <= {data_width{1'bZ}}; if (wren) lifo_array[wrptr] <= DataIn; if ((WrInc == 1'b1) & (wrptr < lifo_depth+1)) wrptr <= wrptr + 1; if (WrPtrClr == 1'b1) wrptr <= {lifo_depth+1{1'b0}}; $display("%h %h", wrptr, rdptr); end assign stack_underflow_flag = (rdptr <= {lifo_depth+1{1'b0}}); assign stack_overflow_flag = (wrptr >= lifo_depth); endmodule