Atmel ATF1508AS Fitter Version 1.8.7.8 ,running Fri May 07 22:59:33 2021


fit1508 C:\USERS\BERT_\DOCUMENTS\01_CCZ80_COMP\CCZ80_MPU\CPLD\MAIN\MAIN.tt2 -CUPL -dev P1508Q100 -JTAG ON


****** Initial fitting strategy and property ******
 Pla_in_file = MAIN.tt2
 Pla_out_file = MAIN.tt3
 Jedec_file = MAIN.jed
 Vector_file = MAIN.tmv
 verilog_file = MAIN.vt
 Time_file = 
 Log_file = MAIN.fit
 err_file = 
 Device_name = PQFP100
 Module_name = 
 Package_type = PQFP
 Preassign_file = 
 Property_file = 
 Sleep_mode = 
 Preassignment = 
 Security_mode = OFF
 Pin_keep_mode = ON
 Dedicated_input_clock = 
 Dedicated_input_reset = 
 Dedicated_input_oe = 
 supporter = CUPL
 optimize = ON
 Soft_buffer = 
 Xor_synthesis = OFF
 Foldback_logic =  on
 Expander = 
 Cascade_logic = OFF
 Dedicated_input = 
 Output_fast = OFF
 *******************************
 Power down pin 1 = OFF
 Power down pin 2 = OFF
 power_reset = OFF
 JTAG = ON
 TDI pullup = OFF
 TMS pullup = OFF
 MC_power = OFF
 Open_collector = OFF
 ITD0 = ON
 ITD1 = ON
 ITD2 = ON
 Fast_inlatch = off
 *******************************
---------------------------------------------------------
 Fitter_Pass 1, Preassign = KEEP, LOGIC_DOUBLING : OFF 
 ... 
## ERROR : Bad user pin assignement : 102
 ## ERROR : Bad user pin assignement 
---------------------------------------------------------
 Fitter_Pass 2, Preassign = KEEP, NODE ASSIGN : OFF 
 ... 
Unable to Keep Fanin of 44 on Block D
 ## Warning : Grouping fail 
---------------------------------------------------------
 Fitter_Pass 3, Preassign = KEEP, CASCADE_LOGIC : (TRY) 
 ... 
 ## Warning : Placement fail 
---------------------------------------------------------
 Fitter_Pass 4, Preassign = KEEP, CASCADE_LOGIC : (OFF) 
 ... 

Performing global Output Enable pin assignments ...

Performing global pin assignments ...
--------------------------------------



Final global control pins assignment (if applicable)...
-------------------------------------------------------
XCLK assigned to pin  89
nRESET assigned to pin  91



Performing input pin pre-assignments ...
------------------------------------
CLKi assigned to pin  92
XCLK assigned to pin  89
nRESET assigned to pin  91
nHALT assigned to pin  90

Attempt to place floating signals ...
------------------------------------
RomA15 is placed at pin 4 (MC 1)
RomA16 is placed at pin 3 (MC 3)
FB_362 is placed at foldback expander node 304 (MC 4)
RomA17 is placed at pin 2 (MC 5)
FB_361 is placed at foldback expander node 305 (MC 5)
nRomCS is placed at pin 1 (MC 6)
DOWAIT is placed at foldback expander node 307 (MC 7)
nWAIT is placed at pin 100 (MC 8)
NOWAIT is placed at foldback expander node 308 (MC 8)
nWE is placed at pin 99 (MC 9)
XXL_376 is placed at feedback node 609 (MC 9)
XXL_375 is placed at feedback node 610 (MC 10)
nWR is placed at pin 98 (MC 11)
XXL_377 is placed at feedback node 611 (MC 11)
XXL_381 is placed at feedback node 612 (MC 12)
nRD is placed at pin 96 (MC 13)
XXL_379 is placed at feedback node 613 (MC 13)
nIORQ is placed at pin 95 (MC 14)
XXL_382 is placed at feedback node 614 (MC 14)
XXL_380 is placed at feedback node 615 (MC 15)
nMREQ is placed at pin 94 (MC 16)
XXL_378 is placed at feedback node 616 (MC 16)
A4 is placed at pin 16 (MC 17)
PRIM2 is placed at feedback node 617 (MC 17)
PRIM0 is placed at feedback node 618 (MC 18)
A3 is placed at pin 15 (MC 19)
PRIM1 is placed at feedback node 619 (MC 19)
SEC4 is placed at feedback node 620 (MC 20)
A2 is placed at pin 14 (MC 21)
SEC5 is placed at feedback node 621 (MC 21)
A1 is placed at pin 12 (MC 22)
SEC3 is placed at feedback node 622 (MC 22)
SEC1 is placed at feedback node 623 (MC 23)
A0 is placed at pin 11 (MC 24)
SEC2 is placed at feedback node 624 (MC 24)
nRFSH is placed at pin 10 (MC 25)
SEC0 is placed at feedback node 625 (MC 25)
R40 is placed at feedback node 626 (MC 26)
nM1 is placed at pin 9 (MC 27)
R41 is placed at feedback node 627 (MC 27)
R31 is placed at feedback node 628 (MC 28)
Z80RESET is placed at pin 8 (MC 29)
nBUSRQ is placed at pin 7 (MC 30)
R20 is placed at feedback node 630 (MC 30)
Com_Ctrl_359 is placed at foldback expander node 330 (MC 30)
XXL_363 is placed at feedback node 631 (MC 31)
TDI is placed at pin 6 (MC 32)
XXL_364 is placed at feedback node 632 (MC 32)
A13 is placed at pin 27 (MC 33)
PRIM3 is placed at feedback node 633 (MC 33)
R46 is placed at feedback node 634 (MC 34)
A12 is placed at pin 26 (MC 35)
R47 is placed at feedback node 635 (MC 35)
R37 is placed at feedback node 636 (MC 36)
A11 is placed at pin 25 (MC 37)
R36 is placed at feedback node 637 (MC 37)
A10 is placed at pin 24 (MC 38)
R26 is placed at feedback node 638 (MC 38)
R27 is placed at feedback node 639 (MC 39)
A9 is placed at pin 23 (MC 40)
R17 is placed at feedback node 640 (MC 40)
A8 is placed at pin 22 (MC 41)
R16 is placed at feedback node 641 (MC 41)
PRIM6 is placed at feedback node 642 (MC 42)
A7 is placed at pin 21 (MC 43)
PRIM7 is placed at feedback node 643 (MC 43)
SEC7 is placed at feedback node 644 (MC 44)
A6 is placed at pin 19 (MC 45)
SEC6 is placed at feedback node 645 (MC 45)
Com_Ctrl_359 is placed at foldback expander node 345 (MC 45)
A5 is placed at pin 18 (MC 46)
XXL_367 is placed at feedback node 646 (MC 46)
XXL_366 is placed at feedback node 647 (MC 47)
TMS is placed at pin 17 (MC 48)
XXL_365 is placed at feedback node 648 (MC 48)
D7 is placed at pin 39 (MC 49)
R15 is placed at feedback node 650 (MC 50)
D6 is placed at pin 38 (MC 51)
R13 is placed at feedback node 652 (MC 52)
D5 is placed at pin 37 (MC 53)
D4 is placed at pin 35 (MC 54)
R11 is placed at feedback node 655 (MC 55)
D3 is placed at pin 34 (MC 56)
D2 is placed at pin 33 (MC 57)
R10 is placed at feedback node 658 (MC 58)
D1 is placed at pin 32 (MC 59)
R12 is placed at feedback node 660 (MC 60)
D0 is placed at pin 31 (MC 61)
A15 is placed at pin 30 (MC 62)
PRIM5 is placed at feedback node 662 (MC 62)
PRIM4 is placed at feedback node 663 (MC 63)
A14 is placed at pin 29 (MC 64)
Com_Ctrl_360 is placed at feedback node 664 (MC 64)
XXL_369 is placed at feedback node 668 (MC 68)
CLK is placed at pin 46 (MC 70)
XXL_368 is placed at feedback node 670 (MC 70)
R44 is placed at feedback node 671 (MC 71)
nINT is placed at pin 47 (MC 72)
R24 is placed at feedback node 672 (MC 72)
nNMI is placed at pin 48 (MC 73)
R34 is placed at feedback node 673 (MC 73)
R14 is placed at feedback node 674 (MC 74)
Debug1 is placed at pin 49 (MC 75)
Debug2 is placed at pin 50 (MC 77)
XXL_370 is placed at feedback node 679 (MC 79)
nBUSACK is placed at pin 52 (MC 80)
ATCLK is placed at pin 54 (MC 81)
INT is placed at pin 55 (MC 83)
XXL_373 is placed at feedback node 684 (MC 84)
nCLK is placed at pin 56 (MC 85)
test1 is placed at pin 57 (MC 86)
XXL_384 is placed at feedback node 690 (MC 90)
XXL_371 is placed at feedback node 691 (MC 91)
XXL_383 is placed at feedback node 692 (MC 92)
nSLT2 is placed at pin 62 (MC 93)
nSLT1 is placed at pin 63 (MC 94)
XXL_374 is placed at feedback node 695 (MC 95)
TCK is placed at pin 64 (MC 96)
XXL_372 is placed at feedback node 696 (MC 96)
R45 is placed at feedback node 697 (MC 97)
R42 is placed at feedback node 698 (MC 98)
test2 is placed at pin 66 (MC 99)
R33 is placed at feedback node 700 (MC 100)
nBUSRD is placed at pin 67 (MC 101)
R35 is placed at feedback node 701 (MC 101)
nResume is placed at pin 69 (MC 102)
R30 is placed at feedback node 702 (MC 102)
R23 is placed at feedback node 703 (MC 103)
SECADR_PIN is placed at pin 70 (MC 104)
R43 is placed at feedback node 705 (MC 105)
R32 is placed at feedback node 706 (MC 106)
nCS_Serial is placed at pin 72 (MC 107)
R25 is placed at feedback node 708 (MC 108)
nCS_HD is placed at pin 73 (MC 109)
SpareCS is placed at pin 74 (MC 110)
R22 is placed at feedback node 711 (MC 111)
TDO is placed at pin 75 (MC 112)
R21 is placed at feedback node 712 (MC 112)
nCS_RTC is placed at pin 77 (MC 113)
nBUScon is placed at pin 78 (MC 115)
RomA14 is placed at pin 81 (MC 120)
RomA13 is placed at pin 82 (MC 121)
RomA19 is placed at pin 83 (MC 123)
RomA18 is placed at pin 85 (MC 125)
nRomRD is placed at pin 86 (MC 126)
nRomWE is placed at pin 87 (MC 128)

                                                                                    
                                                                                    
                                                                                    
                                                                                    
                                           n       n n R   R R R                    
                         n         n n     R n     R R o   o o o                    
                         W         I M   C E H X   o o m   m m m                    
                         A n n G n O R V L S A C G m m A V A A A                    
                         I W W N R R E C K E L L N W R 1 C 1 1 1                    
                         T E R D D Q Q C i T T K D E D 8 C 9 3 4                    
                       --------------------------------------------                 
                      / 100  98  96  94  92  90  88  86  84  82    \               
                     /     99  97  95  93  91  89  87  85  83  81   \              
             nRomCS |  1 (*)                                      80 |              
             RomA17 |  2                                          79 |              
             RomA16 |  3                                          78 | nBUScon      
             RomA15 |  4                                          77 | nCS_RTC      
                VCC |  5                                          76 | GND          
                TDI |  6                                          75 | TDO          
             nBUSRQ |  7                                          74 | SpareCS      
           Z80RESET |  8                                          73 | nCS_HD       
                nM1 |  9                                          72 | nCS_Serial   
              nRFSH | 10                                          71 |              
                 A0 | 11                                          70 | SECADR_PIN   
                 A1 | 12                                          69 | nResume      
                GND | 13                                          68 | VCC          
                 A2 | 14                                          67 | nBUSRD       
                 A3 | 15                                          66 | test2        
                 A4 | 16                ATF1508                   65 |              
                TMS | 17             100-Lead PQFP                64 | TCK          
                 A5 | 18                                          63 | nSLT1        
                 A6 | 19                                          62 | nSLT2        
                VCC | 20                                          61 | GND          
                 A7 | 21                                          60 |              
                 A8 | 22                                          59 |              
                 A9 | 23                                          58 |              
                A10 | 24                                          57 | test1        
                A11 | 25                                          56 | nCLK         
                A12 | 26                                          55 | INT          
                A13 | 27                                          54 | ATCLK        
                GND | 28                                          53 | VCC          
                A14 | 29                                          52 | nBUSACK      
                A15 | 30                                          51 |              
                     \     32  34  36  38  40  42  44  46  48  50   /              
                      \  31  33  35  37  39  41  43  45  47  49    /               
                       --------------------------------------------                 
                         D D D D D V D D D G V       G C n n D D                    
                         0 1 2 3 4 C 5 6 7 N C       N L I N e e                    
                                   C       D C       D K N M b b                    
                                                         T I u u                    
                                                             g g                    
                                                             1	2                    



VCC = Supply Voltage pin which must be connected to (5.0V or 3.0V)

GND = GND pin which must be connected to ground

TMS,TDI,TDO,TDI = JTAG pins which must reserved for the JTAG interface

NC = Unused I/O pins which must be unconnected on the board

Universal-Interconnect-Multiplexer assignments
------------------------------------------------
FanIn assignment for block A [40]
{
A15,A14,
PRIM0,PRIM1,PRIM5,PRIM3,PRIM2,PRIM7,PRIM6,PRIM4,
R43,R40,R20,R13,R30,R10,R42,
SEC4,SEC0,SEC2,SEC6,SEC7,SEC5,SEC1,SEC3,
XXL_377,XXL_376,XXL_383,XXL_371,XXL_375,XXL_384,XXL_372,
nResume,nCS_HD,nCS_RTC,nCS_Serial,nWE,nWR,nMREQ,nRESET,
}
Multiplexer assignment for block A
PRIM0			(MC5	FB)  : MUX 0		Ref (B18fb)
nResume			(MC39	P)   : MUX 1		Ref (G102p)
SEC4			(MC7	FB)  : MUX 2		Ref (B20fb)
R43			(MC30	FB)  : MUX 3		Ref (G105fb)
nCS_HD			(MC32	P)   : MUX 4		Ref (G109p)
nCS_RTC			(MC33	P)   : MUX 5		Ref (H113p)
nCS_Serial		(MC31	P)   : MUX 6		Ref (G107p)
SEC0			(MC12	FB)  : MUX 7		Ref (B25fb)
nWE			(MC34	P)   : MUX 8		Ref (A9p)
XXL_377			(MC3	FB)  : MUX 9		Ref (A11fb)
nWR			(MC35	P)   : MUX 10		Ref (A11p)
R40			(MC13	FB)  : MUX 11		Ref (B26fb)
SEC2			(MC11	FB)  : MUX 12		Ref (B24fb)
R20			(MC14	FB)  : MUX 13		Ref (B30fb)
A15			(MC37	P)   : MUX 14		Ref (D62p)
XXL_376			(MC1	FB)  : MUX 15		Ref (A9fb)
PRIM1			(MC6	FB)  : MUX 16		Ref (B19fb)
SEC6			(MC19	FB)  : MUX 17		Ref (C45fb)
nMREQ			(MC36	P)   : MUX 18		Ref (A16p)
SEC7			(MC18	FB)  : MUX 19		Ref (C44fb)
R13			(MC20	FB)  : MUX 20		Ref (D52fb)
PRIM5			(MC22	FB)  : MUX 21		Ref (D62fb)
R30			(MC29	FB)  : MUX 22		Ref (G102fb)
XXL_383			(MC26	FB)  : MUX 23		Ref (F92fb)
PRIM3			(MC15	FB)  : MUX 24		Ref (C33fb)
XXL_371			(MC25	FB)  : MUX 25		Ref (F91fb)
PRIM2			(MC4	FB)  : MUX 26		Ref (B17fb)
XXL_375			(MC2	FB)  : MUX 27		Ref (A10fb)
SEC5			(MC8	FB)  : MUX 28		Ref (B21fb)
R10			(MC21	FB)  : MUX 29		Ref (D58fb)
A14			(MC38	P)   : MUX 30		Ref (D64p)
PRIM7			(MC17	FB)  : MUX 31		Ref (C43fb)
SEC1			(MC10	FB)  : MUX 32		Ref (B23fb)
PRIM6			(MC16	FB)  : MUX 33		Ref (C42fb)
SEC3			(MC9	FB)  : MUX 34		Ref (B22fb)
PRIM4			(MC23	FB)  : MUX 35		Ref (D63fb)
nRESET			(MC40	FB)  : MUX 36		Ref (GCLR)
XXL_384			(MC24	FB)  : MUX 37		Ref (F90fb)
R42			(MC28	FB)  : MUX 38		Ref (G98fb)
XXL_372			(MC27	FB)  : MUX 39		Ref (F96fb)

FanIn assignment for block B [37]
{
A13,A0,A3,A6,A8,A2,A7,A11,A5,A9,A10,A1,A4,A15,A12,A14,
D5,D2,D4,D3,D1,D0,
PRIM3,PRIM0,
R23,R43,R33,R20,R30,R40,
SEC3,SEC0,
nRD,nWR,nMREQ,nIORQ,nRESET,
}
Multiplexer assignment for block B
nRD			(MC18	P)   : MUX 0		Ref (A13p)
A13			(MC26	P)   : MUX 1		Ref (C33p)
R23			(MC15	FB)  : MUX 2		Ref (G103fb)
D5			(MC7	P)   : MUX 3		Ref (D53p)
D2			(MC10	P)   : MUX 4		Ref (D57p)
R43			(MC16	FB)  : MUX 5		Ref (G105fb)
nWR			(MC17	P)   : MUX 6		Ref (A11p)
D4			(MC8	P)   : MUX 7		Ref (D54p)
R33			(MC13	FB)  : MUX 8		Ref (G100fb)
A0			(MC25	P)   : MUX 9		Ref (B24p)
nMREQ			(MC20	P)   : MUX 10		Ref (A16p)
A3			(MC22	P)   : MUX 11		Ref (B19p)
nIORQ			(MC19	P)   : MUX 12		Ref (A14p)
R20			(MC5	FB)  : MUX 13		Ref (B30fb)
A6			(MC33	P)   : MUX 14		Ref (C45p)
D3			(MC9	P)   : MUX 15		Ref (D56p)
A8			(MC31	P)   : MUX 16		Ref (C41p)
A2			(MC23	P)   : MUX 17		Ref (B21p)
A7			(MC32	P)   : MUX 18		Ref (C43p)
A11			(MC28	P)   : MUX 19		Ref (C37p)
A5			(MC34	P)   : MUX 20		Ref (C46p)
A9			(MC30	P)   : MUX 21		Ref (C40p)
R30			(MC14	FB)  : MUX 22		Ref (G102fb)
R40			(MC4	FB)  : MUX 23		Ref (B26fb)
PRIM3			(MC6	FB)  : MUX 24		Ref (C33fb)
A10			(MC29	P)   : MUX 25		Ref (C38p)
SEC3			(MC2	FB)  : MUX 26		Ref (B22fb)
A1			(MC24	P)   : MUX 27		Ref (B22p)
PRIM0			(MC1	FB)  : MUX 28		Ref (B18fb)
D1			(MC11	P)   : MUX 30		Ref (D59p)
A4			(MC21	P)   : MUX 31		Ref (B17p)
A15			(MC35	P)   : MUX 32		Ref (D62p)
nRESET			(MC37	FB)  : MUX 34		Ref (GCLR)
A12			(MC27	P)   : MUX 35		Ref (C35p)
D0			(MC12	P)   : MUX 36		Ref (D61p)
SEC0			(MC3	FB)  : MUX 37		Ref (B25fb)
A14			(MC36	P)   : MUX 38		Ref (D64p)

FanIn assignment for block C [38]
{
A13,A0,A7,A9,A6,A2,A11,A10,A5,A3,A15,A1,A14,A4,A8,A12,
D7,D6,D3,
PRIM4,PRIM2,PRIM1,
R22,R44,R34,R41,R31,R24,R21,R42,R32,
SEC4,SEC2,SEC1,
nRD,nMREQ,nWR,nIORQ,
}
Multiplexer assignment for block C
nRD			(MC20	P)   : MUX 0		Ref (A13p)
A13			(MC28	P)   : MUX 1		Ref (C33p)
A0			(MC27	P)   : MUX 3		Ref (B24p)
nMREQ			(MC22	P)   : MUX 4		Ref (A16p)
D7			(MC8	P)   : MUX 5		Ref (D49p)
nWR			(MC19	P)   : MUX 6		Ref (A11p)
R22			(MC17	FB)  : MUX 7		Ref (G111fb)
nIORQ			(MC21	P)   : MUX 8		Ref (A14p)
PRIM4			(MC11	FB)  : MUX 9		Ref (D63fb)
A7			(MC34	P)   : MUX 10		Ref (C43p)
A9			(MC32	P)   : MUX 11		Ref (C40p)
PRIM2			(MC1	FB)  : MUX 12		Ref (B17fb)
D6			(MC9	P)   : MUX 13		Ref (D51p)
A6			(MC35	P)   : MUX 14		Ref (C45p)
D3			(MC10	P)   : MUX 15		Ref (D56p)
PRIM1			(MC2	FB)  : MUX 16		Ref (B19fb)
A2			(MC25	P)   : MUX 17		Ref (B21p)
R44			(MC12	FB)  : MUX 18		Ref (E71fb)
R34			(MC14	FB)  : MUX 19		Ref (E73fb)
SEC4			(MC3	FB)  : MUX 20		Ref (B20fb)
A11			(MC30	P)   : MUX 21		Ref (C37p)
SEC2			(MC5	FB)  : MUX 22		Ref (B24fb)
R41			(MC6	FB)  : MUX 23		Ref (B27fb)
A10			(MC31	P)   : MUX 25		Ref (C38p)
A5			(MC36	P)   : MUX 26		Ref (C46p)
A3			(MC24	P)   : MUX 27		Ref (B19p)
A15			(MC37	P)   : MUX 28		Ref (D62p)
A1			(MC26	P)   : MUX 29		Ref (B22p)
A14			(MC38	P)   : MUX 30		Ref (D64p)
R31			(MC7	FB)  : MUX 31		Ref (B28fb)
SEC1			(MC4	FB)  : MUX 32		Ref (B23fb)
A4			(MC23	P)   : MUX 33		Ref (B17p)
A8			(MC33	P)   : MUX 34		Ref (C41p)
A12			(MC29	P)   : MUX 35		Ref (C35p)
R24			(MC13	FB)  : MUX 36		Ref (E72fb)
R21			(MC18	FB)  : MUX 37		Ref (G112fb)
R42			(MC15	FB)  : MUX 38		Ref (G98fb)
R32			(MC16	FB)  : MUX 39		Ref (G106fb)

FanIn assignment for block D [35]
{
A0,A5,A4,A6,A7,A3,A1,A2,
Com_Ctrl_360,
D3,D5,D2,D4,D0,D1,
R12,R15,R16,R10,R13,R17,R14,R11,
SECADR_PIN,
XXL_370,XXL_368,XXL_365,XXL_363,XXL_369,XXL_364,XXL_366,XXL_367,
nRD,nWR,nIORQ,
}
Multiplexer assignment for block D
nRD			(MC26	P)   : MUX 0		Ref (A13p)
D3			(MC13	P)   : MUX 1		Ref (D56p)
D5			(MC10	P)   : MUX 3		Ref (D53p)
D2			(MC14	P)   : MUX 4		Ref (D57p)
XXL_370			(MC23	FB)  : MUX 5		Ref (E79fb)
nWR			(MC25	P)   : MUX 6		Ref (A11p)
R12			(MC17	FB)  : MUX 7		Ref (D60fb)
A0			(MC32	P)   : MUX 9		Ref (B24p)
R15			(MC8	FB)  : MUX 10		Ref (D50fb)
D4			(MC11	P)   : MUX 11		Ref (D54p)
A5			(MC35	P)   : MUX 12		Ref (C46p)
A4			(MC28	P)   : MUX 13		Ref (B17p)
A6			(MC34	P)   : MUX 14		Ref (C45p)
R16			(MC4	FB)  : MUX 15		Ref (C41fb)
XXL_368			(MC21	FB)  : MUX 16		Ref (E70fb)
SECADR_PIN		(MC24	P)   : MUX 17		Ref (G104p)
A7			(MC33	P)   : MUX 18		Ref (C43p)
R10			(MC15	FB)  : MUX 19		Ref (D58fb)
R13			(MC9	FB)  : MUX 20		Ref (D52fb)
XXL_365			(MC7	FB)  : MUX 21		Ref (C48fb)
nIORQ			(MC27	P)   : MUX 22		Ref (A14p)
Com_Ctrl_360		(MC19	FB)  : MUX 23		Ref (D64fb)
XXL_363			(MC1	FB)  : MUX 25		Ref (B31fb)
D0			(MC18	P)   : MUX 26		Ref (D61p)
A3			(MC29	P)   : MUX 27		Ref (B19p)
R17			(MC3	FB)  : MUX 28		Ref (C40fb)
A1			(MC31	P)   : MUX 29		Ref (B22p)
D1			(MC16	P)   : MUX 30		Ref (D59p)
A2			(MC30	P)   : MUX 31		Ref (B21p)
XXL_369			(MC20	FB)  : MUX 32		Ref (E68fb)
XXL_364			(MC2	FB)  : MUX 33		Ref (B32fb)
R14			(MC22	FB)  : MUX 35		Ref (E74fb)
XXL_366			(MC6	FB)  : MUX 37		Ref (C47fb)
R11			(MC12	FB)  : MUX 38		Ref (D55fb)
XXL_367			(MC5	FB)  : MUX 39		Ref (C46fb)

FanIn assignment for block E [40]
{
A0,A13,A12,A7,A5,A1,A15,A4,A8,A11,A9,A10,A3,A2,A6,A14,
CLK,
D4,
PRIM5,PRIM6,PRIM7,
R47,R46,R37,R36,R26,R45,R27,R35,R25,
SEC6,SEC5,SEC7,
nRD,nWR,nMREQ,nNMI,nBUScon,nIORQ,nINT,
}
Multiplexer assignment for block E
nRD			(MC18	P)   : MUX 0		Ref (A13p)
PRIM5			(MC13	FB)  : MUX 1		Ref (D62fb)
R47			(MC3	FB)  : MUX 2		Ref (C35fb)
A0			(MC25	P)   : MUX 3		Ref (B24p)
R46			(MC2	FB)  : MUX 4		Ref (C34fb)
A13			(MC26	P)   : MUX 5		Ref (C33p)
nWR			(MC17	P)   : MUX 6		Ref (A11p)
D4			(MC12	P)   : MUX 7		Ref (D54p)
R37			(MC4	FB)  : MUX 8		Ref (C36fb)
A12			(MC27	P)   : MUX 9		Ref (C35p)
A7			(MC32	P)   : MUX 10		Ref (C43p)
PRIM6			(MC8	FB)  : MUX 11		Ref (C42fb)
A5			(MC34	P)   : MUX 12		Ref (C46p)
A1			(MC24	P)   : MUX 13		Ref (B22p)
A15			(MC35	P)   : MUX 14		Ref (D62p)
A4			(MC21	P)   : MUX 15		Ref (B17p)
A8			(MC31	P)   : MUX 16		Ref (C41p)
SEC6			(MC11	FB)  : MUX 17		Ref (C45fb)
nMREQ			(MC20	P)   : MUX 18		Ref (A16p)
A11			(MC28	P)   : MUX 19		Ref (C37p)
nNMI			(MC39	P)   : MUX 20		Ref (E73p)
A9			(MC30	P)   : MUX 21		Ref (C40p)
R36			(MC5	FB)  : MUX 22		Ref (C37fb)
nBUScon			(MC40	P)   : MUX 23		Ref (H115p)
R26			(MC6	FB)  : MUX 24		Ref (C38fb)
A10			(MC29	P)   : MUX 25		Ref (C38p)
nIORQ			(MC19	P)   : MUX 26		Ref (A14p)
A3			(MC22	P)   : MUX 27		Ref (B19p)
R45			(MC14	FB)  : MUX 28		Ref (G97fb)
nINT			(MC38	P)   : MUX 29		Ref (E72p)
SEC5			(MC1	FB)  : MUX 30		Ref (B21fb)
CLK			(MC37	P)   : MUX 31		Ref (E70p)
R27			(MC7	FB)  : MUX 32		Ref (C39fb)
A2			(MC23	P)   : MUX 33		Ref (B21p)
A6			(MC33	P)   : MUX 34		Ref (C45p)
PRIM7			(MC9	FB)  : MUX 35		Ref (C43fb)
R35			(MC15	FB)  : MUX 36		Ref (G101fb)
R25			(MC16	FB)  : MUX 37		Ref (G108fb)
A14			(MC36	P)   : MUX 38		Ref (D64p)
SEC7			(MC10	FB)  : MUX 39		Ref (C44fb)

FanIn assignment for block F [40]
{
ATCLK,A15,A14,
CLKi,
INT,
PRIM0,PRIM4,PRIM6,PRIM1,PRIM5,PRIM3,PRIM2,PRIM7,
R44,R21,R41,R14,R34,R23,R24,R12,R31,R22,R11,R32,R33,
SEC4,SEC6,SEC7,SEC3,SEC2,SEC1,SEC5,SEC0,
XCLK,
nBUSRQ,nMREQ,nBUSACK,nBUSRD,nHALT,
}
Multiplexer assignment for block F
nBUSRQ			(MC32	P)   : MUX 0		Ref (B30p)
INT			(MC36	P)   : MUX 1		Ref (F83p)
SEC4			(MC4	FB)  : MUX 2		Ref (B20fb)
ATCLK			(MC25	P)   : MUX 3		Ref (F81p)
nMREQ			(MC31	P)   : MUX 4		Ref (A16p)
SEC6			(MC16	FB)  : MUX 5		Ref (C45fb)
PRIM0			(MC2	FB)  : MUX 6		Ref (B18fb)
SEC7			(MC15	FB)  : MUX 7		Ref (C44fb)
SEC3			(MC6	FB)  : MUX 8		Ref (B22fb)
PRIM4			(MC20	FB)  : MUX 9		Ref (D63fb)
R44			(MC21	FB)  : MUX 10		Ref (E71fb)
PRIM6			(MC13	FB)  : MUX 11		Ref (C42fb)
SEC2			(MC8	FB)  : MUX 12		Ref (B24fb)
R21			(MC30	FB)  : MUX 13		Ref (G112fb)
nBUSACK			(MC35	P)   : MUX 14		Ref (E80p)
R41			(MC10	FB)  : MUX 15		Ref (B27fb)
PRIM1			(MC3	FB)  : MUX 16		Ref (B19fb)
R14			(MC24	FB)  : MUX 17		Ref (E74fb)
SEC1			(MC7	FB)  : MUX 18		Ref (B23fb)
R34			(MC23	FB)  : MUX 19		Ref (E73fb)
R23			(MC27	FB)  : MUX 20		Ref (G103fb)
PRIM5			(MC19	FB)  : MUX 21		Ref (D62fb)
R24			(MC22	FB)  : MUX 22		Ref (E72fb)
nBUSRD			(MC37	P)   : MUX 23		Ref (G101p)
PRIM3			(MC12	FB)  : MUX 24		Ref (C33fb)
R12			(MC18	FB)  : MUX 25		Ref (D60fb)
PRIM2			(MC1	FB)  : MUX 26		Ref (B17fb)
R31			(MC11	FB)  : MUX 27		Ref (B28fb)
A15			(MC33	P)   : MUX 28		Ref (D62p)
R22			(MC29	FB)  : MUX 29		Ref (G111fb)
A14			(MC34	P)   : MUX 30		Ref (D64p)
PRIM7			(MC14	FB)  : MUX 31		Ref (C43fb)
R11			(MC17	FB)  : MUX 32		Ref (D55fb)
R32			(MC28	FB)  : MUX 33		Ref (G106fb)
CLKi			(MC38	FB)  : MUX 34		Ref (OE2)
nHALT			(MC40	FB)  : MUX 35		Ref (OE1)
SEC5			(MC5	FB)  : MUX 36		Ref (B21fb)
SEC0			(MC9	FB)  : MUX 37		Ref (B25fb)
R33			(MC26	FB)  : MUX 38		Ref (G100fb)
XCLK			(MC39	FB)  : MUX 39		Ref (GCLK)

FanIn assignment for block G [26]
{
A8,A13,A0,A3,A1,A15,A12,A2,A11,A5,A9,A10,A7,A4,A6,A14,
D3,D5,D2,D1,D0,
nWR,nIORQ,nRFSH,nMREQ,nM1,
}
Multiplexer assignment for block G
D3			(MC2	P)   : MUX 1		Ref (D56p)
A8			(MC21	P)   : MUX 2		Ref (C41p)
D5			(MC1	P)   : MUX 3		Ref (D53p)
D2			(MC3	P)   : MUX 4		Ref (D57p)
A13			(MC16	P)   : MUX 5		Ref (C33p)
nWR			(MC6	P)   : MUX 6		Ref (A11p)
nIORQ			(MC7	P)   : MUX 8		Ref (A14p)
A0			(MC13	P)   : MUX 9		Ref (B24p)
A3			(MC10	P)   : MUX 11		Ref (B19p)
D1			(MC4	P)   : MUX 12		Ref (D59p)
A1			(MC12	P)   : MUX 13		Ref (B22p)
A15			(MC25	P)   : MUX 14		Ref (D62p)
A12			(MC17	P)   : MUX 15		Ref (C35p)
nRFSH			(MC14	P)   : MUX 16		Ref (B25p)
A2			(MC11	P)   : MUX 17		Ref (B21p)
nMREQ			(MC8	P)   : MUX 18		Ref (A16p)
A11			(MC18	P)   : MUX 19		Ref (C37p)
A5			(MC24	P)   : MUX 20		Ref (C46p)
A9			(MC20	P)   : MUX 21		Ref (C40p)
nM1			(MC15	P)   : MUX 24		Ref (B27p)
A10			(MC19	P)   : MUX 25		Ref (C38p)
A7			(MC22	P)   : MUX 28		Ref (C43p)
A4			(MC9	P)   : MUX 31		Ref (B17p)
A6			(MC23	P)   : MUX 34		Ref (C45p)
D0			(MC5	P)   : MUX 36		Ref (D61p)
A14			(MC26	P)   : MUX 38		Ref (D64p)

FanIn assignment for block H [38]
{
A1,A3,A7,A2,A4,A13,A5,A15,A6,A14,
PRIM0,PRIM7,PRIM4,PRIM1,PRIM3,PRIM2,PRIM6,PRIM5,
SEC6,SEC4,SEC2,SECADR_PIN,SEC1,SEC0,SEC7,SEC3,SEC5,
XXL_378,XXL_380,XXL_373,XXL_374,XXL_382,XXL_379,XXL_381,
nRD,nMREQ,nWR,nIORQ,
}
Multiplexer assignment for block H
nRD			(MC26	P)   : MUX 0		Ref (A13p)
SEC6			(MC19	FB)  : MUX 1		Ref (C45fb)
SEC4			(MC9	FB)  : MUX 2		Ref (B20fb)
XXL_378			(MC5	FB)  : MUX 3		Ref (A16fb)
nMREQ			(MC28	P)   : MUX 4		Ref (A16p)
XXL_380			(MC4	FB)  : MUX 5		Ref (A15fb)
nWR			(MC25	P)   : MUX 6		Ref (A11p)
A1			(MC32	P)   : MUX 7		Ref (B22p)
nIORQ			(MC27	P)   : MUX 8		Ref (A14p)
A3			(MC30	P)   : MUX 9		Ref (B19p)
A7			(MC34	P)   : MUX 10		Ref (C43p)
A2			(MC31	P)   : MUX 11		Ref (B21p)
SEC2			(MC13	FB)  : MUX 12		Ref (B24fb)
A4			(MC29	P)   : MUX 13		Ref (B17p)
PRIM0			(MC7	FB)  : MUX 14		Ref (B18fb)
SECADR_PIN		(MC24	P)   : MUX 15		Ref (G104p)
XXL_373			(MC22	FB)  : MUX 16		Ref (F84fb)
PRIM7			(MC17	FB)  : MUX 17		Ref (C43fb)
SEC1			(MC12	FB)  : MUX 18		Ref (B23fb)
PRIM4			(MC21	FB)  : MUX 19		Ref (D63fb)
PRIM1			(MC8	FB)  : MUX 20		Ref (B19fb)
A13			(MC33	P)   : MUX 21		Ref (C33p)
XXL_374			(MC23	FB)  : MUX 23		Ref (F95fb)
PRIM3			(MC15	FB)  : MUX 24		Ref (C33fb)
SEC0			(MC14	FB)  : MUX 25		Ref (B25fb)
A5			(MC36	P)   : MUX 26		Ref (C46p)
XXL_382			(MC3	FB)  : MUX 27		Ref (A14fb)
A15			(MC37	P)   : MUX 28		Ref (D62p)
SEC7			(MC18	FB)  : MUX 29		Ref (C44fb)
SEC3			(MC11	FB)  : MUX 30		Ref (B22fb)
XXL_379			(MC2	FB)  : MUX 31		Ref (A13fb)
PRIM2			(MC6	FB)  : MUX 32		Ref (B17fb)
PRIM6			(MC16	FB)  : MUX 33		Ref (C42fb)
A6			(MC35	P)   : MUX 34		Ref (C45p)
SEC5			(MC10	FB)  : MUX 36		Ref (B21fb)
XXL_381			(MC1	FB)  : MUX 37		Ref (A12fb)
A14			(MC38	P)   : MUX 38		Ref (D64p)
PRIM5			(MC20	FB)  : MUX 39		Ref (D62fb)

Creating JEDEC file C:\USERS\BERT_\DOCUMENTS\01_CCZ80_COMP\CCZ80_MPU\CPLD\MAIN\MAIN.jed ...

PQFP100 programmed logic:
-----------------------------------
ATCLK.D = !ATCLK.Q;

D0.L = ((!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R10.Q)
	# XXL_363);

D3.L = ((!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R13.Q)
	# XXL_364);

D1.L = ((!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R11.Q)
	# XXL_365);

D2.L = ((!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R12.Q)
	# XXL_366);

D4.L = ((!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R14.Q)
	# XXL_367);

D5.L = ((!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R15.Q)
	# XXL_368);

D6.L = ((!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R16.Q)
	# XXL_369);

D7.L = ((!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R17.Q)
	# XXL_370);

PRIM0.D = D0.PIN;

!Debug1 = (!CLK & !nINT & !nNMI);

Debug2 = nBUScon;

PRIM1.D = D1.PIN;

PRIM2.D = D2.PIN;

PRIM3.D = D3.PIN;

PRIM4.D = D4.PIN;

PRIM5.D = D5.PIN;

PRIM6.D = D6.PIN;

PRIM7.D = D7.PIN;

R10.D = D0.PIN;

R11.D = D1.PIN;

R12.D = D2.PIN;

R13.D = D3.PIN;

R14.D = D4.PIN;

R15.D = D5.PIN;

R16.D = D6.PIN;

R17.D = D7.PIN;

R20.D = D0.PIN;

R21.D = D1.PIN;

R22.D = D2.PIN;

R23.D = D3.PIN;

R24.D = D4.PIN;

R25.D = D5.PIN;

R26.D = D6.PIN;

R27.D = D7.PIN;

R30.D = D0.PIN;

R31.D = D1.PIN;

R32.D = D2.PIN;

R33.D = D3.PIN;

R34.D = D4.PIN;

R35.D = D5.PIN;

R36.D = D6.PIN;

R37.D = D7.PIN;

R40.D = D0.PIN;

R41.D = D1.PIN;

R42.D = D2.PIN;

R43.D = D3.PIN;

R44.D = D4.PIN;

R45.D = D5.PIN;

R46.D = D6.PIN;

R47.D = D7.PIN;

RomA13 = A13;

RomA14 = (XXL_382
	# XXL_381);

RomA17 = ((!A14 & !A15 & !nMREQ & PRIM0.Q & PRIM1.Q & SEC0.Q & SEC1.Q & R13.Q)
	# XXL_371
	# (A14 & A15 & !nMREQ & PRIM6.Q & PRIM7.Q & SEC6.Q & SEC7.Q & R43.Q)
	# (!A14 & !A15 & !nMREQ & !PRIM0.Q & !PRIM1.Q & SEC0.Q & SEC1.Q));

RomA15 = (XXL_384
	# XXL_383);

RomA16 = ((A14 & A15 & !nMREQ & !PRIM6.Q & !PRIM7.Q & !SEC7.Q)
	# XXL_372
	# (A14 & A15 & !nMREQ & PRIM6.Q & PRIM7.Q & SEC7.Q & R42.Q & SEC6.Q)
	# (A14 & !A15 & !nMREQ & !PRIM2.Q & !PRIM3.Q & !SEC3.Q));

SEC0.D = D0.PIN;

RomA18 = (XXL_373
	# XXL_374
	# (A14 & !A15 & !nMREQ & PRIM2.Q & PRIM3.Q & !SEC2.Q & !SEC3.Q)
	# (A14 & A15 & !nMREQ & PRIM6.Q & PRIM7.Q & !SEC6.Q & !SEC7.Q));

!RomA19 = ((!A14 & !A15 & !nMREQ & PRIM0.Q & PRIM1.Q & SEC0.Q & SEC1.Q)
	# (A14 & A15 & !nMREQ & PRIM6.Q & PRIM7.Q & SEC6.Q & SEC7.Q)
	# (!A14 & A15 & !nMREQ & PRIM4.Q & PRIM5.Q & SEC4.Q & SEC5.Q)
	# (A14 & !A15 & !nMREQ & PRIM2.Q & PRIM3.Q & SEC2.Q & SEC3.Q));

SEC1.D = D1.PIN;

SEC2.D = D2.PIN;

SEC3.D = D3.PIN;

SEC4.D = D4.PIN;

SEC5.D = D5.PIN;

SEC6.D = D6.PIN;

SEC7.D = D7.PIN;

Z80RESET = nRESET;

SECADR_PIN = (A3 & A5 & A7 & A13 & !nMREQ & A0 & A1 & A2 & A4 & A6 & A8 & A9 & A10 & A11 & A12 & A14 & A15);

!SpareCS = (A8 & A9 & A10 & A11 & A12 & A13);

!nCS_RTC = (!A1 & A2 & !A3 & A4 & A5 & !A6 & A7 & !nIORQ);

nCLK = XCLK;

!nCS_HD = (!A3 & A4 & !A5 & A6 & A7 & !nIORQ);

!nCS_Serial = (!A3 & !A4 & !A5 & !A6 & A7 & !nIORQ);

nRomCS = (XXL_375
	# XXL_376
	# XXL_377
	# nMREQ
	# (!A14 & !A15 & !SEC0.Q & SEC1.Q));

!nRomWE = (XXL_379
	# XXL_380
	# (!A14 & A15 & PRIM4.Q & PRIM5.Q & SEC4.Q & SEC5.Q & !nMREQ & !nWR)
	# XXL_378);

!nSLT1 = ((!A14 & !A15 & !nMREQ & PRIM0.Q & !PRIM1.Q)
	# (A14 & A15 & !nMREQ & PRIM6.Q & !PRIM7.Q)
	# (!A14 & A15 & !nMREQ & PRIM4.Q & !PRIM5.Q)
	# (A14 & !A15 & !nMREQ & PRIM2.Q & !PRIM3.Q));

!test1 = (!CLKi & !INT & !nBUSACK & !nBUSRD & !nBUSRQ & !nHALT);

!nSLT2 = ((A14 & A15 & !nMREQ & !PRIM6.Q & PRIM7.Q)
	# (A14 & !A15 & !nMREQ & !PRIM2.Q & PRIM3.Q)
	# (!A14 & !A15 & !nMREQ & !PRIM0.Q & PRIM1.Q)
	# (!A14 & A15 & !nMREQ & !PRIM4.Q & PRIM5.Q));

nWAIT.L = DOWAIT;

!test2 = (!nM1 & !nRFSH);

!NOWAIT = (nCS_HD & nCS_RTC & nCS_Serial & DOWAIT);

!nRomRD = (!SECADR_PIN & !nRD);

!DOWAIT = (nRESET & nResume & NOWAIT);

!Com_Ctrl_359 = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & A8 & A9 & A10 & A11 & A12 & A13 & A14 & A15 & !nMREQ & !nWR);

Com_Ctrl_360 = ((!nRD & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !A0 & !A1)
	# (!nRD & SECADR_PIN)
	# (!nRD & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ));

!FB_361 = (nCS_RTC & nCS_Serial & nCS_HD);

!FB_362 = (nCS_RTC & nCS_Serial & nCS_HD);

XXL_363 = ((A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R40.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nRD & A8 & A9 & A10 & A11 & A12 & A13 & A14 & A15 & !SEC0.Q & !nMREQ)
	# (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nRD & PRIM0.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R30.Q)
	# (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R20.Q));

XXL_364 = ((A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R43.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nRD & A8 & A9 & A10 & A11 & A12 & A13 & A14 & A15 & !SEC3.Q & !nMREQ)
	# (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nRD & PRIM3.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R33.Q)
	# (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R23.Q));

XXL_365 = ((A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R41.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nRD & A8 & A9 & A10 & A11 & A12 & A13 & A14 & A15 & !SEC1.Q & !nMREQ)
	# (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nRD & PRIM1.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R31.Q)
	# (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R21.Q));

XXL_366 = ((A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R42.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nRD & A8 & A9 & A10 & A11 & A12 & A13 & A14 & A15 & !SEC2.Q & !nMREQ)
	# (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nRD & PRIM2.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R32.Q)
	# (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R22.Q));

XXL_367 = ((A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R44.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nRD & A8 & A9 & A10 & A11 & A12 & A13 & A14 & A15 & !SEC4.Q & !nMREQ)
	# (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nRD & PRIM4.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R34.Q)
	# (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R24.Q));

XXL_368 = ((A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R45.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nRD & A8 & A9 & A10 & A11 & A12 & A13 & A14 & A15 & !SEC5.Q & !nMREQ)
	# (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nRD & PRIM5.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R35.Q)
	# (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R25.Q));

XXL_369 = ((A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R46.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nRD & A8 & A9 & A10 & A11 & A12 & A13 & A14 & A15 & !SEC6.Q & !nMREQ)
	# (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nRD & PRIM6.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R36.Q)
	# (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R26.Q));

XXL_370 = ((A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R47.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nRD & A8 & A9 & A10 & A11 & A12 & A13 & A14 & A15 & !SEC7.Q & !nMREQ)
	# (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nRD & PRIM7.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R37.Q)
	# (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R27.Q));

XXL_371 = ((A14 & !A15 & !nMREQ & !PRIM2.Q & !PRIM3.Q & SEC2.Q & SEC3.Q)
	# (A14 & !A15 & !nMREQ & PRIM2.Q & PRIM3.Q & SEC2.Q & SEC3.Q & R23.Q)
	# (A14 & A15 & !nMREQ & !PRIM6.Q & !PRIM7.Q & SEC6.Q & SEC7.Q)
	# (!A14 & A15 & !nMREQ & !PRIM4.Q & !PRIM5.Q & SEC4.Q & SEC5.Q)
	# (!A14 & A15 & !nMREQ & PRIM4.Q & PRIM5.Q & SEC4.Q & SEC5.Q & R33.Q));

XXL_372 = ((A14 & !A15 & !nMREQ & PRIM2.Q & PRIM3.Q & SEC3.Q & R22.Q & SEC2.Q)
	# (!A14 & A15 & !nMREQ & !PRIM4.Q & !PRIM5.Q & !SEC5.Q)
	# (!A14 & A15 & !nMREQ & PRIM4.Q & PRIM5.Q & SEC5.Q & R32.Q & SEC4.Q)
	# (!A14 & !A15 & !nMREQ & !PRIM0.Q & !PRIM1.Q & !SEC1.Q)
	# (!A14 & !A15 & !nMREQ & PRIM0.Q & PRIM1.Q & SEC1.Q & R12.Q & SEC0.Q));

XXL_373 = ((!A14 & !A15 & !nMREQ & !PRIM0.Q & !PRIM1.Q & SEC0.Q & !SEC1.Q)
	# (!A14 & !A15 & !nMREQ & PRIM0.Q & PRIM1.Q & SEC0.Q & SEC1.Q & R14.Q)
	# (!A14 & A15 & !nMREQ & !PRIM4.Q & !PRIM5.Q & SEC4.Q & !SEC5.Q)
	# (!A14 & A15 & !nMREQ & PRIM4.Q & PRIM5.Q & !SEC4.Q & !SEC5.Q)
	# (!A14 & !A15 & !nMREQ & PRIM0.Q & PRIM1.Q & !SEC0.Q & !SEC1.Q));

XXL_374 = ((A14 & !A15 & !nMREQ & PRIM2.Q & PRIM3.Q & SEC2.Q & SEC3.Q & R24.Q)
	# (A14 & A15 & !nMREQ & !PRIM6.Q & !PRIM7.Q & SEC6.Q & !SEC7.Q)
	# (A14 & A15 & !nMREQ & PRIM6.Q & PRIM7.Q & SEC6.Q & SEC7.Q & R44.Q)
	# (!A14 & A15 & !nMREQ & PRIM4.Q & PRIM5.Q & SEC4.Q & SEC5.Q & R34.Q)
	# (A14 & !A15 & !nMREQ & !PRIM2.Q & !PRIM3.Q & SEC2.Q & !SEC3.Q));

XXL_375 = ((!A14 & !A15 & PRIM0.Q & !PRIM1.Q)
	# (!A14 & A15 & !SEC4.Q & SEC5.Q)
	# (!A14 & A15 & !PRIM4.Q & PRIM5.Q)
	# (!A14 & !A15 & !PRIM0.Q & PRIM1.Q)
	# (!A14 & !A15 & PRIM0.Q & SEC0.Q & !SEC1.Q));

XXL_376 = ((A14 & !A15 & !SEC2.Q & SEC3.Q)
	# (A14 & !A15 & !PRIM2.Q & PRIM3.Q)
	# (A14 & !A15 & SEC2.Q & !SEC3.Q & PRIM2.Q)
	# (!A14 & A15 & PRIM4.Q & SEC4.Q & !SEC5.Q)
	# (!A14 & A15 & PRIM4.Q & !PRIM5.Q));

XXL_377 = ((A14 & A15 & !PRIM6.Q & PRIM7.Q)
	# (A14 & A15 & SEC6.Q & !SEC7.Q & PRIM6.Q)
	# (A14 & A15 & PRIM6.Q & !PRIM7.Q)
	# (A14 & !A15 & PRIM2.Q & !PRIM3.Q)
	# (A14 & A15 & !SEC6.Q & SEC7.Q));

XXL_378 = ((!A14 & !A15 & !nMREQ & !nWR & PRIM0.Q & PRIM1.Q & SEC0.Q & SEC1.Q)
	# (A14 & A15 & !nMREQ & !nWR & PRIM6.Q & PRIM7.Q & !SEC6.Q & !SEC7.Q & !nWE)
	# (!A14 & A15 & !nMREQ & !nWR & !nWE & PRIM4.Q & PRIM5.Q & !SEC4.Q & !SEC5.Q)
	# (A14 & A15 & !nMREQ & !nWR & PRIM6.Q & PRIM7.Q & SEC6.Q & SEC7.Q)
	# (A14 & !A15 & !nMREQ & !nWR & PRIM2.Q & PRIM3.Q & SEC2.Q & SEC3.Q));

XXL_379 = ((!A14 & !A15 & !nMREQ & !nWR & !nWE & !PRIM0.Q & !PRIM1.Q & SEC0.Q & SEC1.Q)
	# (A14 & !A15 & !nMREQ & !nWR & !nWE & !PRIM2.Q & !PRIM3.Q & SEC2.Q & SEC3.Q)
	# (!A14 & A15 & !nMREQ & !nWR & !nWE & !PRIM4.Q & !PRIM5.Q & SEC4.Q & SEC5.Q)
	# (A14 & !A15 & !nMREQ & !nWR & !nWE & PRIM2.Q & PRIM3.Q & !SEC2.Q & !SEC3.Q)
	# (!A14 & !A15 & !nMREQ & !nWR & !nWE & PRIM0.Q & PRIM1.Q & !SEC0.Q & !SEC1.Q));

XXL_380 = ((A14 & A15 & !nMREQ & !nWR & !PRIM6.Q & !PRIM7.Q & !SEC6.Q & !SEC7.Q)
	# (!A14 & !A15 & !nMREQ & !nWR & !nWE & !PRIM0.Q & !PRIM1.Q & !SEC0.Q & !SEC1.Q)
	# (!A14 & A15 & !nMREQ & !nWR & !nWE & !PRIM4.Q & !PRIM5.Q & !SEC4.Q & !SEC5.Q)
	# (A14 & A15 & !nMREQ & !nWR & !nWE & !PRIM6.Q & !PRIM7.Q & SEC6.Q & SEC7.Q)
	# (A14 & !A15 & !nMREQ & !nWR & !nWE & !PRIM2.Q & !PRIM3.Q & !SEC2.Q & !SEC3.Q));

XXL_381 = ((A14 & !A15 & !nMREQ & !PRIM2.Q & !PRIM3.Q & SEC2.Q)
	# (A14 & !A15 & !nMREQ & PRIM2.Q & PRIM3.Q & SEC3.Q & SEC2.Q & R20.Q)
	# (A14 & A15 & !nMREQ & !PRIM6.Q & !PRIM7.Q & !SEC7.Q)
	# (A14 & A15 & !nMREQ & PRIM6.Q & PRIM7.Q & !SEC7.Q & !SEC6.Q)
	# (A14 & !A15 & !nMREQ & PRIM2.Q & PRIM3.Q & !SEC3.Q & !SEC2.Q));

XXL_382 = ((A14 & A15 & !nMREQ & PRIM6.Q & PRIM7.Q & SEC6.Q & SEC7.Q & R40.Q)
	# (!A14 & !A15 & !nMREQ & PRIM0.Q & PRIM1.Q & R10.Q & SEC0.Q & SEC1.Q)
	# (!A14 & A15 & !nMREQ & PRIM4.Q & PRIM5.Q & R30.Q & SEC4.Q & SEC5.Q)
	# (A14 & !A15 & !nMREQ & !PRIM2.Q & !PRIM3.Q & !SEC3.Q)
	# (A14 & A15 & !nMREQ & !PRIM6.Q & !PRIM7.Q & SEC6.Q));

XXL_383 = ((A14 & !A15 & !nMREQ & PRIM2.Q & PRIM3.Q & R21.Q & SEC2.Q & SEC3.Q)
	# (!A14 & A15 & !nMREQ & !PRIM4.Q & !PRIM5.Q & !SEC5.Q)
	# (!A14 & A15 & !nMREQ & PRIM4.Q & PRIM5.Q & !SEC5.Q & !SEC4.Q)
	# (!A14 & A15 & !nMREQ & !PRIM4.Q & !PRIM5.Q & SEC4.Q)
	# (!A14 & !A15 & !nMREQ & PRIM0.Q & PRIM1.Q & R11.Q & SEC0.Q & SEC1.Q));

XXL_384 = ((A14 & A15 & !nMREQ & PRIM6.Q & PRIM7.Q & SEC6.Q & SEC7.Q & R41.Q)
	# (A14 & A15 & !nMREQ & !PRIM6.Q & !PRIM7.Q & !SEC7.Q)
	# (A14 & A15 & !nMREQ & PRIM6.Q & PRIM7.Q & !SEC6.Q & !SEC7.Q)
	# (A14 & A15 & !nMREQ & !PRIM6.Q & !PRIM7.Q & SEC6.Q)
	# (!A14 & A15 & !nMREQ & PRIM4.Q & PRIM5.Q & SEC5.Q & SEC4.Q & R31.Q));

ATCLK.C = XCLK;

D0.LE = Com_Ctrl_360;

D0.OE = Com_Ctrl_360;

D3.LE = Com_Ctrl_360;

D3.OE = Com_Ctrl_360;

D1.LE = Com_Ctrl_360;

D1.OE = Com_Ctrl_360;

D2.LE = Com_Ctrl_360;

D2.OE = Com_Ctrl_360;

D4.LE = Com_Ctrl_360;

D4.OE = Com_Ctrl_360;

D5.LE = Com_Ctrl_360;

D5.OE = Com_Ctrl_360;

D6.LE = Com_Ctrl_360;

D6.OE = Com_Ctrl_360;

D7.LE = Com_Ctrl_360;

D7.OE = Com_Ctrl_360;

PRIM0.C = (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nWR);

PRIM0.AR = !nRESET;

PRIM1.C = (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nWR);

PRIM1.AR = !nRESET;

PRIM2.C = (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nWR);

PRIM2.AR = !nRESET;

PRIM3.C = (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nWR);

PRIM3.AR = !nRESET;

PRIM4.C = (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nWR);

PRIM4.AR = !nRESET;

PRIM5.C = (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nWR);

PRIM5.AR = !nRESET;

PRIM6.C = (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nWR);

PRIM6.AR = !nRESET;

PRIM7.C = (!A0 & !A1 & !A2 & A3 & !A4 & A5 & !A6 & A7 & !nIORQ & !nWR);

PRIM7.AR = !nRESET;

R10.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R10.AR = !nRESET;

R11.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R11.AR = !nRESET;

R12.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R12.AR = !nRESET;

R13.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R13.AR = !nRESET;

R14.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R14.AR = !nRESET;

R15.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R15.AR = !nRESET;

R16.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R16.AR = !nRESET;

R17.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R17.AR = !nRESET;

R20.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R20.AP = !nRESET;

R21.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R21.AR = !nRESET;

R22.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R22.AR = !nRESET;

R23.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R23.AR = !nRESET;

R24.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R24.AR = !nRESET;

R25.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R25.AR = !nRESET;

R26.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R26.AR = !nRESET;

R27.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R27.AR = !nRESET;

R30.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R30.AR = !nRESET;

R31.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R31.AP = !nRESET;

R32.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R32.AR = !nRESET;

R33.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R33.AR = !nRESET;

R34.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R34.AR = !nRESET;

R35.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R35.AR = !nRESET;

R36.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R36.AR = !nRESET;

R37.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R37.AR = !nRESET;

R40.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R40.AP = !nRESET;

R41.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R41.AP = !nRESET;

R42.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R42.AR = !nRESET;

R43.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R43.AR = !nRESET;

R44.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R44.AR = !nRESET;

R45.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R45.AR = !nRESET;

R46.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R46.AR = !nRESET;

R47.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R47.AR = !nRESET;

SEC0.C = Com_Ctrl_359;

SEC0.AR = !nRESET;

SEC1.C = Com_Ctrl_359;

SEC1.AR = !nRESET;

SEC2.C = Com_Ctrl_359;

SEC2.AR = !nRESET;

SEC3.C = Com_Ctrl_359;

SEC3.AR = !nRESET;

SEC4.C = Com_Ctrl_359;

SEC4.AR = !nRESET;

SEC5.C = Com_Ctrl_359;

SEC5.AR = !nRESET;

SEC6.C = Com_Ctrl_359;

SEC6.AR = !nRESET;

SEC7.C = Com_Ctrl_359;

SEC7.AR = !nRESET;

nWAIT.LE = FB_361;

nWAIT.OE = FB_362;


PQFP100 Pin/Node Placement:
------------------------------------
Pin 1  = nRomCS; /* MC 6 */
Pin 2  = RomA17; /* MC 5 */
Pin 3  = RomA16; /* MC 3 */
Pin 4  = RomA15; /* MC 1 */
Pin 6  = TDI; /* MC 32 */
Pin 7  = nBUSRQ; /* MC 30 */
Pin 8  = Z80RESET; /* MC 29 */
Pin 9  = nM1; /* MC 27 */
Pin 10 = nRFSH; /* MC 25 */ 
Pin 11 = A0; /* MC 24 */ 
Pin 12 = A1; /* MC 22 */ 
Pin 14 = A2; /* MC 21 */ 
Pin 15 = A3; /* MC 19 */ 
Pin 16 = A4; /* MC 17 */ 
Pin 17 = TMS; /* MC 48 */ 
Pin 18 = A5; /* MC 46 */ 
Pin 19 = A6; /* MC 45 */ 
Pin 21 = A7; /* MC 43 */ 
Pin 22 = A8; /* MC 41 */ 
Pin 23 = A9; /* MC 40 */ 
Pin 24 = A10; /* MC 38 */ 
Pin 25 = A11; /* MC 37 */ 
Pin 26 = A12; /* MC 35 */ 
Pin 27 = A13; /* MC 33 */ 
Pin 29 = A14; /* MC 64 */ 
Pin 30 = A15; /* MC 62 */ 
Pin 31 = D0; /* MC 61 */ 
Pin 32 = D1; /* MC 59 */ 
Pin 33 = D2; /* MC 57 */ 
Pin 34 = D3; /* MC 56 */ 
Pin 35 = D4; /* MC 54 */ 
Pin 37 = D5; /* MC 53 */ 
Pin 38 = D6; /* MC 51 */ 
Pin 39 = D7; /* MC 49 */ 
Pin 46 = CLK; /* MC 70 */ 
Pin 47 = nINT; /* MC 72 */ 
Pin 48 = nNMI; /* MC 73 */ 
Pin 49 = Debug1; /* MC 75 */ 
Pin 50 = Debug2; /* MC 77 */ 
Pin 52 = nBUSACK; /* MC 80 */ 
Pin 54 = ATCLK; /* MC 81 */ 
Pin 55 = INT; /* MC 83 */ 
Pin 56 = nCLK; /* MC 85 */ 
Pin 57 = test1; /* MC 86 */ 
Pin 62 = nSLT2; /* MC 93 */ 
Pin 63 = nSLT1; /* MC 94 */ 
Pin 64 = TCK; /* MC 96 */ 
Pin 66 = test2; /* MC 99 */ 
Pin 67 = nBUSRD; /* MC 101 */ 
Pin 69 = nResume; /* MC 102 */ 
Pin 70 = SECADR_PIN; /* MC 104 */ 
Pin 72 = nCS_Serial; /* MC 107 */ 
Pin 73 = nCS_HD; /* MC 109 */ 
Pin 74 = SpareCS; /* MC 110 */ 
Pin 75 = TDO; /* MC 112 */ 
Pin 77 = nCS_RTC; /* MC 113 */ 
Pin 78 = nBUScon; /* MC 115 */ 
Pin 81 = RomA14; /* MC 120 */ 
Pin 82 = RomA13; /* MC 121 */ 
Pin 83 = RomA19; /* MC 123 */ 
Pin 85 = RomA18; /* MC 125 */ 
Pin 86 = nRomRD; /* MC 126 */ 
Pin 87 = nRomWE; /* MC 128 */ 
Pin 89 = XCLK;
Pin 90 = nHALT;
Pin 91 = nRESET;
Pin 92 = CLKi;
Pin 94 = nMREQ; /* MC 16 */ 
Pin 95 = nIORQ; /* MC 14 */ 
Pin 96 = nRD; /* MC 13 */ 
Pin 98 = nWR; /* MC 11 */ 
Pin 99 = nWE; /* MC  9 */
Pin 100 = nWAIT; /* MC  8 */
PINNODE 304 = FB_362; /* MC 4 Foldback */
PINNODE 305 = FB_361; /* MC 5 Foldback */
PINNODE 307 = DOWAIT; /* MC 7 Foldback */
PINNODE 308 = NOWAIT; /* MC 8 Foldback */
PINNODE 330 = Com_Ctrl_359; /* MC 30 Foldback */
PINNODE 345 = Com_Ctrl_359; /* MC 45 Foldback */
PINNODE 609 = XXL_376; /* MC 9 Feedback */
PINNODE 610 = XXL_375; /* MC 10 Feedback */
PINNODE 611 = XXL_377; /* MC 11 Feedback */
PINNODE 612 = XXL_381; /* MC 12 Feedback */
PINNODE 613 = XXL_379; /* MC 13 Feedback */
PINNODE 614 = XXL_382; /* MC 14 Feedback */
PINNODE 615 = XXL_380; /* MC 15 Feedback */
PINNODE 616 = XXL_378; /* MC 16 Feedback */
PINNODE 617 = PRIM2; /* MC 17 Feedback */
PINNODE 618 = PRIM0; /* MC 18 Feedback */
PINNODE 619 = PRIM1; /* MC 19 Feedback */
PINNODE 620 = SEC4; /* MC 20 Feedback */
PINNODE 621 = SEC5; /* MC 21 Feedback */
PINNODE 622 = SEC3; /* MC 22 Feedback */
PINNODE 623 = SEC1; /* MC 23 Feedback */
PINNODE 624 = SEC2; /* MC 24 Feedback */
PINNODE 625 = SEC0; /* MC 25 Feedback */
PINNODE 626 = R40; /* MC 26 Feedback */
PINNODE 627 = R41; /* MC 27 Feedback */
PINNODE 628 = R31; /* MC 28 Feedback */
PINNODE 630 = R20; /* MC 30 Feedback */
PINNODE 631 = XXL_363; /* MC 31 Feedback */
PINNODE 632 = XXL_364; /* MC 32 Feedback */
PINNODE 633 = PRIM3; /* MC 33 Feedback */
PINNODE 634 = R46; /* MC 34 Feedback */
PINNODE 635 = R47; /* MC 35 Feedback */
PINNODE 636 = R37; /* MC 36 Feedback */
PINNODE 637 = R36; /* MC 37 Feedback */
PINNODE 638 = R26; /* MC 38 Feedback */
PINNODE 639 = R27; /* MC 39 Feedback */
PINNODE 640 = R17; /* MC 40 Feedback */
PINNODE 641 = R16; /* MC 41 Feedback */
PINNODE 642 = PRIM6; /* MC 42 Feedback */
PINNODE 643 = PRIM7; /* MC 43 Feedback */
PINNODE 644 = SEC7; /* MC 44 Feedback */
PINNODE 645 = SEC6; /* MC 45 Feedback */
PINNODE 646 = XXL_367; /* MC 46 Feedback */
PINNODE 647 = XXL_366; /* MC 47 Feedback */
PINNODE 648 = XXL_365; /* MC 48 Feedback */
PINNODE 650 = R15; /* MC 50 Feedback */
PINNODE 652 = R13; /* MC 52 Feedback */
PINNODE 655 = R11; /* MC 55 Feedback */
PINNODE 658 = R10; /* MC 58 Feedback */
PINNODE 660 = R12; /* MC 60 Feedback */
PINNODE 662 = PRIM5; /* MC 62 Feedback */
PINNODE 663 = PRIM4; /* MC 63 Feedback */
PINNODE 664 = Com_Ctrl_360; /* MC 64 Feedback */
PINNODE 668 = XXL_369; /* MC 68 Feedback */
PINNODE 670 = XXL_368; /* MC 70 Feedback */
PINNODE 671 = R44; /* MC 71 Feedback */
PINNODE 672 = R24; /* MC 72 Feedback */
PINNODE 673 = R34; /* MC 73 Feedback */
PINNODE 674 = R14; /* MC 74 Feedback */
PINNODE 679 = XXL_370; /* MC 79 Feedback */
PINNODE 684 = XXL_373; /* MC 84 Feedback */
PINNODE 690 = XXL_384; /* MC 90 Feedback */
PINNODE 691 = XXL_371; /* MC 91 Feedback */
PINNODE 692 = XXL_383; /* MC 92 Feedback */
PINNODE 695 = XXL_374; /* MC 95 Feedback */
PINNODE 696 = XXL_372; /* MC 96 Feedback */
PINNODE 697 = R45; /* MC 97 Feedback */
PINNODE 698 = R42; /* MC 98 Feedback */
PINNODE 700 = R33; /* MC 100 Feedback */
PINNODE 701 = R35; /* MC 101 Feedback */
PINNODE 702 = R30; /* MC 102 Feedback */
PINNODE 703 = R23; /* MC 103 Feedback */
PINNODE 705 = R43; /* MC 105 Feedback */
PINNODE 706 = R32; /* MC 106 Feedback */
PINNODE 708 = R25; /* MC 108 Feedback */
PINNODE 711 = R22; /* MC 111 Feedback */
PINNODE 712 = R21; /* MC 112 Feedback */

** Resource Usage **


DCERP Field = Summary of Allocations.
|||||
|||||_Preset [p,-]       ==  p = PT preset, - No Preset.
||||
||||__Reset [g,r,-]      ==  g= Global AR, r = PT reset, - No reset.
|||
|||___Clock Enable [e,-] ==  e = Product Term, - always enabled, - none.
||
||____Clock [c,g,-],     ==  c = Product term, g = Global term, - No Clock.
|
|_____Type [C,D,L,T],    ==  Register type C= combin, D=dff, L=latch, T=tff.

For input only = INPUT.

MCell Pin# Oe   PinDrive   DCERP  FBDrive      DCERP  Foldback     CascadeOut     TotPT output_slew
MC1   4    on   RomA15     C----  --                  --           --             2     slow
MC2   0         --                --                  --           --             0     slow
MC3   3    on   RomA16     C----  --                  --           --             4     slow
MC4   0         --                --                  FB_362       --             1     slow
MC5   2    on   RomA17     C----  --                  FB_361       --             5     slow
MC6   1    on   nRomCS     C----  --                  NA           --             5     slow
MC7   0         --                --                  DOWAIT       --             1     slow
MC8   100  PT   nWAIT      Lc---  --                  NOWAIT       --             4     slow
MC9   99   --   nWE        INPUT  XXL_376      C----  NA           --             5     slow
MC10  0         --                XXL_375      C----  NA           --             5     slow
MC11  98   --   nWR        INPUT  XXL_377      C----  NA           --             5     slow
MC12  0         --                XXL_381      C----  NA           --             5     slow
MC13  96   --   nRD        INPUT  XXL_379      C----  NA           --             5     slow
MC14  95   --   nIORQ      INPUT  XXL_382      C----  NA           --             5     slow
MC15  0         --                XXL_380      C----  NA           --             5     slow
MC16  94   --   nMREQ      INPUT  XXL_378      C----  NA           --             5     slow
MC17  16   --   A4         INPUT  PRIM2        Dc-g-  --           --             2     slow
MC18  0         --                PRIM0        Dc-g-  --           --             2     slow
MC19  15   --   A3         INPUT  PRIM1        Dc-g-  --           --             2     slow
MC20  0         --                SEC4         Dc-g-  --           --             2     slow
MC21  14   --   A2         INPUT  SEC5         Dc-g-  --           --             2     slow
MC22  12   --   A1         INPUT  SEC3         Dc-g-  --           --             2     slow
MC23  0         --                SEC1         Dc-g-  --           --             2     slow
MC24  11   --   A0         INPUT  SEC2         Dc-g-  --           --             2     slow
MC25  10   --   nRFSH      INPUT  SEC0         Dc-g-  --           --             2     slow
MC26  0         --                R40          Dc--p  --           --             3     slow
MC27  9    --   nM1        INPUT  R41          Dc--p  --           --             3     slow
MC28  0         --                R31          Dc--p  --           --             3     slow
MC29  8    on   Z80RESET   C----  --                  --           --             1     slow
MC30  7    --   nBUSRQ     INPUT  R20          Dc--p  Com_Ctrl_359 --             4     slow
MC31  0         --                XXL_363      C----  NA           --             5     slow
MC32  6    --   TDI        INPUT  XXL_364      C----  NA           --             5     slow
MC33  27   --   A13        INPUT  PRIM3        Dc-g-  --           --             2     slow
MC34  0         --                R46          Dc-g-  --           --             2     slow
MC35  26   --   A12        INPUT  R47          Dc-g-  --           --             2     slow
MC36  0         --                R37          Dc-g-  --           --             2     slow
MC37  25   --   A11        INPUT  R36          Dc-g-  --           --             2     slow
MC38  24   --   A10        INPUT  R26          Dc-g-  --           --             2     slow
MC39  0         --                R27          Dc-g-  --           --             2     slow
MC40  23   --   A9         INPUT  R17          Dc-g-  --           --             2     slow
MC41  22   --   A8         INPUT  R16          Dc-g-  --           --             2     slow
MC42  0         --                PRIM6        Dc-g-  --           --             2     slow
MC43  21   --   A7         INPUT  PRIM7        Dc-g-  --           --             2     slow
MC44  0         --                SEC7         Dc-g-  --           --             2     slow
MC45  19   --   A6         INPUT  SEC6         Dc-g-  Com_Ctrl_359 --             3     slow
MC46  18   --   A5         INPUT  XXL_367      C----  NA           --             5     slow
MC47  0         --                XXL_366      C----  NA           --             5     slow
MC48  17   --   TMS        INPUT  XXL_365      C----  NA           --             5     slow
MC49  39   PT   D7         Lc---  --                  --           --             4     slow
MC50  0         --                R15          Dc-g-  --           --             2     slow
MC51  38   PT   D6         Lc---  --                  --           --             4     slow
MC52  0         --                R13          Dc-g-  --           --             2     slow
MC53  37   PT   D5         Lc---  --                  --           --             4     slow
MC54  35   PT   D4         Lc---  --                  --           --             4     slow
MC55  0         --                R11          Dc-g-  --           --             2     slow
MC56  34   PT   D3         Lc---  --                  --           --             4     slow
MC57  33   PT   D2         Lc---  --                  --           --             4     slow
MC58  0         --                R10          Dc-g-  --           --             2     slow
MC59  32   PT   D1         Lc---  --                  --           --             4     slow
MC60  0         --                R12          Dc-g-  --           --             2     slow
MC61  31   PT   D0         Lc---  --                  --           --             4     slow
MC62  30   --   A15        INPUT  PRIM5        Dc-g-  --           --             2     slow
MC63  0         --                PRIM4        Dc-g-  --           --             2     slow
MC64  29   --   A14        INPUT  Com_Ctrl_360 C----  --           --             3     slow
MC65  42        --                --                  --           --             0     slow
MC66  0         --                --                  --           --             0     slow
MC67  43        --                --                  --           --             0     slow
MC68  0         --                XXL_369      C----  NA           --             5     slow
MC69  44        --                --                  --           --             0     slow
MC70  46   --   CLK        INPUT  XXL_368      C----  NA           --             5     slow
MC71  0         --                R44          Dc-g-  --           --             2     slow
MC72  47   --   nINT       INPUT  R24          Dc-g-  --           --             2     slow
MC73  48   --   nNMI       INPUT  R34          Dc-g-  --           --             2     slow
MC74  0         --                R14          Dc-g-  --           --             2     slow
MC75  49   on   Debug1     C----  --                  --           --             1     slow
MC76  0         --                --                  --           --             0     slow
MC77  50   on   Debug2     C----  --                  --           --             1     slow
MC78  51        --                --                  --           --             0     slow
MC79  0         --                XXL_370      C----  NA           --             5     slow
MC80  52   --   nBUSACK    INPUT  --                  --           --             0     slow
MC81  54   on   ATCLK      Dg---  --                  --           --             1     slow
MC82  0         --                --                  --           --             0     slow
MC83  55   --   INT        INPUT  --                  --           --             0     slow
MC84  0         --                XXL_373      C----  NA           --             5     slow
MC85  56   on   nCLK       C----  --                  --           --             1     slow
MC86  57   on   test1      C----  --                  --           --             1     slow
MC87  0         --                --                  --           --             0     slow
MC88  58        --                --                  --           --             0     slow
MC89  59        --                --                  --           --             0     slow
MC90  0         --                XXL_384      C----  NA           --             5     slow
MC91  60        --                XXL_371      C----  NA           --             5     slow
MC92  0         --                XXL_383      C----  NA           --             5     slow
MC93  62   on   nSLT2      C----  --                  --           --             4     slow
MC94  63   on   nSLT1      C----  --                  --           --             4     slow
MC95  0         --                XXL_374      C----  NA           --             5     slow
MC96  64   --   TCK        INPUT  XXL_372      C----  NA           --             5     slow
MC97  65        --                R45          Dc-g-  --           --             2     slow
MC98  0         --                R42          Dc-g-  --           --             2     slow
MC99  66   on   test2      C----  --                  --           --             1     slow
MC100 0         --                R33          Dc-g-  --           --             2     slow
MC101 67   --   nBUSRD     INPUT  R35          Dc-g-  --           --             2     slow
MC102 69   --   nResume    INPUT  R30          Dc-g-  --           --             2     slow
MC103 0         --                R23          Dc-g-  --           --             2     slow
MC104 70   on   SECADR_PIN C----  --                  --           --             1     slow
MC105 71        --                R43          Dc-g-  --           --             2     slow
MC106 0         --                R32          Dc-g-  --           --             2     slow
MC107 72   on   nCS_Serial C----  --                  --           --             1     slow
MC108 0         --                R25          Dc-g-  --           --             2     slow
MC109 73   on   nCS_HD     C----  --                  --           --             1     slow
MC110 74   on   SpareCS    C----  --                  --           --             1     slow
MC111 0         --                R22          Dc-g-  --           --             2     slow
MC112 75   --   TDO        INPUT  R21          Dc-g-  --           --             2     slow
MC113 77   on   nCS_RTC    C----  --                  --           --             1     slow
MC114 0         --                --                  --           --             0     slow
MC115 78   --   nBUScon    INPUT  --                  --           --             0     slow
MC116 0         --                --                  --           --             0     slow
MC117 79        --                --                  --           --             0     slow
MC118 80        --                --                  --           --             0     slow
MC119 0         --                --                  --           --             0     slow
MC120 81   on   RomA14     C----  --                  --           --             2     slow
MC121 82   on   RomA13     C----  --                  --           --             1     slow
MC122 0         --                --                  --           --             0     slow
MC123 83   on   RomA19     C----  --                  --           --             4     slow
MC124 0         --                --                  --           --             0     slow
MC125 85   on   RomA18     C----  --                  --           --             4     slow
MC126 86   on   nRomRD     C----  --                  --           --             1     slow
MC127 0         --                --                  --           --             0     slow
MC128 87   on   nRomWE     C----  --                  --           --             4     slow
MC0   92        CLKi       INPUT  --                  --           --             0     slow
MC0   91        nRESET     INPUT  --                  --           --             0     slow
MC0   90        nHALT      INPUT  --                  --           --             0     slow
MC0   89        XCLK       INPUT  --                  --           --             0     slow

Logic Array Block	Logic Cells	I/O Pins	Foldbacks	TotalPT		FanIN	Cascades
A: LC1	- LC16		13/16(81%)	10/16(62%)	4/16(25%)	62/80(77%)	(40)	0
B: LC17	- LC32		16/16(100%)	10/16(62%)	1/16(6%)	42/80(52%)	(37)	0
C: LC33	- LC48		16/16(100%)	10/16(62%)	1/16(6%)	42/80(52%)	(38)	0
D: LC49	- LC64		16/16(100%)	10/16(62%)	0/16(0%)	49/80(61%)	(35)	0
E: LC65	- LC80		9/16(56%)	6/16(37%)	0/16(0%)	25/80(31%)	(40)	0
F: LC81	- LC96		11/16(68%)	7/16(43%)	0/16(0%)	41/80(51%)	(40)	0
G: LC97	- LC112		16/16(100%)	8/16(50%)	0/16(0%)	27/80(33%)	(26)	0
H: LC113- LC128		7/16(43%)	8/16(50%)	0/16(0%)	17/80(21%)	(38)	0

Total dedicated input used:	4/4 	(100%)
Total I/O pins used		69/80 	(86%)
Total Logic cells used 		104/128 	(81%)
Total Flip-Flop used 		58/128 	(45%)
Total Foldback logic used 	6/128 	(4%)
Total Nodes+FB/MCells 		110/128 	(85%)
Total cascade used 		0
Total input pins 		40
Total output pins 		33
Total Pts 			305
Creating pla file C:\USERS\BERT_\DOCUMENTS\01_CCZ80_COMP\CCZ80_MPU\CPLD\MAIN\MAIN.tt3 with 0 inputs 0 outputs, 0 pins 0 nodes and 0 pterms...

----------------  End fitter, Design FITS
$Device PQFP100 fits 
FIT1508 completed in 0.00 seconds
