Atmel ATF1508AS Fitter Version 1.8.7.8 ,running Fri May 07 13:49:09 2021


fit1508 C:\USERS\BERT_\DOCUMENTS\01_CCZ80_COMP\CCZ80_MPU\CPLD\MEMMAP.tt2 -CUPL -dev P1508Q100 -JTAG ON


****** Initial fitting strategy and property ******
 Pla_in_file = MEMMAP.tt2
 Pla_out_file = MEMMAP.tt3
 Jedec_file = MEMMAP.jed
 Vector_file = MEMMAP.tmv
 verilog_file = MEMMAP.vt
 Time_file = 
 Log_file = MEMMAP.fit
 err_file = 
 Device_name = PQFP100
 Module_name = 
 Package_type = PQFP
 Preassign_file = 
 Property_file = 
 Sleep_mode = 
 Preassignment = 
 Security_mode = OFF
 Pin_keep_mode = ON
 Dedicated_input_clock = 
 Dedicated_input_reset = 
 Dedicated_input_oe = 
 supporter = CUPL
 optimize = ON
 Soft_buffer = 
 Xor_synthesis = OFF
 Foldback_logic =  on
 Expander = 
 Cascade_logic = OFF
 Dedicated_input = 
 Output_fast = OFF
 *******************************
 Power down pin 1 = OFF
 Power down pin 2 = OFF
 power_reset = OFF
 JTAG = ON
 TDI pullup = OFF
 TMS pullup = OFF
 MC_power = OFF
 Open_collector = OFF
 ITD0 = ON
 ITD1 = ON
 ITD2 = ON
 Fast_inlatch = off
 *******************************
---------------------------------------------------------
 Fitter_Pass 1, Preassign = KEEP, LOGIC_DOUBLING : OFF 
 ... 
## ERROR : Bad user pin assignement : 102
 ## ERROR : Bad user pin assignement 
---------------------------------------------------------
 Fitter_Pass 2, Preassign = KEEP, NODE ASSIGN : OFF 
 ... 
Unable to Keep Fanin of 42 on Block D
 ## Warning : Grouping fail 
---------------------------------------------------------
 Fitter_Pass 3, Preassign = KEEP, CASCADE_LOGIC : (TRY) 
 ... 

Performing global Output Enable pin assignments ...

Performing global pin assignments ...
--------------------------------------



Final global control pins assignment (if applicable)...
-------------------------------------------------------
XCLK assigned to pin  89
nRESET assigned to pin  91



Performing input pin pre-assignments ...
------------------------------------
XCLK assigned to pin  89
nRESET assigned to pin  91

Attempt to place floating signals ...
------------------------------------
RomA15 is placed at pin 4 (MC 1)
RomA16 is placed at pin 3 (MC 3)
RomA17 is placed at pin 2 (MC 5)
nRomCS is placed at pin 1 (MC 6)
nWAIT is placed at pin 100 (MC 8)
nWR is placed at pin 98 (MC 11)
nRD is placed at pin 96 (MC 13)
FB_263 is placed at foldback expander node 313 (MC 13)
nIORQ is placed at pin 95 (MC 14)
FB_262 is placed at foldback expander node 314 (MC 14)
DOWAIT is placed at foldback expander node 315 (MC 15)
nMREQ is placed at pin 94 (MC 16)
NOWAIT is placed at foldback expander node 316 (MC 16)
A4 is placed at pin 16 (MC 17)
R21 is placed at feedback node 617 (MC 17)
R14 is placed at feedback node 618 (MC 18)
A3 is placed at pin 15 (MC 19)
R13 is placed at feedback node 619 (MC 19)
R12 is placed at feedback node 620 (MC 20)
A2 is placed at pin 14 (MC 21)
R11 is placed at feedback node 621 (MC 21)
A1 is placed at pin 12 (MC 22)
R10 is placed at feedback node 622 (MC 22)
R41 is placed at feedback node 623 (MC 23)
A0 is placed at pin 11 (MC 24)
R40 is placed at feedback node 624 (MC 24)
R24 is placed at feedback node 625 (MC 25)
R31 is placed at feedback node 626 (MC 26)
R22 is placed at feedback node 627 (MC 27)
R20 is placed at feedback node 628 (MC 28)
Z80RESET is placed at pin 8 (MC 29)
R23 is placed at feedback node 630 (MC 30)
XXL_265 is placed at feedback node 631 (MC 31)
TDI is placed at pin 6 (MC 32)
XXL_266 is placed at feedback node 632 (MC 32)
A13 is placed at pin 27 (MC 33)
A12 is placed at pin 26 (MC 35)
A11 is placed at pin 25 (MC 37)
A10 is placed at pin 24 (MC 38)
R47 is placed at feedback node 638 (MC 38)
R45 is placed at feedback node 639 (MC 39)
A9 is placed at pin 23 (MC 40)
R37 is placed at feedback node 640 (MC 40)
A8 is placed at pin 22 (MC 41)
R27 is placed at feedback node 641 (MC 41)
R35 is placed at feedback node 642 (MC 42)
A7 is placed at pin 21 (MC 43)
R25 is placed at feedback node 643 (MC 43)
R15 is placed at feedback node 644 (MC 44)
A6 is placed at pin 19 (MC 45)
R17 is placed at feedback node 645 (MC 45)
A5 is placed at pin 18 (MC 46)
XXL_268 is placed at feedback node 646 (MC 46)
XXL_267 is placed at feedback node 647 (MC 47)
TMS is placed at pin 17 (MC 48)
XXL_264 is placed at feedback node 648 (MC 48)
D7 is placed at pin 39 (MC 49)
D6 is placed at pin 38 (MC 51)
D5 is placed at pin 37 (MC 53)
D4 is placed at pin 35 (MC 54)
R46 is placed at feedback node 655 (MC 55)
D3 is placed at pin 34 (MC 56)
D2 is placed at pin 33 (MC 57)
R30 is placed at feedback node 658 (MC 58)
D1 is placed at pin 32 (MC 59)
R36 is placed at feedback node 660 (MC 60)
D0 is placed at pin 31 (MC 61)
A15 is placed at pin 30 (MC 62)
R26 is placed at feedback node 662 (MC 62)
R16 is placed at feedback node 663 (MC 63)
A14 is placed at pin 29 (MC 64)
XXL_271 is placed at feedback node 664 (MC 64)
CLK is placed at pin 46 (MC 70)
R43 is placed at feedback node 671 (MC 71)
nINT is placed at pin 47 (MC 72)
R33 is placed at feedback node 672 (MC 72)
nNMI is placed at pin 48 (MC 73)
R42 is placed at feedback node 673 (MC 73)
R32 is placed at feedback node 674 (MC 74)
Debug1 is placed at pin 49 (MC 75)
XXL_269 is placed at feedback node 676 (MC 76)
Debug2 is placed at pin 50 (MC 77)
XXL_270 is placed at feedback node 679 (MC 79)
ATCLK is placed at pin 54 (MC 81)
nCLK is placed at pin 56 (MC 85)
R44 is placed at feedback node 695 (MC 95)
TCK is placed at pin 64 (MC 96)
R34 is placed at feedback node 696 (MC 96)
nResume is placed at pin 69 (MC 102)
nCS_Serial is placed at pin 72 (MC 107)
nCS_HD is placed at pin 73 (MC 109)
SpareCS is placed at pin 74 (MC 110)
TDO is placed at pin 75 (MC 112)
nCS_RTC is placed at pin 77 (MC 113)
nBUScon is placed at pin 78 (MC 115)
RomA14 is placed at pin 81 (MC 120)
RomA13 is placed at pin 82 (MC 121)
RomA19 is placed at pin 83 (MC 123)
RomA18 is placed at pin 85 (MC 125)
nRomRD is placed at pin 86 (MC 126)
nRomWE is placed at pin 87 (MC 128)

                                                                                    
                                                                                    
                                                                                    
                                                                                    
                                           n       n n R   R R R                    
                         n         n n     R       R R o   o o o                    
                         W         I M     E   X   o o m   m m m                    
                         A   n G n O R V   S   C G m m A V A A A                    
                         I   W N R R E C   E   L N W R 1 C 1 1 1                    
                         T   R D D Q Q C   T   K D E D 8 C 9 3 4                    
                       --------------------------------------------                 
                      / 100  98  96  94  92  90  88  86  84  82    \               
                     /     99  97  95  93  91  89  87  85  83  81   \              
             nRomCS |  1 (*)                                      80 |              
             RomA17 |  2                                          79 |              
             RomA16 |  3                                          78 | nBUScon      
             RomA15 |  4                                          77 | nCS_RTC      
                VCC |  5                                          76 | GND          
                TDI |  6                                          75 | TDO          
                    |  7                                          74 | SpareCS      
           Z80RESET |  8                                          73 | nCS_HD       
                    |  9                                          72 | nCS_Serial   
                    | 10                                          71 |              
                 A0 | 11                                          70 |              
                 A1 | 12                                          69 | nResume      
                GND | 13                                          68 | VCC          
                 A2 | 14                                          67 |              
                 A3 | 15                                          66 |              
                 A4 | 16                ATF1508                   65 |              
                TMS | 17             100-Lead PQFP                64 | TCK          
                 A5 | 18                                          63 |              
                 A6 | 19                                          62 |              
                VCC | 20                                          61 | GND          
                 A7 | 21                                          60 |              
                 A8 | 22                                          59 |              
                 A9 | 23                                          58 |              
                A10 | 24                                          57 |              
                A11 | 25                                          56 | nCLK         
                A12 | 26                                          55 |              
                A13 | 27                                          54 | ATCLK        
                GND | 28                                          53 | VCC          
                A14 | 29                                          52 |              
                A15 | 30                                          51 |              
                     \     32  34  36  38  40  42  44  46  48  50   /              
                      \  31  33  35  37  39  41  43  45  47  49    /               
                       --------------------------------------------                 
                         D D D D D V D D D G V       G C n n D D                    
                         0 1 2 3 4 C 5 6 7 N C       N L I N e e                    
                                   C       D C       D K N M b b                    
                                                         T I u u                    
                                                             g g                    
                                                             1	2                    



VCC = Supply Voltage pin which must be connected to (5.0V or 3.0V)

GND = GND pin which must be connected to ground

TMS,TDI,TDO,TDI = JTAG pins which must reserved for the JTAG interface

NC = Unused I/O pins which must be unconnected on the board

Universal-Interconnect-Multiplexer assignments
------------------------------------------------
FanIn assignment for block A [20]
{
A15,A14,
R43,R23,R32,R13,R42,R12,R33,R22,R21,R31,R41,R11,
nRESET,nResume,nMREQ,nCS_Serial,nCS_RTC,nCS_HD,
}
Multiplexer assignment for block A
R43			(MC9	FB)  : MUX 0		Ref (E71fb)
nRESET			(MC19	FB)  : MUX 2		Ref (GCLR)
nResume			(MC20	P)   : MUX 3		Ref (G102p)
nMREQ			(MC18	P)   : MUX 4		Ref (A16p)
nCS_Serial		(MC13	P)   : MUX 6		Ref (G107p)
A15			(MC17	P)   : MUX 10		Ref (D62p)
nCS_RTC			(MC15	P)   : MUX 11		Ref (H113p)
A14			(MC16	P)   : MUX 12		Ref (D64p)
R23			(MC8	FB)  : MUX 13		Ref (B30fb)
R32			(MC12	FB)  : MUX 15		Ref (E74fb)
R13			(MC2	FB)  : MUX 16		Ref (B19fb)
R42			(MC11	FB)  : MUX 19		Ref (E73fb)
R12			(MC3	FB)  : MUX 20		Ref (B20fb)
R33			(MC10	FB)  : MUX 22		Ref (E72fb)
R22			(MC7	FB)  : MUX 23		Ref (B27fb)
nCS_HD			(MC14	P)   : MUX 24		Ref (G109p)
R21			(MC1	FB)  : MUX 26		Ref (B17fb)
R31			(MC6	FB)  : MUX 29		Ref (B26fb)
R41			(MC5	FB)  : MUX 32		Ref (B23fb)
R11			(MC4	FB)  : MUX 36		Ref (B21fb)

FanIn assignment for block B [25]
{
A0,A6,A7,A3,A5,A4,A2,A1,
D3,D1,D0,D2,D4,
R12,R22,R42,R31,R11,R21,R41,R32,
nRD,nIORQ,nWR,nRESET,
}
Multiplexer assignment for block B
D3			(MC8	P)   : MUX 1		Ref (D56p)
R12			(MC2	FB)  : MUX 2		Ref (B20fb)
A0			(MC23	P)   : MUX 3		Ref (B24p)
A6			(MC17	P)   : MUX 4		Ref (C45p)
R22			(MC6	FB)  : MUX 5		Ref (B27fb)
A7			(MC18	P)   : MUX 10		Ref (C43p)
A3			(MC14	P)   : MUX 11		Ref (B19p)
A5			(MC16	P)   : MUX 12		Ref (C46p)
A4			(MC15	P)   : MUX 15		Ref (B17p)
D1			(MC10	P)   : MUX 16		Ref (D59p)
A2			(MC21	P)   : MUX 17		Ref (B21p)
R42			(MC12	FB)  : MUX 19		Ref (E73fb)
nRD			(MC24	P)   : MUX 20		Ref (A13p)
R31			(MC5	FB)  : MUX 21		Ref (B26fb)
nIORQ			(MC19	P)   : MUX 22		Ref (A14p)
nWR			(MC22	P)   : MUX 24		Ref (A11p)
D0			(MC11	P)   : MUX 26		Ref (D61p)
D2			(MC9	P)   : MUX 28		Ref (D57p)
A1			(MC20	P)   : MUX 29		Ref (B22p)
R11			(MC3	FB)  : MUX 30		Ref (B21fb)
R21			(MC1	FB)  : MUX 32		Ref (B17fb)
D4			(MC7	P)   : MUX 33		Ref (D54p)
nRESET			(MC25	FB)  : MUX 36		Ref (GCLR)
R41			(MC4	FB)  : MUX 38		Ref (B23fb)
R32			(MC13	FB)  : MUX 39		Ref (E74fb)

FanIn assignment for block C [25]
{
A7,A6,A1,A0,A4,A2,A5,A3,
D7,D5,
R30,R40,R20,R14,R13,R23,R10,R24,R33,R44,R43,R34,
nWR,nRD,nIORQ,
}
Multiplexer assignment for block C
A7			(MC19	P)   : MUX 0		Ref (C43p)
R30			(MC10	FB)  : MUX 1		Ref (D58fb)
R40			(MC4	FB)  : MUX 2		Ref (B24fb)
A6			(MC18	P)   : MUX 4		Ref (C45p)
D7			(MC8	P)   : MUX 5		Ref (D49p)
nWR			(MC23	P)   : MUX 6		Ref (A11p)
A1			(MC21	P)   : MUX 7		Ref (B22p)
A0			(MC24	P)   : MUX 9		Ref (B24p)
R20			(MC6	FB)  : MUX 13		Ref (B28fb)
R14			(MC1	FB)  : MUX 14		Ref (B18fb)
A4			(MC16	P)   : MUX 15		Ref (B17p)
R13			(MC2	FB)  : MUX 16		Ref (B19fb)
A2			(MC22	P)   : MUX 17		Ref (B21p)
R23			(MC7	FB)  : MUX 19		Ref (B30fb)
nRD			(MC25	P)   : MUX 20		Ref (A13p)
nIORQ			(MC20	P)   : MUX 22		Ref (A14p)
D5			(MC9	P)   : MUX 25		Ref (D53p)
A5			(MC17	P)   : MUX 26		Ref (C46p)
A3			(MC15	P)   : MUX 27		Ref (B19p)
R10			(MC3	FB)  : MUX 34		Ref (B22fb)
R24			(MC5	FB)  : MUX 35		Ref (B25fb)
R33			(MC12	FB)  : MUX 36		Ref (E72fb)
R44			(MC13	FB)  : MUX 37		Ref (F95fb)
R43			(MC11	FB)  : MUX 38		Ref (E71fb)
R34			(MC14	FB)  : MUX 39		Ref (F96fb)

FanIn assignment for block D [25]
{
A5,A0,A6,A3,A2,A1,A7,A4,
D6,D0,
R27,R47,R17,R37,
XXL_270,XXL_266,XXL_264,XXL_271,XXL_265,XXL_267,XXL_269,XXL_268,
nRD,nIORQ,nWR,
}
Multiplexer assignment for block D
A5			(MC17	P)   : MUX 0		Ref (C46p)
R27			(MC5	FB)  : MUX 1		Ref (C41fb)
R47			(MC3	FB)  : MUX 2		Ref (C38fb)
A0			(MC24	P)   : MUX 3		Ref (B24p)
A6			(MC18	P)   : MUX 4		Ref (C45p)
XXL_270			(MC14	FB)  : MUX 5		Ref (E79fb)
nRD			(MC25	P)   : MUX 6		Ref (A13p)
XXL_266			(MC2	FB)  : MUX 7		Ref (B32fb)
D6			(MC10	P)   : MUX 9		Ref (D51p)
A3			(MC15	P)   : MUX 11		Ref (B19p)
nIORQ			(MC20	P)   : MUX 12		Ref (A14p)
A2			(MC22	P)   : MUX 17		Ref (B21p)
R17			(MC6	FB)  : MUX 19		Ref (C45fb)
XXL_264			(MC9	FB)  : MUX 21		Ref (C48fb)
XXL_271			(MC12	FB)  : MUX 23		Ref (D64fb)
nWR			(MC23	P)   : MUX 24		Ref (A11p)
XXL_265			(MC1	FB)  : MUX 25		Ref (B31fb)
D0			(MC11	P)   : MUX 26		Ref (D61p)
A1			(MC21	P)   : MUX 27		Ref (B22p)
A7			(MC19	P)   : MUX 28		Ref (C43p)
XXL_267			(MC8	FB)  : MUX 29		Ref (C47fb)
A4			(MC16	P)   : MUX 31		Ref (B17p)
XXL_269			(MC13	FB)  : MUX 35		Ref (E76fb)
R37			(MC4	FB)  : MUX 38		Ref (C40fb)
XXL_268			(MC7	FB)  : MUX 39		Ref (C46fb)

FanIn assignment for block E [25]
{
A0,A3,A7,A2,A5,A6,A1,A4,
CLK,
D3,D2,
R16,R26,R35,R36,R46,R25,R45,R15,
nINT,nRD,nIORQ,nBUScon,nNMI,nWR,
}
Multiplexer assignment for block E
D3			(MC6	P)   : MUX 1		Ref (D56p)
A0			(MC20	P)   : MUX 3		Ref (B24p)
D2			(MC7	P)   : MUX 4		Ref (D57p)
nINT			(MC23	P)   : MUX 5		Ref (E72p)
nRD			(MC21	P)   : MUX 6		Ref (A13p)
nIORQ			(MC16	P)   : MUX 8		Ref (A14p)
A3			(MC11	P)   : MUX 9		Ref (B19p)
A7			(MC15	P)   : MUX 10		Ref (C43p)
A2			(MC18	P)   : MUX 11		Ref (B21p)
A5			(MC13	P)   : MUX 12		Ref (C46p)
nBUScon			(MC25	P)   : MUX 13		Ref (H115p)
nNMI			(MC24	P)   : MUX 14		Ref (E73p)
R16			(MC10	FB)  : MUX 15		Ref (D63fb)
CLK			(MC22	P)   : MUX 17		Ref (E70p)
A6			(MC14	P)   : MUX 18		Ref (C45p)
R26			(MC9	FB)  : MUX 21		Ref (D62fb)
R35			(MC2	FB)  : MUX 23		Ref (C42fb)
nWR			(MC19	P)   : MUX 24		Ref (A11p)
R36			(MC8	FB)  : MUX 25		Ref (D60fb)
A1			(MC17	P)   : MUX 27		Ref (B22p)
R46			(MC5	FB)  : MUX 32		Ref (D55fb)
A4			(MC12	P)   : MUX 33		Ref (B17p)
R25			(MC3	FB)  : MUX 35		Ref (C43fb)
R45			(MC1	FB)  : MUX 36		Ref (C39fb)
R15			(MC4	FB)  : MUX 39		Ref (C44fb)

FanIn assignment for block F [13]
{
A7,ATCLK,A6,A0,A2,A1,A4,A5,A3,
D4,
XCLK,
nWR,nIORQ,
}
Multiplexer assignment for block F
A7			(MC7	P)   : MUX 0		Ref (C43p)
ATCLK			(MC2	P)   : MUX 3		Ref (F81p)
A6			(MC6	P)   : MUX 4		Ref (C45p)
D4			(MC1	P)   : MUX 7		Ref (D54p)
A0			(MC12	P)   : MUX 9		Ref (B24p)
nWR			(MC11	P)   : MUX 10		Ref (A11p)
A2			(MC10	P)   : MUX 11		Ref (B21p)
nIORQ			(MC8	P)   : MUX 12		Ref (A14p)
A1			(MC9	P)   : MUX 13		Ref (B22p)
A4			(MC4	P)   : MUX 15		Ref (B17p)
XCLK			(MC13	FB)  : MUX 17		Ref (GCLK)
A5			(MC5	P)   : MUX 20		Ref (C46p)
A3			(MC3	P)   : MUX 29		Ref (B19p)

FanIn assignment for block G [12]
{
A5,A11,A6,A13,A10,A12,A9,A4,A7,A8,A3,
nIORQ,
}
Multiplexer assignment for block G
A5			(MC3	P)   : MUX 0		Ref (C46p)
A11			(MC11	P)   : MUX 1		Ref (C37p)
A6			(MC4	P)   : MUX 4		Ref (C45p)
A13			(MC7	P)   : MUX 5		Ref (C33p)
A10			(MC10	P)   : MUX 7		Ref (C38p)
A12			(MC12	P)   : MUX 9		Ref (C35p)
A9			(MC9	P)   : MUX 11		Ref (C40p)
nIORQ			(MC6	P)   : MUX 12		Ref (A14p)
A4			(MC2	P)   : MUX 13		Ref (B17p)
A7			(MC5	P)   : MUX 18		Ref (C43p)
A8			(MC8	P)   : MUX 20		Ref (C41p)
A3			(MC1	P)   : MUX 27		Ref (B19p)

FanIn assignment for block H [26]
{
A7,A1,A3,A4,A6,A2,A13,A5,A15,A14,
R30,R40,R44,R14,R10,R15,R35,R24,R25,R45,R20,R34,
nMREQ,nIORQ,nRD,nWR,
}
Multiplexer assignment for block H
A7			(MC17	P)   : MUX 0		Ref (C43p)
R30			(MC10	FB)  : MUX 1		Ref (D58fb)
R40			(MC3	FB)  : MUX 2		Ref (B24fb)
nMREQ			(MC25	P)   : MUX 4		Ref (A16p)
R44			(MC11	FB)  : MUX 5		Ref (F95fb)
R14			(MC1	FB)  : MUX 6		Ref (B18fb)
A1			(MC19	P)   : MUX 7		Ref (B22p)
nIORQ			(MC18	P)   : MUX 8		Ref (A14p)
A3			(MC13	P)   : MUX 9		Ref (B19p)
A4			(MC14	P)   : MUX 13		Ref (B17p)
A6			(MC16	P)   : MUX 14		Ref (C45p)
R10			(MC2	FB)  : MUX 16		Ref (B22fb)
A2			(MC20	P)   : MUX 17		Ref (B21p)
R15			(MC9	FB)  : MUX 19		Ref (C44fb)
nRD			(MC22	P)   : MUX 20		Ref (A13p)
A13			(MC26	P)   : MUX 21		Ref (C33p)
R35			(MC7	FB)  : MUX 23		Ref (C42fb)
nWR			(MC21	P)   : MUX 24		Ref (A11p)
R24			(MC4	FB)  : MUX 25		Ref (B25fb)
A5			(MC15	P)   : MUX 26		Ref (C46p)
A15			(MC24	P)   : MUX 28		Ref (D62p)
A14			(MC23	P)   : MUX 30		Ref (D64p)
R25			(MC8	FB)  : MUX 35		Ref (C43fb)
R45			(MC6	FB)  : MUX 36		Ref (C39fb)
R20			(MC5	FB)  : MUX 37		Ref (B28fb)
R34			(MC12	FB)  : MUX 39		Ref (F96fb)

Creating JEDEC file C:\USERS\BERT_\DOCUMENTS\01_CCZ80_COMP\CCZ80_MPU\CPLD\MEMMAP.jed ...

PQFP100 programmed logic:
-----------------------------------
ATCLK.D = !ATCLK.Q;

D0.L = XXL_264;

D1.L = XXL_265;

D2.L = XXL_266;

D3.L = XXL_267;

D4.L = XXL_268;

D5.L = XXL_269;

D6.L = XXL_270;

Debug2 = nBUScon;

D7.L = XXL_271;

!Debug1 = (!CLK & !nINT & !nNMI);

R10.D = D0.PIN;

R11.D = D1.PIN;

R12.D = D2.PIN;

R13.D = D3.PIN;

R14.D = D4.PIN;

R15.D = D5.PIN;

R16.D = D6.PIN;

R17.D = D7.PIN;

R20.D = D0.PIN;

R21.D = D1.PIN;

R22.D = D2.PIN;

R23.D = D3.PIN;

R24.D = D4.PIN;

R25.D = D5.PIN;

R26.D = D6.PIN;

R27.D = D7.PIN;

R30.D = D0.PIN;

R31.D = D1.PIN;

R32.D = D2.PIN;

R33.D = D3.PIN;

R34.D = D4.PIN;

R35.D = D5.PIN;

R36.D = D6.PIN;

R37.D = D7.PIN;

R40.D = D0.PIN;

R41.D = D1.PIN;

R42.D = D2.PIN;

R43.D = D3.PIN;

R44.D = D4.PIN;

R45.D = D5.PIN;

R46.D = D6.PIN;

R47.D = D7.PIN;

RomA15 = ((A14 & !A15 & !nMREQ & R21.Q)
	# (A14 & A15 & !nMREQ & R41.Q)
	# (!A14 & !A15 & !nMREQ & R11.Q)
	# (!A14 & A15 & !nMREQ & R31.Q));

RomA13 = A13;

RomA16 = ((A14 & !A15 & !nMREQ & R22.Q)
	# (A14 & A15 & !nMREQ & R42.Q)
	# (!A14 & !A15 & !nMREQ & R12.Q)
	# (!A14 & A15 & !nMREQ & R32.Q));

RomA14 = ((A14 & !A15 & !nMREQ & R20.Q)
	# (A14 & A15 & !nMREQ & R40.Q)
	# (!A14 & !A15 & !nMREQ & R10.Q)
	# (!A14 & A15 & !nMREQ & R30.Q));

RomA18 = ((A14 & !A15 & !nMREQ & R24.Q)
	# (A14 & A15 & !nMREQ & R44.Q)
	# (!A14 & !A15 & !nMREQ & R14.Q)
	# (!A14 & A15 & !nMREQ & R34.Q));

RomA17 = ((A14 & !A15 & !nMREQ & R23.Q)
	# (A14 & A15 & !nMREQ & R43.Q)
	# (!A14 & !A15 & !nMREQ & R13.Q)
	# (!A14 & A15 & !nMREQ & R33.Q));

Z80RESET = nRESET;

!nCS_RTC = (!A1 & A2 & !A3 & A4 & A5 & !A6 & A7 & !nIORQ);

RomA19 = ((A14 & !A15 & !nMREQ & R25.Q)
	# (A14 & A15 & !nMREQ & R45.Q)
	# (!A14 & !A15 & !nMREQ & R15.Q)
	# (!A14 & A15 & !nMREQ & R35.Q));

!SpareCS = (A8 & A9 & A10 & A11 & A12 & A13);

nCLK = XCLK;

!nCS_HD = (!A3 & A4 & !A5 & A6 & A7 & !nIORQ);

nWAIT.L = DOWAIT;

!nCS_Serial = (!A3 & !A4 & !A5 & !A6 & A7 & !nIORQ);

nRomCS = nMREQ;

!nRomRD = (!nMREQ & !nRD);

!nRomWE = (!nMREQ & !nWR);

!NOWAIT = (nCS_HD & nCS_RTC & nCS_Serial & DOWAIT);

!DOWAIT = (nRESET & nResume & NOWAIT);

!FB_262 = (nCS_HD & nCS_RTC & nCS_Serial);

!FB_263 = (nCS_HD & nCS_RTC & nCS_Serial);

XXL_264 = ((A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R20.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R40.Q)
	# (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R10.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R30.Q));

XXL_265 = ((A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R21.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R41.Q)
	# (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R11.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R31.Q));

XXL_266 = ((A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R22.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R42.Q)
	# (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R12.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R32.Q));

XXL_267 = ((A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R23.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R43.Q)
	# (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R13.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R33.Q));

XXL_268 = ((A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R24.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R44.Q)
	# (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R14.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R34.Q));

XXL_269 = ((A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R25.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R45.Q)
	# (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R15.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R35.Q));

XXL_270 = ((A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R26.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R46.Q)
	# (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R16.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R36.Q));

XXL_271 = ((A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R27.Q)
	# (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R47.Q)
	# (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R17.Q)
	# (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD & R37.Q));

ATCLK.C = XCLK;

D0.LE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D0.OE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D1.LE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D1.OE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D2.LE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D2.OE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D3.LE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D3.OE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D4.LE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D4.OE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D5.LE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D5.OE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D6.LE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D6.OE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D7.LE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

D7.OE = (A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nRD);

R10.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R10.AR = !nRESET;

R11.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R11.AR = !nRESET;

R12.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R12.AR = !nRESET;

R13.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R13.AR = !nRESET;

R14.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R14.AR = !nRESET;

R15.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R15.AR = !nRESET;

R16.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R16.AR = !nRESET;

R17.C = (!A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R17.AR = !nRESET;

R20.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R20.AP = !nRESET;

R21.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R21.AR = !nRESET;

R22.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R22.AR = !nRESET;

R23.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R23.AR = !nRESET;

R24.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R24.AR = !nRESET;

R25.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R25.AR = !nRESET;

R26.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R26.AR = !nRESET;

R27.C = (A0 & !A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R27.AR = !nRESET;

R30.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R30.AR = !nRESET;

R31.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R31.AP = !nRESET;

R32.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R32.AR = !nRESET;

R33.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R33.AR = !nRESET;

R34.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R34.AR = !nRESET;

R35.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R35.AR = !nRESET;

R36.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R36.AR = !nRESET;

R37.C = (!A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R37.AR = !nRESET;

R40.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R40.AP = !nRESET;

R41.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R41.AP = !nRESET;

R42.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R42.AR = !nRESET;

R43.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R43.AR = !nRESET;

R44.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R44.AR = !nRESET;

R45.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R45.AR = !nRESET;

R46.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R46.AR = !nRESET;

R47.C = (A0 & A1 & A2 & A3 & A4 & A5 & A6 & A7 & !nIORQ & !nWR);

R47.AR = !nRESET;

nWAIT.LE = FB_262;

nWAIT.OE = FB_263;


PQFP100 Pin/Node Placement:
------------------------------------
Pin 1  = nRomCS; /* MC 6 */
Pin 2  = RomA17; /* MC 5 */
Pin 3  = RomA16; /* MC 3 */
Pin 4  = RomA15; /* MC 1 */
Pin 6  = TDI; /* MC 32 */
Pin 8  = Z80RESET; /* MC 29 */
Pin 11 = A0; /* MC 24 */ 
Pin 12 = A1; /* MC 22 */ 
Pin 14 = A2; /* MC 21 */ 
Pin 15 = A3; /* MC 19 */ 
Pin 16 = A4; /* MC 17 */ 
Pin 17 = TMS; /* MC 48 */ 
Pin 18 = A5; /* MC 46 */ 
Pin 19 = A6; /* MC 45 */ 
Pin 21 = A7; /* MC 43 */ 
Pin 22 = A8; /* MC 41 */ 
Pin 23 = A9; /* MC 40 */ 
Pin 24 = A10; /* MC 38 */ 
Pin 25 = A11; /* MC 37 */ 
Pin 26 = A12; /* MC 35 */ 
Pin 27 = A13; /* MC 33 */ 
Pin 29 = A14; /* MC 64 */ 
Pin 30 = A15; /* MC 62 */ 
Pin 31 = D0; /* MC 61 */ 
Pin 32 = D1; /* MC 59 */ 
Pin 33 = D2; /* MC 57 */ 
Pin 34 = D3; /* MC 56 */ 
Pin 35 = D4; /* MC 54 */ 
Pin 37 = D5; /* MC 53 */ 
Pin 38 = D6; /* MC 51 */ 
Pin 39 = D7; /* MC 49 */ 
Pin 46 = CLK; /* MC 70 */ 
Pin 47 = nINT; /* MC 72 */ 
Pin 48 = nNMI; /* MC 73 */ 
Pin 49 = Debug1; /* MC 75 */ 
Pin 50 = Debug2; /* MC 77 */ 
Pin 54 = ATCLK; /* MC 81 */ 
Pin 56 = nCLK; /* MC 85 */ 
Pin 64 = TCK; /* MC 96 */ 
Pin 69 = nResume; /* MC 102 */ 
Pin 72 = nCS_Serial; /* MC 107 */ 
Pin 73 = nCS_HD; /* MC 109 */ 
Pin 74 = SpareCS; /* MC 110 */ 
Pin 75 = TDO; /* MC 112 */ 
Pin 77 = nCS_RTC; /* MC 113 */ 
Pin 78 = nBUScon; /* MC 115 */ 
Pin 81 = RomA14; /* MC 120 */ 
Pin 82 = RomA13; /* MC 121 */ 
Pin 83 = RomA19; /* MC 123 */ 
Pin 85 = RomA18; /* MC 125 */ 
Pin 86 = nRomRD; /* MC 126 */ 
Pin 87 = nRomWE; /* MC 128 */ 
Pin 89 = XCLK;
Pin 91 = nRESET;
Pin 94 = nMREQ; /* MC 16 */ 
Pin 95 = nIORQ; /* MC 14 */ 
Pin 96 = nRD; /* MC 13 */ 
Pin 98 = nWR; /* MC 11 */ 
Pin 100 = nWAIT; /* MC  8 */
PINNODE 313 = FB_263; /* MC 13 Foldback */
PINNODE 314 = FB_262; /* MC 14 Foldback */
PINNODE 315 = DOWAIT; /* MC 15 Foldback */
PINNODE 316 = NOWAIT; /* MC 16 Foldback */
PINNODE 617 = R21; /* MC 17 Feedback */
PINNODE 618 = R14; /* MC 18 Feedback */
PINNODE 619 = R13; /* MC 19 Feedback */
PINNODE 620 = R12; /* MC 20 Feedback */
PINNODE 621 = R11; /* MC 21 Feedback */
PINNODE 622 = R10; /* MC 22 Feedback */
PINNODE 623 = R41; /* MC 23 Feedback */
PINNODE 624 = R40; /* MC 24 Feedback */
PINNODE 625 = R24; /* MC 25 Feedback */
PINNODE 626 = R31; /* MC 26 Feedback */
PINNODE 627 = R22; /* MC 27 Feedback */
PINNODE 628 = R20; /* MC 28 Feedback */
PINNODE 630 = R23; /* MC 30 Feedback */
PINNODE 631 = XXL_265; /* MC 31 Feedback */
PINNODE 632 = XXL_266; /* MC 32 Feedback */
PINNODE 638 = R47; /* MC 38 Feedback */
PINNODE 639 = R45; /* MC 39 Feedback */
PINNODE 640 = R37; /* MC 40 Feedback */
PINNODE 641 = R27; /* MC 41 Feedback */
PINNODE 642 = R35; /* MC 42 Feedback */
PINNODE 643 = R25; /* MC 43 Feedback */
PINNODE 644 = R15; /* MC 44 Feedback */
PINNODE 645 = R17; /* MC 45 Feedback */
PINNODE 646 = XXL_268; /* MC 46 Feedback */
PINNODE 647 = XXL_267; /* MC 47 Feedback */
PINNODE 648 = XXL_264; /* MC 48 Feedback */
PINNODE 655 = R46; /* MC 55 Feedback */
PINNODE 658 = R30; /* MC 58 Feedback */
PINNODE 660 = R36; /* MC 60 Feedback */
PINNODE 662 = R26; /* MC 62 Feedback */
PINNODE 663 = R16; /* MC 63 Feedback */
PINNODE 664 = XXL_271; /* MC 64 Feedback */
PINNODE 671 = R43; /* MC 71 Feedback */
PINNODE 672 = R33; /* MC 72 Feedback */
PINNODE 673 = R42; /* MC 73 Feedback */
PINNODE 674 = R32; /* MC 74 Feedback */
PINNODE 676 = XXL_269; /* MC 76 Feedback */
PINNODE 679 = XXL_270; /* MC 79 Feedback */
PINNODE 695 = R44; /* MC 95 Feedback */
PINNODE 696 = R34; /* MC 96 Feedback */

** Resource Usage **


DCERP Field = Summary of Allocations.
|||||
|||||_Preset [p,-]       ==  p = PT preset, - No Preset.
||||
||||__Reset [g,r,-]      ==  g= Global AR, r = PT reset, - No reset.
|||
|||___Clock Enable [e,-] ==  e = Product Term, - always enabled, - none.
||
||____Clock [c,g,-],     ==  c = Product term, g = Global term, - No Clock.
|
|_____Type [C,D,L,T],    ==  Register type C= combin, D=dff, L=latch, T=tff.

For input only = INPUT.

MCell Pin# Oe   PinDrive   DCERP  FBDrive  DCERP  Foldback  CascadeOut     TotPT output_slew
MC1   4    on   RomA15     C----  --              --        --             4     slow
MC2   0         --                --              --        --             0     slow
MC3   3    on   RomA16     C----  --              --        --             4     slow
MC4   0         --                --              --        --             0     slow
MC5   2    on   RomA17     C----  --              --        --             4     slow
MC6   1    on   nRomCS     C----  --              --        --             1     slow
MC7   0         --                --              --        --             0     slow
MC8   100  PT   nWAIT      Lc---  --              --        --             3     slow
MC9   99        --                --              --        --             0     slow
MC10  0         --                --              --        --             0     slow
MC11  98   --   nWR        INPUT  --              --        --             0     slow
MC12  0         --                --              --        --             0     slow
MC13  96   --   nRD        INPUT  --              FB_263    --             1     slow
MC14  95   --   nIORQ      INPUT  --              FB_262    --             1     slow
MC15  0         --                --              DOWAIT    --             1     slow
MC16  94   --   nMREQ      INPUT  --              NOWAIT    --             1     slow
MC17  16   --   A4         INPUT  R21      Dc-g-  --        --             2     slow
MC18  0         --                R14      Dc-g-  --        --             2     slow
MC19  15   --   A3         INPUT  R13      Dc-g-  --        --             2     slow
MC20  0         --                R12      Dc-g-  --        --             2     slow
MC21  14   --   A2         INPUT  R11      Dc-g-  --        --             2     slow
MC22  12   --   A1         INPUT  R10      Dc-g-  --        --             2     slow
MC23  0         --                R41      Dc--p  --        --             3     slow
MC24  11   --   A0         INPUT  R40      Dc--p  --        --             3     slow
MC25  10        --                R24      Dc-g-  --        --             2     slow
MC26  0         --                R31      Dc--p  --        --             3     slow
MC27  9         --                R22      Dc-g-  --        --             2     slow
MC28  0         --                R20      Dc--p  --        --             3     slow
MC29  8    on   Z80RESET   C----  --              --        --             1     slow
MC30  7         --                R23      Dc-g-  --        --             2     slow
MC31  0         --                XXL_265  C----  --        --             4     slow
MC32  6    --   TDI        INPUT  XXL_266  C----  --        --             4     slow
MC33  27   --   A13        INPUT  --              --        --             0     slow
MC34  0         --                --              --        --             0     slow
MC35  26   --   A12        INPUT  --              --        --             0     slow
MC36  0         --                --              --        --             0     slow
MC37  25   --   A11        INPUT  --              --        --             0     slow
MC38  24   --   A10        INPUT  R47      Dc-g-  --        --             2     slow
MC39  0         --                R45      Dc-g-  --        --             2     slow
MC40  23   --   A9         INPUT  R37      Dc-g-  --        --             2     slow
MC41  22   --   A8         INPUT  R27      Dc-g-  --        --             2     slow
MC42  0         --                R35      Dc-g-  --        --             2     slow
MC43  21   --   A7         INPUT  R25      Dc-g-  --        --             2     slow
MC44  0         --                R15      Dc-g-  --        --             2     slow
MC45  19   --   A6         INPUT  R17      Dc-g-  --        --             2     slow
MC46  18   --   A5         INPUT  XXL_268  C----  --        --             4     slow
MC47  0         --                XXL_267  C----  --        --             4     slow
MC48  17   --   TMS        INPUT  XXL_264  C----  --        --             4     slow
MC49  39   PT   D7         Lc---  --              --        --             3     slow
MC50  0         --                --              --        --             0     slow
MC51  38   PT   D6         Lc---  --              --        --             3     slow
MC52  0         --                --              --        --             0     slow
MC53  37   PT   D5         Lc---  --              --        --             3     slow
MC54  35   PT   D4         Lc---  --              --        --             3     slow
MC55  0         --                R46      Dc-g-  --        --             2     slow
MC56  34   PT   D3         Lc---  --              --        --             3     slow
MC57  33   PT   D2         Lc---  --              --        --             3     slow
MC58  0         --                R30      Dc-g-  --        --             2     slow
MC59  32   PT   D1         Lc---  --              --        --             3     slow
MC60  0         --                R36      Dc-g-  --        --             2     slow
MC61  31   PT   D0         Lc---  --              --        --             3     slow
MC62  30   --   A15        INPUT  R26      Dc-g-  --        --             2     slow
MC63  0         --                R16      Dc-g-  --        --             2     slow
MC64  29   --   A14        INPUT  XXL_271  C----  --        --             4     slow
MC65  42        --                --              --        --             0     slow
MC66  0         --                --              --        --             0     slow
MC67  43        --                --              --        --             0     slow
MC68  0         --                --              --        --             0     slow
MC69  44        --                --              --        --             0     slow
MC70  46   --   CLK        INPUT  --              --        --             0     slow
MC71  0         --                R43      Dc-g-  --        --             2     slow
MC72  47   --   nINT       INPUT  R33      Dc-g-  --        --             2     slow
MC73  48   --   nNMI       INPUT  R42      Dc-g-  --        --             2     slow
MC74  0         --                R32      Dc-g-  --        --             2     slow
MC75  49   on   Debug1     C----  --              --        --             1     slow
MC76  0         --                XXL_269  C----  --        --             4     slow
MC77  50   on   Debug2     C----  --              --        --             1     slow
MC78  51        --                --              --        --             0     slow
MC79  0         --                XXL_270  C----  --        --             4     slow
MC80  52        --                --              --        --             0     slow
MC81  54   on   ATCLK      Dg---  --              --        --             1     slow
MC82  0         --                --              --        --             0     slow
MC83  55        --                --              --        --             0     slow
MC84  0         --                --              --        --             0     slow
MC85  56   on   nCLK       C----  --              --        --             1     slow
MC86  57        --                --              --        --             0     slow
MC87  0         --                --              --        --             0     slow
MC88  58        --                --              --        --             0     slow
MC89  59        --                --              --        --             0     slow
MC90  0         --                --              --        --             0     slow
MC91  60        --                --              --        --             0     slow
MC92  0         --                --              --        --             0     slow
MC93  62        --                --              --        --             0     slow
MC94  63        --                --              --        --             0     slow
MC95  0         --                R44      Dc-g-  --        --             2     slow
MC96  64   --   TCK        INPUT  R34      Dc-g-  --        --             2     slow
MC97  65        --                --              --        --             0     slow
MC98  0         --                --              --        --             0     slow
MC99  66        --                --              --        --             0     slow
MC100 0         --                --              --        --             0     slow
MC101 67        --                --              --        --             0     slow
MC102 69   --   nResume    INPUT  --              --        --             0     slow
MC103 0         --                --              --        --             0     slow
MC104 70        --                --              --        --             0     slow
MC105 71        --                --              --        --             0     slow
MC106 0         --                --              --        --             0     slow
MC107 72   on   nCS_Serial C----  --              --        --             1     slow
MC108 0         --                --              --        --             0     slow
MC109 73   on   nCS_HD     C----  --              --        --             1     slow
MC110 74   on   SpareCS    C----  --              --        --             1     slow
MC111 0         --                --              --        --             0     slow
MC112 75   --   TDO        INPUT  --              --        --             0     slow
MC113 77   on   nCS_RTC    C----  --              --        --             1     slow
MC114 0         --                --              --        --             0     slow
MC115 78   --   nBUScon    INPUT  --              --        --             0     slow
MC116 0         --                --              --        --             0     slow
MC117 79        --                --              --        --             0     slow
MC118 80        --                --              --        --             0     slow
MC119 0         --                --              --        --             0     slow
MC120 81   on   RomA14     C----  --              --        --             4     slow
MC121 82   on   RomA13     C----  --              --        --             1     slow
MC122 0         --                --              --        --             0     slow
MC123 83   on   RomA19     C----  --              --        --             4     slow
MC124 0         --                --              --        --             0     slow
MC125 85   on   RomA18     C----  --              --        --             4     slow
MC126 86   on   nRomRD     C----  --              --        --             1     slow
MC127 0         --                --              --        --             0     slow
MC128 87   on   nRomWE     C----  --              --        --             1     slow
MC0   92        --                --              --        --             0     slow
MC0   91        nRESET     INPUT  --              --        --             0     slow
MC0   90        --                --              --        --             0     slow
MC0   89        XCLK       INPUT  --              --        --             0     slow

Logic Array Block	Logic Cells	I/O Pins	Foldbacks	TotalPT		FanIN	Cascades
A: LC1	- LC16		5/16(31%)	9/16(56%)	4/16(25%)	20/80(25%)	(20)	0
B: LC17	- LC32		16/16(100%)	7/16(43%)	0/16(0%)	39/80(48%)	(25)	0
C: LC33	- LC48		11/16(68%)	10/16(62%)	0/16(0%)	28/80(35%)	(25)	0
D: LC49	- LC64		14/16(87%)	10/16(62%)	0/16(0%)	38/80(47%)	(25)	0
E: LC65	- LC80		8/16(50%)	5/16(31%)	0/16(0%)	18/80(22%)	(25)	0
F: LC81	- LC96		4/16(25%)	3/16(18%)	0/16(0%)	6/80(7%)	(13)	0
G: LC97	- LC112		3/16(18%)	5/16(31%)	0/16(0%)	3/80(3%)	(12)	0
H: LC113- LC128		7/16(43%)	8/16(50%)	0/16(0%)	16/80(20%)	(26)	0

Total dedicated input used:	2/4 	(50%)
Total I/O pins used		57/80 	(71%)
Total Logic cells used 		68/128 	(53%)
Total Flip-Flop used 		42/128 	(32%)
Total Foldback logic used 	4/128 	(3%)
Total Nodes+FB/MCells 		72/128 	(56%)
Total cascade used 		0
Total input pins 		31
Total output pins 		28
Total Pts 			168
Creating pla file C:\USERS\BERT_\DOCUMENTS\01_CCZ80_COMP\CCZ80_MPU\CPLD\MEMMAP.tt3 with 0 inputs 0 outputs, 0 pins 0 nodes and 0 pterms...

----------------  End fitter, Design FITS
$Device PQFP100 fits 
FIT1508 completed in 0.00 seconds
