DA8 | <-- | 1 | CRT9x53 | 40 | --> | DA7 | |
DA9 | <-- | 2 | 39 | --> | DA6 | ||
DA10 | <-- | 3 | 38 | --> | DA5 | ||
GND | --- | 4 | 37 | --> | DA4 | ||
XTAL2 | <-- | 5 | 36 | --> | DA3 | ||
XTAL1 | --> | 6 | 35 | --> | DA2 | ||
<-- | 7 | 34 | --> | DA1 | |||
INTOUT | <-- | 8 | 33 | --> | DA0 | ||
<-- | 9 | 32 | <-> | DB7 | |||
DD0 | <-> | 10 | 31 | <-> | DB6 | ||
DD1 | <-> | 11 | 30 | <-> | DB5 | ||
DD2 | <-> | 12 | 29 | <-> | DB4 | ||
DD3 | <-> | 13 | 28 | <-> | DB3 | ||
DD4 | <-> | 14 | 27 | <-> | DB2 | ||
DD5 | <-> | 15 | 26 | <-> | DB1 | ||
DD6 | <-> | 16 | 25 | <-> | DB0 | ||
DD7 | <-> | 17 | 24 | <-- | A/ |
||
HSYNC | <-- | 18 | 23 | <-- | |||
VSYNC | <-- | 19 | 22 | <-- | R/ |
||
CSYN | <-- | 20 | 21 | <-- | VCC | ||
CRT 9053 | CRT 9153 |
---|
Built-in High Frequency (4 to 18.7 MHz) Oscillator
Built-in Video Shift Register
Built-in Character Generator (128 Characters, 7×11 Dot Font)
Bi-Directional Smooth Scroll Capability
Visual Attributes Include Reverse Video, Intensity Control, Underline, and Character Blank and Blink
Separate HSYNC, VSYNC and VIDEO Outputs Composite Sync (RS170 Compatible) Output Absolute (RAM address) Cursor Addressing MASK Programmable Video Parameters: Dots Per Character Block (8-9) Raster Scans Per Data Row (11-13) Characters Per Data Row (32,48,64,80) Data Rows Per Page (8,10,12,16,20,24 or 25) Horizontal Blanking (8-64 Characters) Horizontal Sync Front Porch (0-7 Characters) Horizontal Sync Duration (1-64 Characters) Horizontal Sync Polarity Two Values of Vertical Blanking Two Values of Vertical Sync Front Porch (0-63 Scan Lines) Two Values of Vertical Sync Duration (1-16 Scan Lines) Vertical Sync Polarity Internal 128 Character 7×11 Dot Font Character/Cursor Underline Position Character/Cursor Blink Rate Scan Row and Column for Thin Graphics Entity Segments Scan Rows and Columns for Wide Graphics Entity Elements
Software Enabled Non-Scrolling 25th Data Row Available with 25 Data Row/Page Display
Non-Interlace Display Format
Embedded Attribute or Tag Bit Attribute Capability
Separate Display Memory Bus Eliminates Contention Problems
Fill (Erase) Screen Capability
Standard 8-bit Data Bus Microprocessor Interface
Wide Graphics with Six Independently Addressable Segments Per Character Space
Thin Graphics with Four Independently Addressable Segments Per Character Space
Single + 5V Supply
COPLAMOS® n-Channel Silicon Gate Technology
TTL Compatible
The CRT 9053 EVTLC and CRT 9153 EVTLC are mask-programmable 40-pin COPLAMOS® n-channel MOS/LSI Video Display Controller Chips that combine video timing, video attributes, alphanumeric and graphics generation, smooth scroll and screen buffer interface functions.
The EVTLC incorporates many of the features (previously requiring a number of external components) required in building a low cost yet versatile display interface. An internal mask programmable 128 character font provides for a full ASCII character set. Wide graphics allow plotting and graphing capabilities while thin graphics and visual attributes can make the display of forms straight-forward.
Two pinout configurations enhance the versatility of the
EVTLC. The CRT 9053 controls data flow over the
processor system data bus through separate read (
The EVTLC provides two independent data buses; one bus that interfaces to the processor and one that interfaces to the display memory. Data is transferred to the display memory from the processor through the EVTLC eliminating contention problems and the need for a separate row buffer.
The EVTLC has an internal crystal oscillator requiring only an external crystal to operate. Masked constants for critical video timing simplify programming, operation and improve reliability. A separate non-scrolling status line (enabled or disabled by the processor) is available for displaying system status.
Z80 is a registered trademark of Zilog Corporation. Z8 is a trademark of Zilog Corporation.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications: consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best product possible.