J069 SVC

EVTLC Data

DESCRIPTION OF SYSTEM OPERATION

The video controller is referred to throughout the Appendix as an EVTLC (Enhanced Video Terminal Logic Controller). The SMC 9153 circuit provides two control functions. One function interprets and controls data from the system processor interface through data bus bits 7-0. The other function generates and refreshes the video image on the screen. Because the system data is isolated from the display data bus, the SMC 9153 maintains complete control over access to display memory. All data flow between display RAM and the processor or the SMC 9153 takes place through the SMC 9153.

DISPLAY MEMORY ACCESS

Processor display memory access is a accomplished through the CHARACTER register of the SMC 9153. All processor transfers to or from the CHARACTER register take place only when the DONE bit is high. The DONE bit is used to synchronize data transfers between the SMC 9153 and the processor. When the processor needs to store a byte of data in the display memory, it will write the byte to the CHARACTER register of the SMC 9153. The SMC 9153 will immediately reset the DONE bit indicating that the transfer hardware is busy. At the next blanked Video time, the SMC 9153 will store the byte in the display memory, increment the character address (if auto increment is enabled) and set the DONE bit. When the processor needs to read a byte of data from the display memory, it will read the CHARACTER register. The SMC 9153 will fetch the desired byte from the display memory during the next blanked VIDEO time, increment the character address (if enabled), and set the DONE bit. When the processor detects that the DONE bit is set, it will read the CHARACTER register to get the data byte from the SMC 9153. This read will reset the DONE bit and cause the SMC 9153 to fetch the next byte of data from the memory.

If auto increment is not enabled, the processor must set the cursor address in the CURLO and CURHI register to the address of the memory location being read from, or written into, before every access to the CHARACTER register.

It should be noted that Auto increment does not affect the visible cursor location. If auto-increment is enabled, the current character location will equal the cursor position only for the first character transfered following an update of the CURLO and CURHI registers. Note that the DONE bit must be high before attempting to update the cursor registers because the loading of the cursor registers will reset the character position counters to the cursor position.

SMOOTH SCROLL

The SMC 9153 may be programmed to do either "jump" or "smooth" scrolling. Jump scrolling moves the data up or down the monitor screen one data row at a time. Smooth scrolling moves the data up the monitor screen one scan line at a time. The number of scan lines and the rate they move up the screen is under processor control.

Smooth scroll is control led through manipulation of the SS3-SS0 bits of the CURHI register. These bits represent the binary address of the first scan line of the first data row displayed on the monitor screen (the data row whose beginning is in the TOSADD register). When the value represented by these bits is incremented, the video data on the monitor screen moves up by the same number of scan lines. After the address of the last scan line of the data row is loaded into the CURHI register and the VIDEO data has moved up the last scan line of the data row, the processor should reset the SS3-SS0 addresses to point to scan line 0 and do a jump scroll. Jump scroll is accomplished by incrementing the RAM address in the TOSADD register by a data row length (so that it points to the address of the first character of the new top data row on the monitor).

When programming for a data row of 80 characters/data row display (1920 data words) for example, the display RAM contains 25 actual rows of data (2000 RAM locations). If the smooth scroll offset equals zero, the SMC 9153 will display the 1919 RAM locations following the top of screen address when displaying data. The first data row is partially scrolled off the screen and the 25th data row is scrolled onto the screen when the smooth scroll offset is incremented. The SMC 9153 will now display the 1999 RAM locations following the top of screen address (wrapping to 0 after address 1999). After SMC 9153 does a jump scroll, the processor must program it to erase the line just scrolled off the screen (preparing it to be scrolled onto the screen). This line now becomes the non-displayed 25th data row.

NON-SCROLLING STATUS LINE

The non-scrolling status line is only functional on a SMC 9153 that has been programmed for 25 data rows. This data row will remain stationary at the bottom of the screen and will not move up the screen when the remainder of the display data is scrolled. Otherwise, VIDEO data on the status line may be manipulated as though it were normal display data. The smooth scroll offset will not function properly when the status line is enabled. The memory address of the characters on the status line are always characters 1920-1999.

CHIP RESET

The CRT 9053 and CRT 9153 Chip Reset requires two steps. The system processor first writes the reset address to the address register of the SMC 9153. The system processor then writes a dummy character to the SMC 9153 Data register. Writing to the Data register resets the chip. This reset process causes the MODE 2 register to be set to the "00" state which disables the blinking cursor and enables the 9x28 operation mode.

REGISTER DESCRIPTION

ADDRESS REGISTER

Writing a byte to the ADDRESS register will select the specified register for the next time the processor accesses the SMC 9153 data registers. The data register addresses are as follows:

register bit name logic
ADDRESS 7-4 xxxx = dont care
3-0 ADDR = 0 1 1 0 = 06h RESET
= 1 0 0 0 = 08h TOSADD
= 1 0 0 1 = 09h CURLO
= 1 0 1 0 = 0Ah CURHI
= 1 0 1 1 = 0Bh FILADD
= 1 1 0 0 = 0Ch ATTDAT
= 1 1 0 1 = 0Dh CHARACTER
= 1 1 1 0 = 0Eh MODE 1
= 1 1 1 1 = 0Fh MODE 2

STATUS REGISTER

When reading the STATUS register, the DONE bit (bit 7 of STATUS Register) will represent the current status of the CHARACTER register. The bit is used to synchronize data transfers between the processor and the SMC 9153. The SMC 9153 will set the DONE bit to a logic one after completing a byte transfer command or a FILL operation. The DONE bit is set to logic zero reading from, or writing to, the CHARACTER register. The processor must wait until the DONE bit is 1 before attempting to change the CURSOR ADDRESS, in order to write a character to, or read a character from, the Character register.

register bit name logic
STATUS 7 DONE = 1, processor may access CURHI, CURLO, and CHARACTER
= 0, processor must wait until transfer of data completed
6-0 xxxxxx = not used

DATA REGISTERS

FILADD

(Fill Address) This register contains the RAM address of the character following the last address to be filled. Writing to this register will enable the SMC 9153 "fill" circuitry. The FILL operation will then be triggered by the next processor write to the CHARACTER register. The FILL operation will write the character in the CHARACTER register to every location in display memory starting with the address specified in the CURLO and CURHI registers through the location preceding the address specified in the FILADD register. The cursor position is not changed after a FILL operation. Note that the address bits DA3-DA0 are internally forced to 0 forcing the FILADD address to be 00, 16, 32, etc. to 1920. The CURLO and CURHI registers will not be changed by this operation. Writing to the CHARACTER register will cause the SMC 9153 to reset bit 7 of the STATUS register to "0". Bit 7 will set to 1 after the SMC 9153 has filled the last memory location specified.

register bit name logic
FILADD 7 x = not used
6-0 DA10-4 Display RAM Address to FILL to

TOSADD

(Top of Screen Address) This register contains the RAM address of the first character displayed at the top of the video monitor screen. In addition, this register controls selection of either of two mask programmable vertical scan rates.

register bit name logic
TOSADD 7 TIM must be cleared to zero for correct operation
6-0 DA10-4 Top of Screen Address bits 10 to 4

Note that address bits DA3-DA0 are internally forced to 0 forcing the first address at the beginning of each row to be 00, 16, 32, etc. to 1920. The most significant bit of this register (TIM) must be set to zero.

CURLO

(Cursor Low) This register contains the eight lower order address bits of the RAM cursor address. All FILL screen and character transfer operations begin at the memory location pointed to by this address.

register bit name logic
CURLO 7-0 DA7-0 Cursor Display-Address bits 7 to 0

CURHI

(Cursor High) This register contains the three higher address bits of the RAM cursor address (DA10, DA9, DA8). All FILL screen and character transfer operations begin at the memory location pointed to by this address. In addition, the register contains the Smooth Scroll Offset Values SS3-SS0 which determine the number of scan lines that the data is shifted on the screen. The MSB of this register (SLE- Status Line Enable) is the enable for the non-scrolling status line.

register bit name logic
CURHI 7 SLE = 1 enables non-scrolling (25th) status line
= 0 disables status line
6-3 SS3-0 Smooth Scroll Offset Value
2-0 DA10-8 Cursor Display-Address bits 10 to 8

ATTDAT

(Screen Attribute Data) Two attribute modes are provided. In the "tag bit" attribute mode, bit 7 of each character is used to "tag" those characters which are to be enhanced with the attribute specified by the ATTDAT register. This allows individual characters to be attributed, but with the limitation that only one attribute style may be enabled for a specific screen. This is compatible with the CRT9028/9128 and is specified as the 9x28 operation mode. In the "embedded attribute" mode, multiple attributes may be displayed on the screen. This is specified as the 9x53 operation mode. See "MODE 2" register for selection of 9x28 modes.

The ATTDAT register specifies the visual attributes of the video data in 9x28 operation mode, and the cursor presentation. The visual attributes specified in the ATTDAT register (bits 3-0) are enabled or disabled by a TAG bit (bit 7) that is appended to the ASCII character written to the CHARACTER register. Every character on the screen with its TAG bit set is displayed with the same attribute. Changing the Attribute register will change the attribute of every "tagged" character on the screen. Character attributes in the 9x53 mode are determined by specific attribute characters embedded in the character data stream as explained below in the section titled CHARACTER SETS. The functions of the remaining bits in the ATTDAT register are not affected by the display character's TAG bit.

NOTE: Alll 8 bits are valid for the 9x28 mode. In the 9x53 mode the only bits that are recognized are bits 6, 5 and 4.

register bit name logic
ATTDAT 7 MODE-SELECT = 1 enables graphics mode display (no attributes)
= 0 enables alphanumeric mode display
Note: See CHARACTER SETS for definition of character sets available in each mode
6 CURSOR SUPPRESS = 1 inhibits display at cursor
(appears as background)
= 0 enables video display at cursor time
(the cursor may be blinked by toggling this bit from software)
5 CURSOR DISPLAY = 1 enables underline cursor display
Note: An underline cursor in an underline character will be dashed
= 0 enables block cursor display
4 SCREEN = 1 for black characters on white screen
= 0 for white characters on black screen
Note: This a screen attribute (not a character attribute) and specifies the default video background level

Bits 3–0 are attribute bits and are not recognized (dont care) in 9153 mode
3 CHARACTER SUPPRESS = 0 to enable video suppress
= 1 to inhibit video suppress
2 INTENSITY = 1 to intensify character
= 0 for normal intensity
1 UNDERLINE = 1 to underline character
= 0 for normal character
0 REVERSE = 1 to swap background and foreground levels VIDEO (those selected by bit 4)
= 0 for normal video

MODE 1

The AUTO INCREMENT bit in this register specifies whether or not the display memory character address is automatically incremented by the SMC 9155 after every read/write of the CHARACTER register. Note: The visible cursor position is not affected.

register bit name logic
MODE 1 7 AUTOINC = 1 for automatic increment of the display memory address after every display memory access
= 0 disables auto increment
6-0 xxxxxx = don't care

MODE 2

This register contains two bits which control operational modes of the device. Bit 0 controls whether the device operates as a 9x53 or emulates the 9x28. In the 9x28 mode the device is fully compatible with the CRT 9028/9128 with the exception of the higher density character set. Bit 1 enables the cursor blink function where the blink rate is a mask programmable feature (see CRT 9053/9153 coding sheet.) This function is automatically disabled when in 9x28 mode.

register bit name logic
MODE 2 7-2 xxxxxx = don't care
1 CURSOR BLINK = 1 enables blinking cursor
= 0 for steady cursor control led by bit 6 of ATTDAT register
0 9x53 ENABLE = 1 to enable 9053/9153 operation
= 0 for 9028/9128 operation

CHARACTER

This register allows access to the display memory for both byte transfers and FILL operations. In BYTE Transfer Write Mode, the processor first writes a character to this register. The SMC 9153 takes that character and stores it in the display memory in the location specified by the CURLO and CURHI registers. In Byte Transfer Read Mode, the processor reads this register causing the SMC 9153 to fetch the character (whose address is specified in the CURLO and CURHI registers) from the display memory and place it in the CHARACTER register. The processor then reads the character and initiates another fetch from memory cycle. In FILL mode, writing a byte to this register will initiate a FILL operation. All SMC 9153/memory data transfers take place during horizontal and vertical video retrace blank time.

register bit name logic
CHARACTER 7-0 CHAR 8-bit character value

See next section, CHARACTER SETS, for definition of 8 bit characters.

CHARACTER SETS

The character set consists of 128 characters, a six segment "wide graphics" and a four segment "thin graphics" entity. Included in the 128 mask programmable characters can be the 96 standard ASC11 characters and 32 special characters.

9x28 OPERATION MODE (MODE 2: bit 0 = 0)

A. GRAPHICS MODE - (ATTDAT: bit 7 = 1)

This mode allows an intermix of alphanumeric and graphics characters. No attributes are permitted in this mode. If bit 7 = 1, the character will be alphanumeric. If bit 7 = 0, the character will be a graphics character. Bit 7 is the “tag bit”.

Bit number76543210
CHARACTER07-bit Character data
THIN GRAPHICS00xxSEG4SEG3SEG2SEG1
WIDE GRAPHICS00SEG6SEG5SEG4SEG3SEG2SEG1
B. ALPHANUMERICS MODE (ATTDAT: bit 7 = 0)

This mode allows display of alphanumeric characters with attributes. If bit 7 (of a screen data byte) is set to a logical one, the attribute(s) specified in the ATTDAT register will be enabled for that character. If a bit 7 is cleared, attributes will not be enabled for that character. Bit 7 is called a “tag bit”.

Bit number76543210
CHARACTER07-bit Character data
ATTRIBUTE
CHARACTER
100BLANKBLINKINTENSITYUNDER
LINE
REVERSE
THIN GRAPHICS10xxSEG4SEG3SEG2SEG1
WIDE GRAPHICS10SEG6SEG5SEG4SEG3SEG2SEG1

9x53 OPERATION MODE (MODE 2: bit 0 = 1)

This mode allows the use of embedded field attributes where the desired attribute for any given string of one or more consecutive characters is defined by an attribute character which is part of the character data stream and is located immediately in front of the characters to be attributed. A second attribute character should be located immediately following the string of attributed characters to restore the normal display mode. Since the specific attribute characters occupy character positions, they are actually displayed as spaces.

  1. Graphics segments are turned on when bit is set to a "1".

  2. A specific field attribute is enabled by setting the appropriate bit and disabled by resetting the bit. Attributes can be mixed. The following defines the available attributes indicated in the ATTRIBUTE CHARACTER.

    bit 4 (BLANK) - Suppresses character video output.
    bit 3 (BLINK) - Causes character to blink at mask programmed rate.
    bit 2 (INTENSITY) - Controls INTOUT output pin.
    bit 1 (UNDERLINE)-Causes character to be underlined.
    bit 0 (REVERSE VIDEO) - Reverses foreground/background video levels.

GRAPHICS CHARACTERS

  1. Pixels within Wide Graphics character numbered by segment.

    Note segments 6, 5, and 4 have different width from 3, 2, and 1. This allows the segments to join up with neighbouring segments (including those on the character rows above and below. Although not exactly square, wide graphics characters can be used as low resolution pixels.

    Column876543210
    Scanline 0 →6 3
    Scanline 1 →
    Scanline 2 →
    Scanline 3 →
    Scanline 4 →5 2
    Scanline 5 →
    Scanline 6 →
    Scanline 7 →
    Scanline 8 →4 1
    Scanline 9 →
    Scanline 10 →
    Scanline 11 →
  2. Pixels within Thin Graphics character numbered by segment

    Note central pixel (marked +) is always present if one or more segments are "on", allowing box corners to be constructed.

    Column →876543210
    Scanline 0 → 3
    Scanline 1 →
    Scanline 2 →
    Scanline 3 →
    Scanline 4 →
    Scanline 5 →
    Scanline 6 →5 + 2
    Scanline 7 → 1
    Scanline 8 →
    Scanline 9 →
    Scanline 10 →
    Scanline 11 →