J069 SVC

Links and Options

The boards are described as if you were viewing them from the component side with the bus connector to the right.

Note:
+ indicates the standard link connection, as supplied.
* indicates a signal is active low

Link positions

Fig. 1. Link Positions


LK1 Board addresses
	LK1H	select if A4 low
	LK1G	select if A5 low
	LK1F	select if A6 low
	LK1E	select if A7 low
+	LK1D1	ignore A8
	LK1D2	select if A8 low
+	LK1C1	ignore A9
	LK1C2	select if A9 low
+	LK1B1	ignore A10
	LK1B2	select if A10 low
+	LK1A1	ignore A11
	LK1A2	select if A11 low
Figure 2. Link Area 1
   
o H  o    
o G  o    
o F  o    
o E  o ___
o D1 o D2 o
o C1 o C2 o
o B1 o B2 o
o A1 o A2 o

Standard jumpering as shown above gives a base address of the board of 3A0 (hexadecimal). Note that some operating systems may not access this board at the standard address. You MUST check in the software manual.

The board will be selected when a particular combination of address bits and command modifiers is sent to it, with the strobe lines and DATSTB* active. The command modifiers are those for I/O cycles - CM2 high, CM1 low and CM0 high or low for read or write. The address bits are determined by the jumpering on LK1, which sets what the top eight bits of the address are required to be, and the jumpering on LK3 and LK4 which determine what A2 and A3 should be. The internal configuration of IC5 deals with the lower two bits. STEbus I/O accesses use twelve of the twenty address lines.

If any of the jumpers A2, B2, C2, D2, E, F, G, H is inserted, the corresponding comparison address bits (A11 to A4) must be low for the board to be selected, as shown in the table above. For example, consider the base address of the board, which is the address of the data register of the chip (see Section 5 for more details). If all these jumpers are inserted, the base address is 000.

If one of the above jumpers is removed, the corresponding address bit must be high for the board to be selected. Thus, with no jumpers, the base address is FF0 (i.e. BASE = 4080 decimal).

If jumpers A1, B1, C1, D1 are inserted, the top 4 bits of the 12-bit address are not used in the comparison, so with these jumpers in, the base address is XF0.

If you do not wish to have to set up the top four address lines (for convenience when programming with an 8-bit CPU with a 256 byte I/O map, for example), then make A1, B1, C1 and D1, and leave A2, B2, C2, D2 open.

Another way of looking at the question of address selection is to consider the address lines to have a 'weight', as follows.

Table 1. Address Weights.

LK1Address
Line
Hex
weight
Decimal
weight
H A4 10 16
G A5 20 32
F A6 40 64
E A7 80 128
D A8 100 256
C A9 200 512
B A10 400 1024
A A11 800 2048

The standard base address is 03A0h (links H2, F2, B2 and A2 made)

Link 2 RAM Size
+	Link 2A is made for 2k static RAM devices.
	Link 2A is cut for 8k static RAM devices.
Figure 3. Link Area 2
o A o
Links 3,4 Base Address (lower four bits)
+	LK3B select if A2 low
	LK3A select if A2 high
+	LK4B select if A3 low
	LK4A select if A3 high
Figure 4. Link Area 3
o A o
o B o
Figure 5. Link Area 4
o A o
o B o

Up to four SVC's may reside within 16 I/O locations.

+	SVC base address 0-3		make LK3 B, LK4 B.
	SVC base address 4-7		make LK3 A, LK4 B. 
	SVC base address 8-11		make LK3 B, LK4 A. 
	SVC base address 12-15		make LK3 A, LK4 A.
Link 5 Attention Request Lines

Make one of these links if using interrupts:

	LK5 H Interrupt generated on ATNRQ0* 
	LK5 G Interrupt generated on ATNRQ1* 
	LK5 F Interrupt generated on ATNRQ2* 
	LK5 E Interrupt generated on ATNRQ3* 
	LK5 D Interrupt generated on ATNRQ4* 
	LK5 C Interrupt generated on ATNRQ5*
	LK5 B Interrupt generated on ATNRQ6* 
	LK5 A Interrupt generated on ATNRQ7*
Figure 6. Link Area 5
o H o
o G o
o F o
o E o
o D o
o C o
o B o
o A o