J069 SVC
The SVC is based on the SMC 9153 text controller device. This device (IC10) provides CRT timing and video signals, supports external character memory, and has an internal. ASCII character set and a microprocessor interface. Access to the text controller chip from the STEbus is accomplished by IC5, 6 and 7. IC5 and IC7 are programmable logic arrays which decode a valid bus access, enable data bus buffers, and provide DATACK* and ATNRQ* signals. IC6 is a shift register used as a delay line. The outputs from this device are used by IC5 and 7 to synchronise signals to IC10 and return signals to the bus.
The SVC occupies four I/O locations. The lower two are accesses to IC10 while the upper two addresses are used for attention request generation. Attention request signals are generated on the falling edge of horizontal sync following an I/O write to base address+3.
This address should be written to following every character transfer until the software-maintained output buffer is empty. The sequence must be restarted by writing to this address if a character is written into an empty buffer.
The video circuitry supports two types of video monitor. Composite video compatible with the RS170 standard is provided on pin 1 of PL2 while pins 3, 4 and 5 are TTL level vertical sync, horizontal sync and video respectively. The intensity attribute is adjustable for the composite video output by VR1, the TTL monitor video intensity is fixed by R9 and R10.
The composite video and sync. output is compatible with most monitors that accept a composite video and sync. input Vertical sync. is identified by horizontal sync. being inverted for the vertical sync. period. The sync. timing is similar to that of a 625 line television system.
Horizontal scan period = 64 µs Frame refresh period = 20 ms Output load impedance = 75 ohms