Links and Options

The boards are described as if you were viewing them from the component side with PL4 to the right.



Note:
+ indicates the standard link connection, as supplied.
* indicates a signal is active low

Link positions

Link area 1. Base Address selection

  LK1H select if A4 low
+ LK1G select if A5 low
+ LK1F select if A6 low
  LK1E select if A7 low
  LK1D select if A8 low
  LK1C select if A9 low
  LK1B select if A10 low
  LK1A select if A11 low
Link area 1.
o A o
o B o
o C o
o D o
o E o
o F o
o G o
o H o

Standard jumpering as shown above gives a base address of F90 (hex) or 3984 (decimal). Note that some operating systems may not access this board at the standard address. You MUST check with the appropriate software manual.

LK1 sets up the standard base address of the SG84 in STE I/O space. The standard base address is F90 (hex). Inserting a jumper on link 1 means the board will only respond if that address line is low, omitting a jumper means the board will only respond if that address line is high.

Table 1. Address Weights

LK1 Address Hex Dec
    Line
H     A4	10      16
G     A5	20      32
F     A6	40      64
E     A7	80     128
D     A8	100    256
C     A9	200    512
B     A10       400   1024
A     A11       800   2048

Link 2. DATACK* to STEbus

+ LK2 DATACK* goes to STEbus

Remove this link only when the test connector is being used.

Link 2.
o o

Link areas 3 and 4. Interrupt and DMA Attentlon request outputs

LK3A  Interrupt request output on ATNRQ0*
LK3B  Interrupt request output on ATNRQ1*
LK3C  Interrupt request output on ATNRQ2*
LK3D  Interrupt request output on ATNRQ3*
Link area 3.
o A o
o B o
o C o
o D o
LK4A2 Interrupt request output on ATNRQ4*
LK4B2 Interrupt request output on ATNRQ5*
LK4C2 Interrupt request output on ATNRQ6*
LK4D2 Interrupt request output on ATNRQ7*
LK4A1 DMA transfer request output on ATNRQ4*
LK4B1 DMA transfer request output on ATNRQ5*
LK4C1 DMA transfer request output on ATNRQ6*
LK4D1 DMA transfer request output on ATNRQ7*
Link area 4.
o A1 o A2 o
o B1 o B2 o
o C1 o C2 o
o D1 o D2 o

Link area 5. On-board/external master clock

+ LK5A Normal operation using the on-board oscillator
  LK5B Master clock from external video source
Link area 5.
o A o B o

Note: there must always be a source of master clock, otherwise the ACRTC will be damaged.

Link areas 6, 7 & 8.

Links 6, 7, and 8. Analogue RGB output signal termination

LK6 75R termination on analogue red signal
LK7 75R termination on analogue green signal
LK8 75R termination on analogue blue signal
LK7 o  o  LK6
    o  o
LK8 o
    o

Link area 9. IC17 Screen blanking option

  LK9A ACRTC 'flash' option blanks video output (TTL monitors)
+ LK9B video output blanked during palette write cycles (analogue monitors)
Link area 9.
o A o B o

Links 10, 13, 17-19. TTL/Analogue video output to PL4

LK10 PL4 pin 6 is TTL Intensity output

Link areas 10-19

+ LK13A PL4 pin 5 is Analogue blue output
  LK13B PL4 pin 5 is TTL blue output
+ LK17A PL4 pin 8 is HSYNC output
  LK17B PL4 pin 8 is CSYNC output
  LK17C PL4 pin 7 is CSYNC output
+ LK18A PL4 pin 4 is Analogue green output
  LK18B PL4 pin 4 is TTL green output
+ LK19A PL4 pin 3 is Analogue red output
  LK19B PL4 pin 3 is TTL red output

Link areas 11,12, 15 and 16. Signal options

  LK11 Make for positive TTL Hsync pulses
+ LK12 Sync superimposed on analogue RGB
  LK15 Make to invert TTL RGBI outputs
  LK16 Make for positive TTL Vsync pulses

Link area 14. External sync routing

+ LK14A1 External sync out to PL4
+ LK14A2 External sync from ACRTC
  LK14B1 External sync from PL4
  LK1482 External sync in to ACRTC
LK14
o A1 o
B1   B2
o A2 o
o 15 o
o 16 o
 o
17A	o
 o	10
17B	o
 o
17C	o
 o	11
	o
 o
18A
 o	o
 o	12
18B	o
 o
 o   o
19A 13A
 o   o
19B 13B
 o   o

The default link settings have been chosen to suit the majority of monitors. Those that have been tested with the SG84 are listed below, with link adjustments where necessary.

Sony Multisync monitor: Model no. CDP-1402E

Analogue/Digital RGB. Accepts several different sync. standards.

Philips Multimode: Model no. CM8873

Analogue/Digital RGB. Positive syncs, not superimposed on analogue RGB.

Zenith data systems: Model no. ZVM-123-E

Monochrome. Composite video input.

Link Summary

		Default		Sony		Philips		Zenith 
		(Analogue,	multisync	multimode	monochrome
		-ve syncs)	CDP-1402E	CM8873		ZVM-123-E
				Ana, TTL	Ana, TTL
LK6,7,8		-		In	x	-	x	x
LK10		-		x	In	x	In	x
LK11		-		-	x	x	-	x
LK12		In       	-	-	In	In	x
LK13,18,19	A		A	B	A	B	x
LK15		-		-	-	-	-	-
LK16		-		-	-	-	-	-
LK17		A		A	A	A	A	x
- Link out
x Dont care