To use the SG84 the ACRTC control registers must first be initialised, the palette must be programmed and finally drawing commands must be issued to produce screen output.
There are three main groups of registers:
These are accessed at STEbus I/O locations, as described in Section 4. I/O Map.
All these registers are accessed by first writing the register number to the ACRTC address register, then the required value to the data register. They can be sub-divided as follows:
r00H - the FIFO entry register enables access to FIFO accessible, (command accessible) registers.
r02H - the command control register controls overall ACRTC operation such as aborting, defining DMA protocols and enabling/disabling interrupt sources.
r04H - the operation mode register defines basic parameters of ACRTC operation such as frame buffer access mode, display or drawing priority etc.
r06H - the display control register independently enables or disables each of four logical display screens and also contains 8 bits of extra video attributes specific to the SG84.
These registers define ACRTC timing, including specification for CRT control signals, logical display screen size and display period.
These registers define logical screen display parameters such as start addresses and memory width. Also included are the cursor definitions, zoom factors and light pen registers.
Writing to registers 80H onwards will automatically increment the value of the address register by one. 16 bit registers and data are transmitted as two groups of 8 bits, high byte first, low byte second.
All these registers are accessed via the read and write FIFOs, using the ACRTC commands read pattern RAM, write pattern RAM, read parameter register and write parameter regis-ter.
Pattern RAM is used to define drawing and painting patterns. 16 x 16 bits of data may be sent to the pattern RAM, and all drawing operations will then interpret this information according to the values stored in the pattern RAM control registers and the colour registers where 0 (bit not set) corresponds to CL0 and 1 (bit set) corresponds to CL1. Thus, setting both colour registers to the same value will produce solid, one-colour drawing irrespective of the information in the pattern RAM.
These registers define detailed parameters of the drawing process, such as colour control, area control and pattern RAM pointers.
To initialise the ACRTC, the general control registers must first be set up for the operation and access modes required. Some of these require specific explanation.
Graphic bit mode (CCR, high-order, bits 6-4):
4 bits per pixel means that for each of the 640 pixels displayed across the screen, 4 bits of frame buffer information are required. Each of these logical pixels can therefore hold the value 00H to 0FH, corresponding to the 16 definable colours in the palette look-up table.
In 8 bit mode each pixel requires 8 bits of frame buffer information. These can hold the value 00H to FFH, corresponding to the 256 colours in the palette look-up table.
This means that in 4 bits per pixel mode half as much RAM is required to display the same number of pixels as in 8 bits per pixel mode.
For example, if the whole screen is cleared to colour 1, one 16-bit word read from that area would hold the value:
1111H - 4 bit mode (4 pixels)
0101H - 8 bit mode (2 pixels)
Access mode (OMR, low order, bits 3-2):
In 4 bits per pixel mode you should interleave the drawing and display functions (dual access mode 0). In 8 bit mode single access needs to be selected (with display priority) otherwise picture interference would occur while drawing.
Attribute control (DCR, low order, bits 7-0):
Some of these bits are hardware specific to the SG84:
Bit 0 defines the cursor type: 0 = crosshair, 1 = block cursor (cursor type also needs to be defined in CDR, rE8H)
Bit 1 defines the graphic bit mode: 0 = 4 bit mode, 1 = 8 bit mode (this needs to be set to the same mode as defined in the CCR)
Bit 2 provides TTL output to pin 1 of PL5
The timing control registers must be initialised to display at least the base screen, although they are also used to initialise the upper and lower screens, and the window if required. Positioning of these screens can only be done on 32-bit word boundaries relative to the base screen.
Horizontal timing calculations:
SET VIA LINE PERIOD = 64 us = 100% HC (Horizontal cycle) HSYNC = 5.12 us = 8% HSW (Horizontal sync width) BACK PORCH = 5.12 us = 8% HDS (Horizontal display start) ACTIVE DISPLAY PERIOD = 51.2 us = 80% HDW (Horizontal display width) FRONT PORCH = 2.56 us = 4% REMAINING TIME
Frame buffer cycle time is 320 ns for a 25MHz crystal:
4 pixels/word = 320 ns/word
12.5 MHz/pixel
Thus, the values sent to the horizontal timing registers are:
Horizontal Sync register (r82H): C710H
Horizontal Display register (r84H): 0F9FH
Vertical timing calculations:
Typically the vertical flyback period occupies about 7% of the vertical period. In the case of the 312 line system example (i.e. 625 lines, non-interlaced), 20 lines are lost per frame. As the resolution is to be 256 lines, the front and back porches will be 18 lines each.
Thus, the values sent to the vertical timing registers are:
Vertical Sync register (r86H): 0138H
Vertical Display register (r88H): 1114H
Split Screen Width Register (r8AH): 0100H
The display control registers must be initialised for at least the base screen. This involves setting up the start address register (SAR1, high and low bytes) with the physical memory address which will correspond to the top left pixel on the screen, and the memory width reg-ister (MWR1) with the number of 16-bit words to display 1 line of pixels. The memory width is thus dependant on the number of bits per pixel i.e. divide the number of horizontal pixels required by 4 for 4 bits per pixel, or 2 for 8 bits per pixel.
The SG84 has 256k of frame buffer memory available. In 4 bits per pixel mode, with 640 pixels horizontally (i.e. 320 bytes) and 256 pixels vertically, the screen display requires about 82k, leaving 174k extra, which means that drawing is possible outside the displayed area. It is possible to display this extra memory by altering the start address, to produce a scrolling effect.
If the memory width is defined as equal to the display width, only vertical scrolling is possible. if it is defined as greater than the display width, horizontal scrolling is also possible.
After this initialisation procedure, before any drawing is attempted, it is necessary to clear the display area and define a logical origin. These operations require the use of ACRTC commands which are described below.
A palette is simply a colour look-up table. The pixel data from the DRAM is bitwise ANDed with the pixel mask register to form an 8-bit address to a high speed RAM. The 18-bit data from this RAM (6 bits each for red, green and blue respectively) is sent to three 6-bit high-speed D to A converters, which provide the analogue voltage to drive the three colour guns of the monitor. By changing the data in the palette, you can redefine the physical colours produced by the logical pixels.
The palette can be programmed with 16 (4 bits per pixel) or 256 (8 bits per pixel) groups of three intensity values, where 0 is no intensity for that colour, and 63 is maximum intensity.
The colour number register is used to specify the position in the look-up table to be written with a colour value. The colour value register contains the data used to update the contents of the colour number specified by the colour number register.
To write a new value to the table a colour number must be specified and then 18 bits of data written to that colour number in the table. This is done by writing a colour number to the colour number register, and then three successive byte writes to the colour value register. The least significant 6 bits are taken from each byte, the first defines the red intensity, the sec-ond the green and the last the blue. If the colour number register is modified during a colour value write sequence, the colour value register is initialised, aborting any unfinished write sequence.
The colour number register increments automatically after every colour value write sequence.
The colour number used to access the colour look-up table is the result of bitwise ANDing the incoming colour number and the contents of the pixel mask register. For example, if the incoming colour number is 3EH and the mask register contains 0FH, the resulting colour number selected will be 0EH. Thus the displayed colours can be altered without altering the look up table, to produce, for example, flashing objects.
There are a variety of uses for a palette. One can for instance take a grey-level image and assign a false colour to each level in order to highlight details or contours. This would be useful in thermography, with colours representing temperature levels (say blue = cold, red = warm).
Another palette trick is the use of 'invisible ink' drawing. The pixel mask register can be set to &7F, so that colours 128-255 appear the same as colours 0-127. An invisible image can be drawn by setting bit 7 of affected pixels. When this image has been completely drawn, colours 128-255 can be redefined (e.g. as red). When the pixel mask register is set to &FF, all the affected pixels will appear on the screen simultaneously. This trick is useful in real-time animations, because the image is not seen until it has been completely drawn. It also
gives the illusion that the computer is much faster than it actually is, as it appears to the viewer that the image is being redrawn instantly, whereas in actual fact it may use up to all the time between successive frames to generate each frame.
Similar to the example above, but the top half of the palette is a reduced intensity copy of the bottom half, tinted with a desired colour. Hence logical pixels with bit 7 set appear to be translucent to a background image.
ACRTC commands consist of a 16-bit operation code, optionally followed by one or more 16-bit parameters. Commands, parameters and data are sent to and from the ACRTC high byte first, low byte second. The low 8 bits of the operation code may be used to define area, colour and operation modes, where area defines the logical x,y coordinates within which drawing will appear on the display, colour determines the way in which the colour registers are interpreted and operation determines whether the drawing will be done in AND, OR, XOR mode etc. ACRTC drawing commands can be classified into three groups:
Registers associated with drawing (pattern RAM and drawing parameter registers) are accessed using the register access commands. These are the origin command, read and write parameter register, and read and write pattern RAM.
Data transfer commands are used to move 16-bit word data between memory and the frame buffer, or within the frame buffer itself. The horizontal coordinates of these commands re-late to word values across the screen, so they are dependant on the graphic bit mode. Before issuing these commands, a physical 20 bit frame buffer address must be specified by the RWP (read/write pointer) in the drawing parameter registers. They include commands to clear, copy and modify words of data in the frame buffer, and to read and wite words directly.
Graphic drawing is performed by modifying the contents of the frame buffer based upon microcoded drawing algorithms in the drawing processor. There are 23 graphic drawing commands, including commands to move, draw a line, draw a circle etc. They use logical x,y coordinates relative to the most recently defined origin.
Further discussion of the properties of the ACRTC are beyond the scope of this document. For further information refer to the Hitachi HD63484 ACRTC Advanced CRT Controller Users Manual.
The SG84 is designed to be used with a monitor with analogue colour inputs, in order to take full advantage of the palette colour range. The SG84 can also drive a standard TTL-compatible RGB monitor. These are inherently limited to 8 colours, plus intensity. In this case connect the monitor signals (R,G,B, COMPSYNC, GND) to PL4 (as shown in Appendix B. Connections). These outputs are driven by the logical pixel value, since the physical pixel value is internal to the palette chip, so no palette techniques can be used with this type of monitor.
The SG84 may be used with the following monitors:
In countries using a different video standard to the U.K., it is usually possible to modify the board to work with these standards by simply re-programming the ACRTC registers. For example, in the U.S.A. the line period is the same, but the frame period is shorter. In countries where the line period is considerably different to the U.K., it will probably still be possible to sync. with a monitor, but the picture may be the wrong size.