I/O Map

The STEbus has a total of 4096 possible I/O addresses, corresponding to a 12- bit address bus. There are six I/O addresses to which the board will respond. The upper 8 bits of the 12-bit I/O address are set by jumpers, as described in the previous section, and the remaining four bits of the I/O address define the group of I/O addresses to which the board responds. The table below shows the I/O addresses and the meaning of the bits at each address.

Table 1. I/O Addresses

Address Rd/Wr bit Function
base Wr 0-7 ACRTC Address register
Rd   ACRTC Status register
0 Write-FIFO Empty
1 Write-FIFO Ready
2 Read-FIFO Ready
3 Read-FIFO Full
4 Light Pen Strobe Detect
5 Command End
6 Area Detect
7 Command Error
base+1 Rd/Wr 0-7 ACRTC Data register
base+2 Rd/Wr 0-7 Accesses to this location perform a DMA cycle with the ACRTC
base+3 Rd/Wr 0-7 Repeat of above. Non-preferred address
      Palette:
base+4 Wr 0-7 Address register.
Write the 8-bit logical colour number to this location
base+5 Wr 0-7 Colour Value register
Write the red, green, blue values to this location (in that order), then these will be loaded into the colour look-up table and the address register (above) automatically incremented.
base+6 Wr 0-7 Mask register
Incoming pixels from the shift registers are logically ANDed with the mask register before being sent to the colour look-up table.