Applix 1616 programmable logic - timing

PAL16R8 (IC51) Timing logic

      TPAL
OSC(30MHz) --> 1 PAL
 16R8 
20 VCC  
15 MHz --> 2 19 --> 7.5 MHz --> CPU CLK
RAMSEL --> 3 18 --> 3.75 MHz
DISPEN --> 4 17 --> 1.875 MHz
AS --> 5 16 --> DTACKR
UDS --> 6 15 --> RAS
LDS --> 7 14 --> CASL
R/W --> 8 13 --> CASU
RESET --> 9 12 --> LPULSE
  GND 10 11 <-- OE = GND

7.5 MHz needs halving to 3.25 MHz and again to 1.625 MHz, so this is probably done by pins 13 and 18 (though which is which is yet to be determined)

VHDL description

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CUPL description

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