The 1616 is a 68000 machine with colour video, designed by Paul Berger and Andrew Morton after extensive discussion with ETI staff early in 1986. It used publicly available chips, and was "open source" - the circuit details were published in the magazine ETI (Australia).
It predates the first colour Apple Mac (March 1987), which used custom ASIC chips, surface mount, and was "closed source" - even if you got hold of the circuit you coud not get the ASIC chips.
The 1616 looked a good place to start learning how to implement video on a 68000 machine, as a basis for cloning (in FPGA) more popular machines such as the Apple Mac or Atari ST. I've since lost interest in that, I believe people have already done that. I'm only really interested in the electronics, as I can do more with my PC than I can with the old 68000 machines.
However, some people on the Applix forum have expressed in reproducing the 1616. This can be done by stripping a board to the PCB, digitising the PCB patterns and getting copies made. All the chips are still available as of 2021.
There are two programmable logic chips that need to be programmed, but the original logic equations have been lost.
Apart from creating new 1616 machines, they are now a critical component of old machines.
I felt this would be a good exercise project for me. Not trivially easy or unfeasibly difficult, not too time-consuming (I hope), and it is something other people would welcome.
There are too few Applix enthusiasts to make it economically practical to have professionally reverse-engineered. This usually involves several attempts, stripping the plastic away using very scary acids then reading the fuses with a microscope. Few people are keen on having their PALs destroyed without a guaranteed replacement!
Another method is to throw all possible inputs and states at the PAL and analyse the response. This brute force method guarantees to capture the behaviour but then you have to analyse the response. One chap has created a PAL analysis board which simply loads the input states and reads the responses controlled by a PC serial port. The PC then runs Java to analyse the behaviour. His project is on GitHub but presented 'as is', without hand-holding or user manual. This means you have to work out how to use his project, which looks a job in itself. https://github.com/DuPAL-PAL-DUmper
The final way involves looking at the circuit and documentation, analysing the operation, and designing replacements. This involves thinking work, but ultimately leads to real understanding. This is the approach I shall be trying.
Both the processor and the video controller need access to shared memory, and the video data has higher priority.
One way to do this is to have interleaved CPU/VDU memory accesses. I've been familiar with this ever since reading how it was done in the 6502/6845-based BBC Micro. I used the technique in my own 6502 computer project, albeit with static RAM.
Where the 6502 made one clock cycle per memory cycle, the Z80 made 3 or 4, and the 68000 made eight. The clock cycles were numbered 0 to 7.
In the BBC micro, displaying 640 bicolour pixels needed 80 bytes of data in each 40 microsecond video display period. That makes for a 2 MHz byte rate for the 6845. The 6502 also ran at 2 MHz. These were interleaved, so the memory actually ran at 4 MHz memory cycle rate.
In the Applix 1616, two bytes are read every memory cycle. Quoting the articles:
"The MC6845 CRTC video controller (U27) generates timing and addressing signals which interact with the timing PAL to load 16 bits of data from the RAMS into the shift registers (U29 and U30, both 74LS166 8 bit parallel in to 1 bit serial out) every 533 ns. This data is shifted two bits at a time into the video PAL (U5) at 15 MHz."
So the memory cycle time is roughly the same as the BBC Micro, but getting 16 bits instead of 8. This allows the 1616 to have 4 colours at 640-pixels per line, where the BBC Micro had 2.
Operation is simple but there are many pins and connections.
Operation is simple, the odd and even bits of the 16-bit video data are read into two 8-bit shift registers and shifted left (MS bits first).
U4 74LS670 |
4 | ← | 17 | U5 PAL16R8 (video) |
4 | ← | 13 | U31 74LS166 |
|||||||||||||||||
R ← | 6 | 14 | 12 | 11 | 10 | 5 | 4 | 3 | 2 | ||||||||||||||||
G ← | 7 | ↑ | ↑ | ↑ | ↑ | ↑ | ↑ | ↑ | ↑ | ||||||||||||||||
B ← | 9 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ← Video data bit | |||||||
I ← | 10 | ↓ | ↓ | ↓ | ↓ | ↓ | ↓ | ↓ | ↓ | ||||||||||||||||
14 | 12 | 11 | 10 | 5 | 4 | 3 | 2 | ||||||||||||||||||
5 | ← | 16 | 5 | ← | 13 | U29 74LS166 |
Video data bit connections
The 74LS670 4x4-bit register is a rather specialised function, and I suspected it would have little demand and perhaps no longer be made. However, as of 2021-10-09, Mouser stock them for £1.94 in DIP or SOIC packages.