Electronics Today International: The Applix Articles
Pin# | Name | Description |
---|---|---|
1-2 | Com | System common ground. |
3-4 | +5V | +5 V power supply. |
5-6 | +12V | +12 V power supply. |
7-8 | -12V | -12 V power supply. |
9-24 | D0-D15 | Data bus (D0-D15). Bidirectional, three-state data bus. |
25 | Address strobe. This signal indicates that there is valid data on the address bus. | |
26 | Upper data strobe. This signal indicates that valid data is available on data bus bits D8-D15. | |
27 | Lower data strobe. This signal indicates that valid data is available on data bus bits D0-D7. | |
28 | R/ | Read/write. This signal defines the data bus transfer as a read or write cycle. It also works in conjunction with |
29 | Data transfer acknowledge. This pin is used by expansion boards to determine when another board or the main board has responded. | |
30 | External data transfer acknowledge. This open collector signal is used by expansion boards and indicates that the date transfer is completed. When the processor recognizes | |
31 | Bus grant. This output indicates to all other potential bus master devices that the processor will release bus control at the end of the current bus cycle. | |
32 | Bus grant acknowledge. This input indicates that some other device has become the bus master. | |
33 | Bus request. This input is wire ORed with all other devices that could become bus masters. It indicates to the processor that some other device desires to become the bus master. | |
34 | Halt. When this bidirectional line is driven by an external device, it will cause the processor to stop at the end of the current bus cycle. When the processor has been halted using this input, all control signals are inactive and all three-state lines are high impedance. When the processor has stopped executing instructions, such as in a double bus fault condition, the | |
35 | Reset. This bidirectional line acts to reset the processor in response to an external reset signal. An internally generated reset (result of a | |
36 | Valid memory address. This output is used to indicate to M6800 devices that there is a valid address on the address bus and the processor is synchronized to enable (E) signal. | |
37 | E | Enable. This signal is the standard enable signal common to all M6800 devices. The period for this output is ten MC68000 clock periods (six low; four high). |
38 | Valid peripheral address. This signal indicates to expansion boards that the device or region currently being addressed is an M6800 family device. | |
39 | Bus error. This input informs the processor that there is a problem with the cycle currently being executed. | |
40 | Interrupt control ( | |
41 | ||
42 | ||
43 | FC2 | These function code outputs indicate the state and cycle type currently being executed and are valid whenever |
44 | FC1 | |
45 | FC0 | |
46-68 | A23-A1 | Address bus (A23-A1). This 23-bit, unidirectional, three-state bus is capable of addressing eight megawords of data. It provides the address for bus operation during all cycles except interrupts. |
69 | Start up. Power on jump signal for use with expansion cards. | |
70 | External valid peripheral address. This input indicates that the device or region addressed is an M6800 family device and that the data transfer be synchronized with the enable (E) signal. This input also indicates that the processor should use automatic vectoring for an interrupt. | |
71 | External interrupt request. These decoded inputs are used by expansion boards to generate interrupts. The level of the interrupt is determined by the setting of the 'INT LEVEL' straps on the main board. | |
72 | ||
73 | ||
74 | ||
75-76 | +5V | +5 V power supply. |
77-78 | Com | System common ground. |
79 | CLK | Clock. 7.5 MHz system clock. |
80 | 30M | 30 MHz clock. |