; ; Source code reverse engineered from ; page 68-69 of Elektor, March 1986. ; ; Assembles online at https://www.asm80.com/ ; ; 2023-06-11 First draft, hex output matches the byts in the hex dump. ; ; THERE MAY BE SOME ERRORS! ; ; ; .cpu 6502 .if 0 base = $c000 scratch = $cf00 vdu_card = $e150 wibble = $0e00 video_buf = $7000 ; to AFFF .else base = $b000 scratch = $bf00 vdu_card = $e150 wibble = $e100 video_buf = $6000 ; to AFFF .endif .binfrom base .binto end_of_code zp_18 = $0018 var_0100 = $0100 var_0101 = $0101 var_0102 = $0102 var_0103 = $0103 var_0104 = $0104 var_0105 = $0105 var_0106 = $0106 var_0107 = $0107 ; ; ; Some arrays: ; arr_8d0e = $8d0e arr_ad0e = $ad0e ; ; Variables ; var_0069 = $0069 wibble_0d = wibble+$0d wibble_50 = wibble+$50 wibble_51 = wibble+$51 wibble_53 = wibble+$53 wibble_55 = wibble+$55 wibble_58 = wibble+$58 wibble_59 = wibble+$59 wibble_5b = wibble+$5b wibble_64 = wibble+$64 wibble_65 = wibble+$65 wibble_66 = wibble+$66 wibble_67 = wibble+$67 var_35c = base+$35c var_35d = base+$35d var_571 = base+$571 var_572 = base+$572 var_94e = base+$94e var_e9b = base+$e9b var_f0a = base+$f0a var_f80 = base+$f80 var_f81 = base+$f81 var_f82 = base+$f82 var_f83 = base+$f83 var_f84 = base+$f84 arr_f85 = base+$f85 var_f86 = base+$f86 var_f89 = base+$f89 var_f8a = base+$f8a var_f8b = base+$f8b var_f8c = base+$f8c var_f8e = base+$f8e var_f8f = base+$f8f var_f90 = base+$f90 var_f91 = base+$f91 var_f92 = base+$f92 var_f93 = base+$f93 var_f94 = base+$f94 var_f95 = base+$f95 var_f96 = base+$f96 var_f97 = base+$f97 var_f98 = base+$f98 var_f99 = base+$f99 var_f9a = base+$f9a var_f8d = base+$f8d var_f99 = base+$f99 var_f9b = base+$f9b vector_f9c = base+$f9c var_f9e = base+$f9e var_f9f = base+$f9f var_fa0 = base+$fa0 var_fa1 = base+$fa1 var_fa2 = base+$fa2 var_fa3 = base+$fa3 var_fa4 = base+$fa4 var_fa5 = base+$fa5 var_fa6 = base+$fa6 var_fa7 = base+$fa7 ; ; ; vdu_card_reg_0 = vdu_card+0 vdu_card_reg_8 = vdu_card+8 vdu_card_reg_9 = vdu_card+9 ; ; ; ; hardware_wr_IC12 = $e164 hardware_rd_IC13 = $e164 hardware_wr_IC6 = $e165 hardware_wr_IC11 = $e166 var_e167 = $e167 ; magazine article says this is unused ; ; ; var_f5d0 = $f5d0 ; ; Calls to external addresses: ; l_0819 = $0819 l_f71d = $f71d l_f724 = $f724 l_f78f = $f78f .org base jmp lb02e jmp lb45c jmp lb39c lb009 jsr l_f78f cmp #3 bne lb01f lda #$11 jsr lb173 jmp l_0819 lb018 lda $e10d and #2 bne lb020 lb01f rts ; lb020 pla pla jsr l_f724 jmp lb411 lb028 jsr l_f71d jmp lb411 ; lb02e ldx #3 lb030 stx hardware_wr_IC11 stx var_f93 lda #7 sta vdu_card+0 jsr lb08d dex bpl lb030 ; lda #0 sta hardware_wr_IC12 sta var_f91 sta var_f94 sta var_f95 sta var_f98 ldx #3 lb054 sta arr_f85,x dex bpl lb054 stx var_f96 stx video_buf lda #$60 sta var_f99 lb065 lda #0 sta hardware_wr_IC6 sta var_e167 sta var_f92 sta var_f90 lda #$48 sta var_f8e lda #$0f sta var_f97 lda #7 sta vdu_card+0 jsr lb08d jsr lb107 lda #$b sta vdu_card+1 lb08d lda #4 and vdu_card+0 beq lb08d rts ; lb095 lda vdu_card+3 and #$f0 clc bne lb09e sec lb09e ror a lsr a sta var_f83 lsr a clc adc var_f83 sta var_f83 rts ; lb0ac lda vdu_card+3 and #$0f bne lb0b5 lda #$10 lb0b5 asl a asl a asl a sta var_f83 rts ; lb0bc lda #0 sta vdu_card+9 sta vdu_card+8 sta var_f90 lb0c7 jsr lb0ac lda var_f92 clc adc vdu_card+$b cmp var_f83 bcc lb0e2 lb0d6 lda vdu_card+$b sec sbc var_f83 sta vdu_card+$b sec rts ; lb0e2 jsr lb0d6 lda var_f92 beq lb0ef lda var_f83 bne lb0f5 lb0ef lda #0 sec sbc vdu_card+$b lb0f5 clc adc var_f92 lb0f9 sta var_f92 sec lda #0 sbc var_f92 sta hardware_wr_IC6 clc rts ; lb107 jsr lb0ac lda #0 sta var_f92 sta hardware_wr_IC6 sta vdu_card+$9 sta vdu_card+$8 sta var_f90 sec sbc var_f83 sta vdu_card+$b rts ; lb123 jsr lb095 clc adc vdu_card+$9 lda vdu_card+$8 adc #0 cmp #2 rts ; lb132 pha lda vdu_card+$9 pha lda vdu_card+$8 pha lda #1 sta vdu_card+$0 lda var_f93 and #$7f sta hardware_wr_IC11 jsr lb08d lda #$0a sta vdu_card+$0 jsr lb08d pla sta vdu_card+$8 pla sta vdu_card+$9 lda #0 sta vdu_card+$0 jsr lb08d pla sta vdu_card+$0 lda var_f93 sta hardware_wr_IC11 inc var_f90 jmp lb08d lb173 ldy var_f94 beq lb17f cmp #4 bcc lb17f jmp lb50a lb17f cmp #$20 bcc lb197 cmp #$80 bcc lb18a rts ; .byte $ff ;11111111 .byte $ff ;11111111 ; lb18a pha jsr lb123 bcc lb193 jsr lb0bc lb193 pla jmp lb132 lb197 asl a tax lda var_35c,x cmp #$ff php sta vector_f9c lda var_35d,x sta vector_f9c+1 cmp #$ff bne lb1b0 plp bne lb1b1 rts ; lb1b0 plp lb1b1 jmp (vector_f9c) lb1b4 jsr lb095 dec var_f90 lda vdu_card+$9 sec sbc var_f83 sta vdu_card+$9 lda vdu_card+$8 sbc #0 sta vdu_card+$8 bcc lb1cf rts ; lb1cf lda #0 sta vdu_card+$9 sta vdu_card+$8 sta var_f90 pha lb1db pla lda vdu_card+$9 pha clc adc var_f83 sta vdu_card+$9 lda vdu_card+$8 adc #0 sta vdu_card+$8 inc var_f90 jsr lb123 bcc lb1db pla sta vdu_card+$9 dec var_f90 lb1fe: jsr lb0ac clc adc vdu_card+$b sta vdu_card+$b rts ; .byte $ff ;11111111 .byte $ff ;11111111 ; lb20b: jsr lb123 bcc lb213 jsr lb0bc lb213 jsr lb095 clc adc vdu_card+$9 sta vdu_card+$9 lda vdu_card+$8 adc #0 sta vdu_card+$8 inc var_f90 lb228 rts ; lb229 jsr lb0c7 bcc lb238 lda vdu_card+$8 bne lb228 lda vdu_card+$9 bne lb228 lb238 jmp lb2c1 ; lb23b: lda vdu_card+$3 pha jsr lb065 pla sta vdu_card+$3 jmp lb107 ; lb249: lda vdu_card+$8 bne lb256 lda vdu_card+$9 bne lb256 rts ; .byte $ff ;11111111 .byte $ff ;11111111 ; lb256 lda #1 sta vdu_card+$1 jsr lb0ac clc adc vdu_card+$b sta vdu_card+$b lda vdu_card+$8 pha lda vdu_card+$9 pha lda #$ff sec sbc vdu_card+$9 sta vdu_card+$5 lda #1 sbc vdu_card+$8 lsr a ror vdu_card+$5 txa pha lb281 dec vdu_card+$b jsr lb2a1 dec var_f83 bne lb281 lda #0 sta vdu_card+$9 sta vdu_card+$8 sta var_f90 lda #$0b sta vdu_card+$1 pla pla pla tax rts ; lb2a1 tsx lda var_0105,x sta vdu_card+$8 lda var_0104,x sta vdu_card+$9 jsr lb2b9 inc vdu_card+$9 bne lb2b9 inc vdu_card+$8 lb2b9 lda #$10 sta vdu_card+$0 jmp lb08d ; lb2c1 lda vdu_card+$9 pha lda vdu_card+$8 pha lda var_f90 pha lda #0 sta vdu_card+$8 sta vdu_card+$9 jsr lb256 pla sta var_f90 pla sta vdu_card+$8 pla sta vdu_card+$9 rts ; lb2E5: jsr lb0ac lda #5 sta vdu_card+$0 jsr lb08d lda #0 sta var_f90 lda #1 nop nop nop sec sbc var_f83 sbc var_f92 sta vdu_card+$b rts ; lb305: lda vdu_card+$9 pha lda vdu_card+$8 pha lda var_f90 pha jsr lb256 pla sta var_f90 pla sta vdu_card+$8 pla sta vdu_card+$9 rts ; lb321: ldx #0 stx hardware_wr_IC6 stx var_f92 inx stx var_f94 ldx #3 stx vdu_card+$1 rts ; lb333: lda #$11 sta vdu_card+$3 rts ; lb339: lda var_f96 beq lb34f lda #$60 sta var_f99 lda #0 sta var_f98 sta video_buf lb34b sta var_f96 rts ; lb34f lda #$ff bne lb34b lb353: lda #1 sta var_f95 sta var_f94 rts ; ; Jump table ; word_b35c: .word $ffff .word lb4aa .word lb339 .word lb34f .word lb353 .word $ffff .word $ffff .word $ffff .word lb1b4 .word lb20b .word lb229 .word lb1fe .word lb23b .word lb249 .word $ffff .word $ffff .word lb20b .word $ffff .word lb321 .word $ffff .word lb333 .word $ffff .word $ffff .word $ffff .word $ffff .word $ffff .word lb2c1 .word lb0c7 .word lb2e5 .word lb305 .word $ffff .word $ffff CHRINP_routine: lb39c jsr lb4df jsr lb3a5 jmp lb4e9 ; lb3a5 lda var_f94 beq lb3ad jmp lb028 ; lb3ad jsr lb43d lda var_f92 sta var_f8d lda #0 sta var_f8f lda var_f8e bne lb3c3 jmp lb028 ; lb3c3 jsr lb018 lda var_f93 ora #$80 sta hardware_wr_IC11 lb3ce jsr lb018 jsr lb123 bcc lb3de jsr lb0bc bcs lb3de jsr lb256 lb3de jsr lb018 lda #$0a sta vdu_card+$0 inc var_f8f jsr lb08d jsr lb44c jsr lb018 lda var_f8e cmp #$ff bne lb3fc jmp lb028 ; lb3fc sta var_f8b sta var_f8c lb402 jsr lb018 dec var_f8b bne lb402 dec var_f8c bne lb402 beq lb3ce lb411 pha lda var_f94 bne lb43b ror var_f8f bcc lb435 jsr lb123 bcc lb424 jsr lb0bc lb424 lda #$0a sta vdu_card+$0 jsr lb08d jsr lb44c lda var_f8d jsr lb0f9 lb435 lda var_f93 sta hardware_wr_IC11 lb43b pla rts ; lb43d txa pha ldx #3 lb441 lda vdu_card+$8,x sta arr_f85,x dex bpl lb441 bmi lb459 ; lb44c txa pha ldx #3 lb450 lda arr_f85,x sta vdu_card+$8,x dex bpl lb450 lb459 pla tax rts ; lb45c jsr lb4dc jsr lb465 jmp lb4e6 lb465 ldy var_f96 bne lb4a1 cmp #3 bcc lb4a1 ldy var_f94 beq lb47f cpy #$d0 beq lb47f cmp #$20 beq lb4a7 cmp #$0a beq lb4a7 lb47f ldy #0 jsr lb4f0 sta ($18),y tya iny sta ($18),y jsr lb4f0 inc var_f98 bne lb4a1 lda var_f99 clc adc #1 cmp #$af bne lb49e lda #$60 lb49e sta var_f99 lb4a1 jsr lb4e6 lb4a4 jsr lb173 lb4a7 jmp lb009 lb4aa: lda var_f96 beq lb4a7 ldy #0 sty var_f9a lda #$60 sta var_f9b lb4b9 jsr lb4f0 ldy #0 lda ($1a),y jsr lb4f0 beq lb4a7 jsr lb4a4 inc var_f9a bne lb4b9 lda var_f9b clc adc #1 sta var_e9b cmp #$af beq lb4a7 bne lb4b9 ; lb4dc sta var_f80 lb4df sty var_f82 stx var_f81 rts ; lb4e6 lda var_f80 lb4e9 ldy var_f82 ldx var_f81 rts ; lb4f0 pha tya pha ldy #3 lb4f5 lda zp_18,y pha lda var_f98,y sta zp_18,y pla sta var_f98,y dey bpl lb4f5 pla tay pla rts ; lb50a jsr lb51a lda var_f95 beq lb519 lda var_f89 cmp #$0d beq lb538 lb519 rts ; lb51a sta var_f89 cpy #$50 bne lb530 jsr lb643 bcc lb53b cmp #$0d bne lb52f lda #1 sta var_f94 lb52f rts ; lb530 cmp #$11 beq lb538 cmp #$41 bne lb541 lb538 jmp lb66e lb53b sta vdu_card+$0 jmp lb08d lb541 cmp #$20 beq lb52f jsr lb63c bcs lb5a3 jsr lb64a lda var_f89 and #$7f sta var_f94 sec sbc #$42 asl a tax lda var_571,x sta vector_f9c ldy var_572,x sty vector_f9c+1 cpy #$ff bne lb56e cmp #$ff beq lb52f lb56e jmp (vector_f9c) ; .word lb6af .word lb6f5 .word lb791 .word $ffff .word $ffff .word lb9db .word lb694 .word lb6a1 .word lb7ce .word $ffff .word lb71a .word lb873 .word lbab9 .word lb9b0 .word $ffff .word lb72b .word lb886 .word lb8cf .word lb743 .word lb8f1 .word lb918 .word lb760 .word lb944 .word $ffff .word lb773 ; lb5a3 cpy #1 beq lb5c7 tay lda var_f94 bpl lb5c8 and #$7f sta var_f94 cpy #$2b beq lb5c7 cpy #$2d bne lb5c8 lda #2 sec sbc var_f8d asl a tax lda #$80 sta var_f9e,x lb5c7 rts ; lb5c8 cpy #$2c bne lb5d7 ora #$80 sta var_f94 dec var_f8d bmi lb56e rts ; lb5d7 cpy #$0d bne lb5e2 ora #$80 sta var_f94 bne lb56e lb5e2 tya jsr lb633 bcs lb632 and #$0f pha lda #2 sec sbc var_f8d asl a tax lda var_f9e,x pha lda var_f9f,x pha asl var_f9f,x rol var_f9e,x asl var_f9f,x rol var_f9e,x clc pla adc var_f9f,x sta var_f9f,x pla adc var_f9e,x sta var_f9e,x asl var_f9f,x rol var_f9e,x pla php clc adc var_f9f,x sta var_f9f,x lda #0 adc var_f9e,x plp bcc lb62f ora #$80 lb62f sta var_f9e,x lb632 rts ; lb633 cmp #$30 bcc lb63a cmp #$3a rts lb63a sec rts ; lb63c cmp #$41 bcc lb63a cmp #$5b rts ; lb643 cmp #$20 bcc lb63a cmp #$80 rts ; lb64a lda #0 ldy #5 lb64e sta var_f9e,y dey bpl lb64e rts ; lb655 lda var_f94 and #$7f sta var_f94 jsr lb64a lda var_f89 cmp #$2c bne lb66a jmp (vector_f9c) ; lb66a lda #1 bne lb690 lb66e lda #0 sta var_f95 sta var_f94 lda #$0b sta vdu_card+$1 lb67b lda #7 and vdu_card+$b beq lb687 inc vdu_card+$b bne lb67b lb687 rts ; lb688 sta var_f8d lda var_f94 ora #$80 lb690 sta var_f94 rts ; lb694: ldx #3 lb696 lda arr_f85,x sta vdu_card+$8,x dex bpl lb696 bmi lb6ac ; lb6a1: ldx #3 lb6a3 lda vdu_card+$8,x sta arr_f85,x dex bpl lb6a3 lb6ac jmp lb66a ; lb6af: lda var_f94 bmi lb6b9 lda #0 jmp lb688 lb6b9 lda var_fa3 and #$0f pha bit var_fa2 bpl lb6ce and var_f97 asl a asl a asl a asl a ora var_fa3 lb6ce sta var_f91 sta hardware_wr_IC12 lda #2 lb6d6 bit vdu_card+$0 bne lb6d6 lb6db bit vdu_card+$0 beq lb6db lda #$0c sta vdu_card+$0 jsr lb08d pla sta var_f97 lda var_f91 sta hardware_wr_IC12 jmp lb66a ; lb6f5: lda var_f94 bpl lb730 lda var_fa3 and #$0f sta var_fa3 bit var_fa2 bpl lb711 and var_f97 asl a asl a asl a asl a ora var_fa3 lb711 sta var_f91 sta hardware_wr_IC12 jmp lb66a ; lb71a: lda var_f94 bpl lb730 lda var_fa3 and #3 sta var_fa3 lda #$0c bne lb754 lb72b: lda var_f94 bmi lb735 lb730 lda #0 jmp lb688 lb735 lda var_fa3 and #$02 asl a asl a sta var_fa3 lda #7 bne lb754 lb743: lda var_f94 bpl lb730 lda var_fa3 and #1 asl a asl a sta var_fa3 lda #$0b lb754 and vdu_card+$2 ora var_fa3 sta vdu_card+$2 jmp lb66a lb760: lda var_f94 bpl lb730 lda var_fa3 ror a ror a and #$80 sta var_fa3 lda #$7f bne lb782 lb773: lda var_f94 bpl lb730 lda var_fa3 and #3 sta var_fa3 lda #$80 lb782 and var_f93 ora var_fa3 sta hardware_wr_IC11 sta var_f93 jmp lb66a ; lb791: lda var_f94 bpl lb7d3 ldx #0 jsr lb7a3 ldx #2 jsr lb7a3 jmp lb7d8 lb7a3 lda var_fa1,x sec sbc vdu_card+$9,x sta var_fa1,x lda var_fa0,x and #$7f sbc vdu_card+$8,x sta var_fa0,x bcs lb7cd lda #0 sec sbc var_fa1,x sta var_fa1,x lda #0 sbc var_fa0,x ora #$80 sta var_fa0,x lb7cd rts ; lb7ce: lda var_f94 bmi lb7d8 ; lb7d3 lda #1 jmp lb688 ; lb7d8 ldx #3 ; lb7da lda var_fa0,x pha dex bpl lb7da jsr lb7e7 jmp lb655 ; lb7e7 tsx lda #$40 asl var_0105,x rol a asl var_0103,x rol a rol a pha lsr var_0103,x lsr var_0105,x lda var_0104,x sta vdu_card+$5 lda var_0106,x sta vdu_card+$7 lda #1 sta var_0104,x sta var_0106,x ; lb80e ldy var_0103,x bne lb818 ldy var_0105,x beq lb82d ; lb818 lsr var_0103,x ror vdu_card+$5 ror var_0104,x lsr var_0105,x ror vdu_card+$7 ror var_0106,x asl a bne lb80e ; lb82d tay ; lb82e lda var_0103,x clc adc var_0104,x sta var_0103,x php lda var_0105,x clc adc var_0106,x sta var_0105,x lda var_0100,x bcc lb84a ora #$88 ; lb84a plp bcc lb84f ora #$a0 ; lb84f pha pla bpl lb859 sta vdu_card+$0 jsr lb08d ; lb859 lda var_0100,x ora #$10 sta vdu_card+$0 jsr lb08d dey bne lb82e pla pla sta var_0105,x pla sta var_0106,x pla pla rts ; lb873: lda var_f94 bpl lb88b ldx #3 ; lb87a lda var_fa0,x sta vdu_card+$8,x dex bpl lb87a jmp lb66a ; lb886: lda var_f94 bmi lb890 lb88b lda #1 jmp lb688 ; lb890 ldx #0 jsr lb89d ldx #2 jsr lb89d jmp lb66a ; lb89d lda var_fa0,x bmi lb8b6 lda vdu_card+$9,x clc adc var_fa1,x sta vdu_card+$9,x lda vdu_card+$8,x adc var_fa0,x sta vdu_card+$8,x rts ; lb8b6 and #$7f sta var_fa0,x lda vdu_card+$9,x sec sbc var_fa1,x sta vdu_card+$9,x lda vdu_card+$8,x sbc var_fa0,x sta vdu_card+$8,x rts lb8cf: lda var_f94 bmi lb8d9 ; lb8d4 lda #1 jmp lb688 ; lb8d9 lda var_fa3 and #$0f sta var_fa3 lda var_fa1 asl a asl a asl a asl a ora var_fa3 sta vdu_card+$3 jmp lb66a ; lb8f1: lda var_f94 bpl lb8d4 lda var_fa3 and #1 sta var_fa3 lda var_fa1 and #1 asl a ora var_fa3 sta var_fa3 lda vdu_card+$1 and #$fc ora var_fa3 sta vdu_card+$1 jmp lb66a ; lb918: lda var_f94 bpl lb8d4 ldx #3 ; lb91f lda vdu_card+$8,x pha dex bpl lb91f ldx #3 ; lb928 lda var_fa0,x sta vdu_card+$8,x dex bpl lb928 lda #$0f sta vdu_card+$0 jsr lb08d lda hardware_rd_IC13 and #$0f sta var_f8a jmp lba2d ; lb944: lda var_f94 bmi lb952 ; lb949 lda #2 jmp lb688 clc asl $1c1a,x ; lb952 lda var_fa1 sta vdu_card+$5 sta vdu_card+$7 lda var_f9f and #1 sta var_f9f asl var_fa0 rol a tax ldy var_94e,x ldx var_fa3 ; lb96e sty vdu_card+$0 jsr lb08d lda var_f9f beq lb97f jsr lb988 clc bcc lb982 ; lb97f jsr lb99c ; lb982 dex bne lb96e jmp lb655 ; lb988 jsr lb993 lda #$d6 sta vdu_card+$0 jsr lb08d ; lb993 inc vdu_card+$9 bne lb99b inc vdu_card+$8 lb99b rts ; lb99c jsr lb9a7 lda #$d4 sta vdu_card+$0 jsr lb08d lb9a7 inc vdu_card+$b bne lb9af inc vdu_card+$a lb9af rts lb9b0: lda var_f94 lb9b3 bpl lb949 lda var_f9f bne lb9cf lda #$ff sta var_f9f lda var_fa3 beq lb9c6 lb9c4 lda #1 lb9c6 sta var_fa0 jsr lbafd jmp lb66a lb9cf lda var_fa3 cmp var_fa1 bne lb9c4 lda #2 bne lb9c6 lb9db: lda var_f94 bpl lb9b3 ldx #3 lb9e2 lda vdu_card+$8,x pha dex bpl lb9e2 bit var_f9e php lda var_f9f and #1 beq lba3b jsr lba82 jsr lbaa6 jsr lba82 jsr lbaa6 plp bpl lba2d lba03 ldx #0 jsr lba61 beq lba2d bit var_fa0 bmi lba1a inc vdu_card+$9 bne lba27 inc vdu_card+$8 jmp lba27 lba1a dec vdu_card+$9 lda vdu_card+$9 cmp #$ff bne lba27 dec vdu_card+$8 lba27 jsr lbaa6 jmp lba03 lba2d ldx #0 lba2f pla sta vdu_card+$8,x inx cpx #4 bne lba2f jmp lb655 lba3b jsr lba82 jsr lba88 jsr lbaa6 plp bpl lba2d jsr lba82 lba4a ldx #2 jsr lba61 beq lba2d jsr lba88 ldx #0 jsr lba61 beq lba2d jsr lba88 jmp lba4a lba61 jsr lba77 beq lba81 lda var_fa1,x sec sbc #1 sta var_fa1,x lda var_fa0,x sbc #0 sta var_fa0,x lba77 lda var_fa0,x and #$7f bne lba81 lda var_fa1,x lba81 rts lba82 lda #0 pha pha beq lba95 lba88 lda var_fa3 pha lda var_fa2 pha eor #$80 sta var_fa2 lba95 lda var_fa1 pha lda var_fa0 pha eor #$80 sta var_fa0 lbaa2 jsr lb7e7 rts lbaa6 lda var_fa3 pha lda var_fa2 pha eor #$80 sta var_fa2 lda #0 pha pha beq lbaa2 lbab9: lda var_f94 bmi lbac3 lda #2 jmp lb688 lbac3 ldx #3 lbac5 lda vdu_card+$8,x pha lda var_fa0,x sta vdu_card+$8,x dex bpl lbac5 lda var_f9f and #$0f sta var_f9f bit var_f9e bpl lbae9 and var_f97 asl a asl a asl a asl a ora var_f9f lbae9 sta hardware_wr_IC12 lda #$80 sta vdu_card+$0 jsr lb08d lda var_f91 sta hardware_wr_IC12 jmp lba2d lbafd jmp lbc49 lbb00 stx var_f84 tsx lda var_0104,x bcs lbb16 adc var_0106,x tay lda var_0103,x adc var_0105,x inx bne lbb21 lbb16 sbc var_0106,x tay lda var_0103,x sbc var_0105,x inx lbb21 pha lda var_0100,x sta var_0104,x lda var_0101,x sta var_0105,x pla inx inx inx txs ldx var_f84 rts ; ; ; ; lbb39 equ lbb37+2 ; !!! ; called from 4 places lbb40 equ lbb37+9 ; !!! ; called from 4 places ; lbb37 clc ; called from 6 places bit $38 ldx #0 beq lbb43 ; lbb3e clc ; called from 4 places bit $38 ldx #2 ; lbb43 pha lda #0 pha lda var_f86,x pha lda arr_f85,x pha jsr lbb00 sta vdu_card+$8,x tya sta vdu_card+$9,x rts lbb5a inc var_fa6 bne lbb62 inc var_fa7 lbb62 rts lbb63 sty vdu_card+$0 jmp lb08d lbb69 lda #0 ldy var_fa0 cpy #2 bne lbb79 lda var_fa4 sec sbc var_fa5 lbb79 sta vdu_card+$5 lsr a sta vdu_card+$7 lda #1 bit var_f9f beq lbb99 lda var_fa4 jsr lbb37 lda var_fa5 lsr a jsr lbb3e ldy #$16 jsr lbb63 lbb99 lda #2 bit var_f9f beq lbbb2 lda var_fa5 jsr lbb37 lda var_fa4 lsr a jsr lbb3e ldy #$14 jsr lbb63 lbbb2 lda #4 bit var_f9f beq lbbcb lda var_fa5 jsr lbb39 ; !!! lda var_fa4 lsr a jsr lbb3e ldy #$14 jsr lbb63 lbbcb lda #8 bit var_f9f beq lbbe4 lda var_fa4 jsr lbb39 ; !!! lda var_fa5 lsr a jsr lbb3e ldy #$10 jsr lbb63 lbbe4 lda #$10 bit var_f9f beq lbbfd lda var_fa4 jsr lbb39 ; !!! lda var_fa5 lsr a jsr lbb40 ; !!! ldy #$10 jsr lbb63 lbbfd lda #$20 bit var_f9f beq lbc16 lda var_fa5 jsr lbb39 ; !!! lda var_fa4 lsr a jsr lbb40 ; !!! ldy #$12 jsr lbb63 lbc16 lda #$40 bit var_f9f beq lbc2f lda var_fa5 jsr lbb37 lda var_fa4 lsr a jsr lbb40 ; !!! ldy #$12 jsr lbb63 lbc2f lda #$80 bit var_f9f bne lbc37 rts lbc37 lda var_fa4 jsr lbb37 lda var_fa5 lsr a jsr lbb40 ; !!! ldy #$16 jmp lbb63 lbc49 lda var_fa1 sta var_fa4 sta var_fa6 lda #0 sta var_fa5 sta var_fa7 sta hardware_wr_IC6 sta var_f92 ldy var_fa0 beq lbc79 cpy #1 beq lbc76 sec sbc var_fa6 sta var_fa6 dec var_fa7 jmp lbd52 lbc76 jsr lbb69 lbc79 lda var_fa4 asl a pha lda #0 rol a pha lda var_fa6 pha lda var_fa7 pha sec jsr lbb00 sta var_fa7 sty var_fa6 lbc94 ldy var_fa5 lda #2 cmp var_fa0 bne lbca3 clc adc var_fa5 tay lbca3 cpy var_fa4 bcc lbcab jmp lbd58 lbcab lda var_fa0 bne lbcb3 jsr lbb69 lbcb3 lda var_fa6 pha lda var_fa7 pha lda var_fa5 asl a pha lda #0 rol a pha clc jsr lbb00 sta var_fa7 sty var_fa6 jsr lbb5a inc var_fa5 lda var_fa7 bmi lbd05 lda var_fa4 asl a pha lda #0 rol a pha lda var_fa6 pha lda var_fa7 pha sec jsr lbb00 sta var_fa7 sty var_fa6 jsr lbb5a jsr lbb5a lda var_fa4 sec sbc #1 sta var_fa4 bcc lbd58 lbd05 lda var_fa0 beq lbd55 cmp #1 bne lbd52 lda var_fa4 asl a pha lda #0 rol a pha lda var_fa6 pha lda var_fa7 pha sec jsr lbb00 tax tya pha txa pha lda var_fa1 asl a pha lda #0 rol a pha clc jsr lbb00 iny bne lbd3b clc adc #1 lbd3b and #$80 cmp #$80 bne lbd52 sec lda var_fa4 sbc #1 sta var_fa4 bcs lbd4f jsr lbb69 lbd4f inc var_fa4 lbd52 jsr lbb69 lbd55 jmp lbc94 lbd58 lda var_fa0 cmp #1 bne lbd64 lda var_fa3 bne lbd65 lbd64 rts lbd65 dec var_fa3 dec var_fa1 jmp lbc49 end_of_code: .end