J105 STMC
The board base address is selected by IC4, an 8-bit comparator. Jumpers A to H set the comparison address on the top 8 bits of the STE I/O address. Jumpers short to ground, so 'no jumpers gives an address of FF0. Comparison of the top 4 address lines can be disabled which provides a choice of 16 possible locations for the board. Select signals go to IC5, a logic array which decodes chip selects.
These chip selects go to the stepper controller i.e. (IC10), the input I/O buffer (IC12) and the output I/O latch (IC13). IC13 outputs may be jumpered to the limit switch inputs on IC11. Use of this feature is explained in Section 6.
Interrupts from the stepper controller IC may be jumpered to an attention request line on the bus via LK2. The clock for the stepper controller is 4 MHz, derived from a crystal by division in IC7. A step-rate clock of 46.875 kHz is also produced by IC7.
IC10 is a high-current 4-phase bipolar driver which is connected to the stepper motor via PL2. Diodes D1-8 protect the driver from voltage spikes, caused by the back EMF of the motor.