J105 STMC
Note: + = standard jumper configuration, as supplied. * = signal is active-low.
Figure 1. Link Positions
LK1A1 ignore A11 + LK1A2 select if A11 low Figure 2. Link Area 1 LK1B1 ignore A10 + LK1B2 select if A10 low o H o LK1C1 ignore A9 o G o LK1C2 select if A9 low o F o LK1D1 ignore A8 o E o LK1D2 select if A8 low o D2 o D1 o LK1E select if A7 Low o C2 o C1 o + LK1F select if A6 low o B2 o B1 o LK1G select if A5 low o A2 o A1 o LK1H select if A4 low
Standard jumpering as shown above gives an base address of 3B0 - see the 'I/O Map' section.
The board will be selected when a particular combination of address bits and command modifiers is sent to it, with the strobe lines ADRSTB* and DATSTB* active. The command modifiers are those for I/O cycles - CM2 high, CM1 low and CM0 high or low for read or write. The address bits are determined by the jumpering on LK1, which sets what the top eight bits of the address are required to be, and the internal configuration of IC4, which deals with the lower four bits. STEbus I/O accesses use twelve of the twenty address lines.
If any of the jumpers A2,B2,C2,D2,E,F,G,H are inserted, the corresponding comparison address bits (A11 to A4) must be low for the board to be selected, as shown in the table above. For example, consider the base address of the board, which is the address of the data port of IC8 (see the next section for more details). If all these jumpers are inserted, the base address is 0DD.
If one of the above jumpers is removed, the corresponding address bit must be high for the board to be selected. Thus, with no jumpers, the base address is FF0.
If jumpers A1,B1,C1,D1 are inserted, the top 4 bits of the 12-bit address are not used in the comparison, so with these jumpers in, the base address is XF0.
With the standard jumpering as indicated above, the base address is 3B0.
Make one (and only one) of these links if using interrupts:
Figure 3. Link Area 2 LK2H - Interrupt on ATMRQ0* o H o LK2G - Interrupt on ATNRQ1* o G o LK2F - Interrupt on ATNRQ2* o F o LK2E - Interrupt on ATNRQ3* o E o LK2D - Interrupt on ATNRQ4* o D o LK2C - Interrupt on ATNRQ5* o C o LK2B - Interrupt on ATNRQ6* o B o LK2A - Interrupt on ATNRQ7* o A o
Links LK3 and LK4 can connect the output I/O port to the limit switch inputs of the stepper controller IC. See Section 6 for information about using this feature.
Figure 4. Link Areas 3 & 4 LK3 if made will connect bit 4 of the o 3 o output port to the CNP input. LK4D if made connects bit 3 to the L4 input o 4D o LK4C if made connects bit 2 to the L3 input o 4C o LK4B if made connects bit 1 to the L2 input o 4B o LK4A if made connects bit 0 to the L1 input o 4A o
LK5 shorts out the resistor which isolates the motor ground from the computer. This link should be inserted if you wish to run the motor from the same power supply as the computer. Note that this is not recommended, as voltage spikes and current surges from the motor may cause computer malfunction.
The STMC is supplied with LK5 inserted. Remove it when using a separate motor supply.