; DP84412	PAL Boolean Equations (2024-02-03 not verified yet!)

PAL16R6A	;FAST PAL
NEW PAL FOR THE NATIONAL SEMICONDUCTOR NS32016, 32008, 32032 
NATIONAL SEMICONDUCTOR (WORKS UP 10 MHz)

FCLK !TSO RFIO !ADS !DDIN !WAITWR CTTL !CS !WAITRD GND
!OE !CWAIT !4DLY !3DLY !2DLY !MODE !RASIN !CYCLED !INCY VCC

RASIN	:=	INCY * !CYCLED * !MODE * !CTTL * DDIN		; Start !RASIN fast during
								; "READ"  cycle
	+	INCY * !MODE * 2DLY * !WAITWR			; "WRITE" cycle without WAIT states
	+	!CS * INCY * !MODE * 2DLY			; Hidden Refresh !RASIN
	+	 CS * INCY * !MODE * 2DLY * WAITWR * !CTTL	; "WRITE" cycle with WAIT states
	+	RASIN * INCY * !MODE * 2DLY			; continue !RASIN


CYCLED	:=	!MODE * 2DLY * !WAITWR * !DDIN * !CTTL		; No WAITS inserted 
	+	!MODE * 2DLY * !WAITRD *  DDIN * !CTTL		; No WAITS inserted 
	+	!MODE * 2DLY * !4DLY * WAITRD *  DDIN * !CTTL	; WAIT in READ cycle 
	+	!MODE * 2DLY * !4DLY * WAITWR * !DDIN * !CTTL	; WAIT in WRITE cycle
	+	CYCLED * TSO * !MODE
	+	CYCLED *       !MODE * CTTL

MODE	:=	!RFIO * !INCY * !2DLY * !CTTL			; forced refresh during idle 
								; states, in long cycles, 
	+	MODE * !3DLY					; or at the end of a cycle
	+	MODE * !4DLY	
	+	MODE * CTTL	

2DLY	:=	MODE * !4DLY * !CTTL
	+	2DLY *  CTTL
	+	INCY * !CYCLED *! MODE * !3DLY * 4DLY * !CTTL
	+	CS *  DDIN * WAITRD * INCY * !MODE * 2DLY * !3DLY *! 4DLY	; extend 2DLY if
	+	CS * !DDIN * WAITWR * INCY * !MODE * 2DLY * !3DLY *! 4DLY	; WAIT states are wanted

3DLY	:=	2DLY * !4DLY  * !CTTL
	+	3DLY *           CTTL

4DLY	:=	3DLY * !CTTL
	+	4DLY *  CTTL
	+	!INCY * !MODE * !CTTL
	+	 INCY * !MODE * !2DLY *! CTTL

IF (VCC) INCY	=	ADS * !MODE
		+	CS * TSO * !CYCLED * !MODE * !2DLY * 4DLY	; Start INCY for CS 
		+	INCY * !CYCLED				; access after forced 
		+	INCY * 2DLY				; refresh

IF (CS) CWAIT	=	CS * TSO * !CYCLED * !MODE * !2DLY * 4DLY	; for Access during 
								; forced refresh
		+	CS * TSO * MODE				; during forced refresh
		+	CS * INCY * !CYCLED *  DDIN * WAITRD * !MODE * 2DLY * !3DLY * 4DLY	; CS READ  cycle with WAIT states
		+	CS * INCY * !CYCLED * !DDIN * WAITWR * !MODE * 2DLY * !3DLY * 4DLY	; CS WRITE cycle with WAIT states

FIGURE 1. Equations for the Series 32000 Family Interface PAL

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