J058 SCRAM

Section 3. Circuit Description

Memory accesses

The board base address is selected by IC6, a 3 to 8 line decoder, and a link connects one of the outputs to an input of IC7, a custom PAL chip. This chip decodes the CM lines as well, and sends out a trigger to start a timing chain consisting of IC10 and IC11. The correct RAM socket is enabled by another PAL chip, IC8, which also deals with the 8K/2K option. Links from each CS line also go to IC12, an octal 'and' gate, and this indicates to IC7 that the chip being accessed does in fact exist. If it does not, then the board will neither send a DATACK* signal (an asterisk (*) indicates that the signal is active-low) nor alter any RAM location, so that other boards can respond to that location. Assuming that the selected chip does exist, it is accessed, its WR line asserted (during write cycles), and after a wait to allow the chip’s internal lines to stabilise (determined by the timing chain, which runs off the system clock for stability), the !WR line is negated and DATACK* asserted on the bus via TR2.

Clock accesses

The board I/O address is determined by the linking on IC9, an octal comparator, which then signals to IC7. If the CM lines are correct for I/O, IC6 starts the timing chain. The RTC chip used on the Arcom SCRAM has a multiplexed address/data bus, so IC7 transfers address then data either to or from the RTC chip, IC15, asserting DATACK* onto the bus when this operation is complete.

IC18 is a voltage-sensing chip. When the supply voltage is below the working limit, (e.g. during power-up or power-down) it immediately turns off the LEDs in the opto-isolators IC19, 26, 27, 28. This turns off the phototransistors, thus preventing IC8 putting any of the chip selects low. On power-up it keeps the chip selects disabled until the power supply reaches operating voltage and is stable.

This system gives the board a very high degree of protection against data corruption during switch-on and switch-off.