J151 SC88PIO

2. Circuit Description

The 16 MHz clock generated by a 16 MHz oscillator module drives the 80188 Central Processing Unit (CPU) IC10, and optionally the STEbus system clock via LK4. The 8 MHz clock output signal CKOUT from the CPU is halved by IC11, to produce the 4 MHz clock signal CK4 to drive the Serial Communications Controller (SCC) IC16. The SCC drives connector PL3 via RS232 buffers IC12 and 17.

IC5 is a logic array which detects bus accesses and generates wait states, based on the address, the state of the on-board chip selects and the CPU status. IC6 latches the top 4 bits of the CPU address bus and IC9 latches the lowest eight bits. IC11 controls chip-select signals, R0 and R1, for the RAMs (IC20,15) and implements a one-bit port for use as an attention request output to the STEbus.

Two 32 kbyte RAM chips are fitted with the standard SC88PIO board, or two 128 kbyte RAMs if you have purchased the SC88PIO-82 (or if you have updated the SC88PIO board). There is a link which determines which RAMs you are using (LK17). They are backed up by a 3.6V NiCd battery which is trickle charged while the board is powered up. IC14 and IC19 automatically disable the RAM when the supply voltage falls below about 4.5V. If the battery should fail or be removed, an additional standby supply connected to the STEbus VSTBY line can be automatically selected by IC14 and IC19.

The EPROMs (IC13 and 18) can be 8, 16, 32, 64 or 128K each and there is a jumper to set the EPROM size. Address and data lines on the bus are driven by IC1,2,3 and 4, with IC4 driving the strobes. Incoming bus signals are buffered by IC7 and IC8. Reset can either come in from the bus (via LK12A) to reset the CPU, or go to the bus from the on-board reset circuit, in which case a reset switch can be wired between the pins of connector PL2. The 80188's counter/timers can be used either for the bus timeout or user I/O from PL4.

The parallel I/O is done by IC22, and IC24-27. PL4 is divided into four groups.

Group 0 is a simple latched output (write only), and group 1 is a simple latched input (read only).

Group 2 is slightly more sophisticated, as it can be written to and read back. Also, group 2 outputs are open-collector driven. Hence, inputs and outputs can be mixed within the byte group. If you do not want SC88PIO output operations to interfere with input data, then those bits being used as inputs should always have a 1 written to them; their outputs will then be pulled up to 5V by resistor pack RP3.

Group 3 contains the counter/timer outputs from buffer IC23, and some TTL level outputs from the SCC.

Group 4 contains the counter/timer inputs to the CPU via buffer IC23, and some TTL level inputs to the SCC.