J151 SC88PIO

5. I/O Map

The chip-selects for I/O devices are generated by the 80188, and it is vital to set the 80188 up in software as part of the initialisation sequence. If this is not done the board will not function correctly. This section contains information on how to do this, and a summary of the 80188 internal registers. Other examples of using the I/O devices are given in the example program from Appendix D.

There are several types of I/O devices which the 80188 can access.

5.1. I/O boards on the STEbus

The STEbus 4K I/O space is accessed in the lower 32K of the 80188's 64K I/O address space. This selection is automatic, and the programmer should not relocate any of the programmable I/O chip-selects in this space.

5.2. The On-board Serial Communications Controller

The on-board SCC is controlled by two programmable chip-selects. PCS1 is the chip-select which accesses the registers. Accessing PCS2 will assert INTA, the SCC interrupt acknowledge input. This must be done to acknowledge the SCC interrupt generated on INT2 of the 80188, because the 80188 in its most useful interrupt mode does not generate an acknowledge. A read from PCS2 will read the interrupt vector from the SCC and reset the SCC ready for the next interrupt. See Appendix D for an example of how to use the SCC.

5.3. The on-board parallel I/O

The three parallel I/O ports are controlled by PCS4, with further address decoding based on A0 and A1. Once this chip select is set up, the ports are accessed by reading and writing to the appropriate I/O addresses.

5.4. The 80188 on-chip peripherals (counter/timers, DMA etc.)

These integrated peripherals (and the address of PCS1 and PCS2) are controlled by the Internal Control Block. Even the I/O base location of this block of peripherals is controlled by the relocation register within the block. It is recommended that you do not alter this block unless you are sure what you are doing. Two of the on-chip counter/timers can be accessed from connector PL4, if LK15 and LK16 have been set up correctly.

Internal Control Block register map

After a reset, the 256-byte Internal Control Block base address will be at FF00 (hex) in I/O space. The individual control registers reside within the block, at fixed-offsets from the base address. Each register is 16-bits wide, and is read/writable.

Programming the control block requires some knowledge of how an 80188 functions. Detailed information may be found in the Intel 80188 data book. This manual shows some example values for many useful features of the SC88PIO. After reset, the control block registers are at the following addresses, which will be assumed in all further examples.

I/O address Name Control Block register
FF20 to FF3E Interrupt controller
FF50 to FF56 Timer 0 Control
FF58 to FF5E Timer 1 Control
FF60 to FF66 Timer 2 Control
FFA0 UMCS Upper Memory Chip Select
FFA2 LMCS Lower Memory Chip Select
FFA4 ΡΑCS Peripheral Base Address Control
FFA6 MMCS Middle Memory Chip Select
FFA8 MPCS Middle Peripheral Chip Select
FFC0 to FFCA DMA Descriptors Channel 0
FFD0 to FFDA DMA Descriptors Channel 1
FFFE Relocation Register

Two registers directly affect the I/O structure.

The PACS register at FFA4 allows you to relocate the I/O chip selects (bits 15 and 16), and to specify wait-state generation for chip selects PCS0-3 (bits 2-0).

The MPCS register at FFA8 defines features of both memory and I/O. The memory feature bits (bits 14-8) are described in the "Memory Map" section. The I/O features are as follows:

Bit 7: Selects 5 or 7 peripheral chip select lines.
This can be anything, since we only use a maximum of
five peripheral chip select lines
Bit 6: Peripherals in I/O or memory space.
This should be set to zero, for peripherals in I/O space.
Bit 2: Whether external ready is ignored or not for PCS4-6.
This can be either 0 or 1.
Bits 1 & 0: Number of wait states for PCS4-6.
Two is a reasonable value here.

If PACs (at FFA4) is loaded with 0FBE and MPCS (at FFA8) is loaded with 80BE then the Peripheral Chip Select map appears as below. Note that the chip selects are located at the top of on-board I/O space.

I/O address Name Peripheral Chip Select I/O map
F800 PCS0 Not used
F880 PCS1 SCC channel B control
F881 SCC channel A control
F882 SCC channel B data
F883 SCC channel A data
F900 PCS2 Read to generate INTA and fetch vector from
the SCC (the interrupt acknowledge address)
F980 PCS3 Writing a byte with D0 = 1 asserts /ATOUT (low).
This may be jumpered to an ATNRQ line.
Do not read, as D0 will not be predictable.
FA00 PCS4 Write-only output PL4 group 0 (pins 3-10)
FΑ01 Read-only input PL4 group 1 (pins 13-20)
FΑ02 Read-Write I/O PL4 group 2 (pins 23-30)
FA80 PCS5 Not used
FB00 PCS6 Not used