J151 SC88PIO

3. STEbus Interface

The SC88PIO has an STEbus interface (IEEE 1000). Here is a summary of the features of the bus with some notes on their implementation on the SC88PIO board. The pinout of the bus is given in Appendix B.

The SC88PIO can be jumpered either to act as a potential master which requests the bus from the permanent master or separate arbiter, or it can be set up to ignore arbitration. If the SC88PIO is set to ignore arbitration it must be the only master on the bus. If you wish to use more than one master on the bus then you must have one and only one arbiter. A suitable arbiter is available on the SYSCON board. See Links and Options for details of how to set up the board.

Table 1. STEbus Interface on the SC88PIO

Signal In/Out type Description Implementation
A0-19 O 3s 20-bit memory address Buffered from the CPU 20-bit address.
A0-11 O 3s 12-bit I/O address As above.
A0-2 O 3s 3-bit acknowledge address The SC88PIO does not handle bus-vectored interrupts. It responds to bus interrupts on lines ATNRQ0* to ATNRQ3* if appropriately jumpered.
D0-7 I/O 3s 8-bit data bus Driven by the CPU on write cycles, or by the slave on read cycles.
ADRSTB* O 3s Address strobe Addresses, data and command modifiers are valid before the falling edge of ADRSTB* and DATSTB*. Both strobes are active at the same time on the SC88PIO.
DATSTB* O 3s Data strobe On the write cycle, valid data and CM0 are present before this is asserted. On a read cycle, CM0 is high before DATSTB* is asserted to inform the slave that the processor is ready to accept data.
CM2—0 O 3s  

Command modifiers indicating the type of bus cycle, according to the following table.

CM2,1,0
  1 1 1 memory read
  1 1 0   " write
  1 0 1 I/O read
  1 0 0  "  write
  0 1 1 acknowledge
  0 1 0 )
  0 0 1 )reserved
  0 0 0 )

(Note: the acknowledge cycle is NOT generated by the SC88PIO)

BUSRQ0-1* O o/c Bus request Potential (temporary) bus masters request the bus from the arbiter on either of these lines. BUSRQ0* has a higher priority than BUSRQ1*.
The SC88PIO acts as a potential master, and can be jumpered to ignore arbitration as a single permanent master.
BUSAK0-1* I in Bus acknowledge The arbiter acknowledges a request from either of the two potential masters on these lines. A potential master may only drive the bus when it has received an acknowledge on the line corresponding to its request.
DATACK* I o/c Handshake The slave addressed by the master asserts this line to indicate that it has accepted data from a write cycle, or that its data are valid during a read cycle.
TRFERR* I o/c Handshake If data from the slave are wrong (for example from a parity error) the slave asserts this signal instead of DATACK*. The SC88PIO can be jumpered to produce a non-maskable interrupt if this line is asserted.
ATNRQ0-7* I o/c Interrupts Attention request lines.
ATNRQ0-3* are used for interrupts, and ATNRQ0* has the highest priority. ATNRQ5-7* may be jumpered to provide data requests for the on-board DMA channels. ATNRQ1-5* may also be used to signal to other processors.
SYSCLK O tp Clock 16 MHz system clock.
May optionally be generated by the SC88PIO.
SYSRST* I/O o/c Reset System reset. The SC88PIO may either generate this signal or take it from the bus.
Key:	*	= signal is active low
	3s	= tri-state 
	tp	= totem-pole 
	o/c	= open-collector

It is quite easy to use the SC88PIO on the STEbus. You will need a terminated backplane, and one or more slave boards, such as AD converters, for example. In order to comply fully with the specification the impedance of each backplane line should be 60 ohms ±10%. However, a short backplane is not likely to cause any malfunction even if its impedance varies considerably from this. A terminator is necessary because some of the lines are open-collector, and timing is critical on the strobes.

An SC88PIO configured as standard will generate all necessary bus signals. All that is required to generate a bus access is that you try to read from or write to a memory or I/O location which the on-board logic defines as on the bus. See the Memory Map and I/O Devices sections for details on which addresses are on-board and which are not.

Note: The internal timers on the SC88PIO can be programmed so that if the slave board which you are attempting to access does not respond, for example if you used the wrong address, a bus timeout will be generated. This will release the SC88PIO from its wait-state and generate an interrupt. See Section 7. Using the SC88PIO for more details.

If the SC88PIO "hangs" on a bus access, or a bus timeout occurs, check the following:

Are the address and data lines enabled ("HUNG" state)?

If they are not, the SC88PIO has not gained access to the bus. This may be because some other master already has access to the bus and has not released it. Check the state of the BUSRQ* and BUSAK* lines, and links LK1, LK2 and LK8.

If they are, check that DATACK* or TRFERR* has been received.

If DATACK* or TRFERR* have not been received (bus timeout)

Check that the slave board can respond to the bus access which the SC88PIO sent out.

If it can, check that SYSCLK is present on the bus, as many slave boards require this for timing, and check also that SYSCLK is coming from only one source, if you have more than one CPU on the bus.

Check also that your software has allowed bus timeouts to occur, and that it can deal with interrupts from bus timeouts if they happen. It may sometimes be useful to disable bus timeouts and check the bus in the "hung" state if you are confused.