J151 SC88PIO
The 80188 CPU has several programmable chip-select lines, which are asserted when the CPU address falls within the chip select boundaries defined in the CPUs internal chip select registers. Upon reset, the 80188 asserts the Upper Memory-Chip-Select (UMCS) to select EPROM1 (IC13), and jumps to location 0FFFF0H. The first instructions must be to reset the Upper Memory Chip Select register (UMCS) as in the table below, then jump to some code lower down in EPROM. This code can then set up the MMCS and MPCS registers, by which time both EPROMS will be properly selected. An example of this is given at the end of the assembly language program in Appendix D.
If EPROM0 (IC18) is not to be used then it will not be enabled if the MMCS register is left unaccessed. If IC18 is to be used, then using the values in the table below, EPROM0 will occupy memory directly below EPROM1, forming a contiguous block. This also imposes the restriction that EPROM0 and EPROM1 must be the same size.
Because UCS overlaps MCS3, the number of programmable wait states must be identical for UCS and MCS0-3. Two wait-states will be required by slow EPROMs. If STEbus memory overlaps MCS1 and MCS0 then MCS0-3 must accept externally generated wait-states until DATACK" is received from the bus. Both the above conditions are satisfied by the contents of the table below.
The RAM is selected by the Lower Memory Chip-Select (LCS), whose size must be set to 64K (two 32K RAMs) or 256K (two 128K RAMs). Refer to Section 4 Links and Options for more information. Wait-states are not usually required for the fast static RAMs fitted.
If a memory access is made to an address which is within neither UMCS, MCS2 or LCS, the STEbus will be selected automatically. This may result in a bus timeout if no actual memory exists on the bus.
The tables below contain chip select register values for various RAM and EPROM sizes. EPROM1 and EPROM0 must be the same size.
Total EPROM Individual EPROM Register addresses and contents (hex.) capacity type size UMCS MMCS MPCS (FFA0) (FFA6) (FFA8) 16K 2764 8K FE3E F802 8438 32K 27128 16K FC3E F002 8838 64K 27256 32K F83E E002 9038 128K 27512 64K F03E C002 A038 256K 27101 128K E03E 8002 C038
Note that all these EPROMs are 28-pin devices, except for type 27101 which has 32 pins. The EPROM sockets can accept 28-pin or 32-pin devices. The 28 pin devices should be fitted in the lower 28 pins of the socket, furthest away from the edge of the board.
The EPROM pins in the circuit diagram are labelled as for 32-pin devices.
Location (Hex address) |
Contents | ||
---|---|---|---|
00000 | LCS: IC20, RAM 0 (32K) | 128K | 512K |
08000 | LCS: IC15, RAM 1 (32K) | ||
10000 | STEbus accesses | ||
20000 | 128K | ||
30000 | |||
40000 | STEbus accesses | ||
50000 | |||
60000 | |||
70000 | |||
80000 | ROM 0 (256K) | ||
90000 | |||
A0000 | |||
B0000 | |||
C0000 | ROM 0 (128K) | ROM 1 (256K) | |
D0000 | |||
E0000 | MCS2: IC18, ROM 0 (64K)* | ROM 1 (128K) | |
F0000 | UCS: IC13, ROM 1 (64K) |
* STEbus if MCS0-3 disabled.
Example memory map using two 32K RAMs (permanently fitted) and two 32K EPROMS.
The memory blocks of the 80188 processor cannot be mapped at any arbitrary location.
The Upper Memory Chip Select always ends at FFFFF, and only its lower boundary is programmable. EPROM1 should always be present, to contain the initialisation code.
Middle-Memory-Chip-Select lines are all the same size, and must be mapped at a base address which is a multiple of the middle memory block size. Hence, Making UCS and MCS block sizes identical and making the MCS base address four times lower than UCS, is the only way of programming a chip select area to be contiguous with UCS.
MCS0, MCS1, and MCS3 are not used. To ensure they do not interfere with STEbus memory space, set UCS and MCS to include externally generated wait states. Memory accesses to the MCS0 and MCS1 areas wait for the STEbus DATACK* signal.
If EPROM 0 is not used, and MCS0-3 disabled, then STEbus accesses may continue up to the base address of EPROM 1.
LCS is a single select line, which is further decoded into two select lines for the RAM chips. Because these are permanently fitted, the upper boundary should always be set to 10000 hex.