J151 SC88PIO

4. Links and Options

There are many different ways in which you can configure the SC88PIO; they are selected by jumpering across the links on the board. A '+' indicates the standard configuration, a '*' indicates the signal is active low.

The board is described as if you were viewing it from the component side with the 64-way bus connector to the right.

Link Positions

Link summary

This part of the section describes how to set up some commonly used link configurations. The second part describes the links in numerical order.

Installing memory

RAM is already installed underneath the EPROMs.

	Small EPROMs (up to 27256):		LK14A 
	Large EPROMs (27512, 27101):		LK14B

Serial communications

	On PL3 (standard 10-way connector):	LK11B 
	Using RS232 levels:			LK13B

Bus accesses

	SYSCLK out to STEbus:			LK4
	SYSRST* out to STEbus:			LK7
	Ignore arbitration:			LK8A

Compatibility with Concurrent DOS

	Bus time-outs:				LK15A, 15C, 16A
	Interrupts:				LK5B, 6A, 10A

DMA requests: LK9B

Input/Output

	Counter/timers to PL4:			LK15D, 16B

Miscellaneous

	Non-maskable interrupts disabled:	LK3B
	Reset switch from PL2:			LK12B

The following diagrams show the layout of the link areas.

Link areas 1 and 2. Bus Arbitration level

								Link areas 1 and 2.
	LK1A	Bus acknowledges on BUSACK1*
	LK1B	Bus acknowledges on BUSACK0*			o  o 
	LK2A	Bus requests on BUSRQ1*				2Α 1Α
	LK2B	Bus requests on BUSRQ0*				o  o
								2B 1B
								o  o

Notes: If LK8A is made, the state of LK2 and LK1 is irrelevant. However, if LK8B is made, an external arbiter must be used, and the request and acknowledge must be on the same level. This means that if LK2A is made, LK1A must also be made. Alternatively, if LK2Bis made, LK1B must also be made.

Link area 3. Non-Maskable Interrupts (NMIs)

								Link area 3. 

								o
	LK3A	NMI from TRFERR*				A
+	LK3B	NMI disabled					о С о
	LK3C	NMI from ATNRQ0*				B
								o

Link area 4. SYSCLK to STEbus

								Link area 4.

+	SYSCLK driven by this board				o o

Link area 5, 6, 9, and 10. Attention Requests in and out

/ATOUT is the attention request output from the CPU.

					

	LK5A	/ATOUT		to	ATNRQ1*
	LK5B	CPU INT0	from	ATNRQ1*			Link areas 5,6,9 and 10

	LK10B	/ATOUT		to	ATNRQ2*					   LK6
	LK10A	CPU INT1	from	ATNRQ2*			LK9		o B o A o
								    o
	LK6B	/ATOUT		to	ATNRQ3*			    F
	LK6A	CPU INT3	from	ATNRQ3*			o E o D o C o B o A o

	LK9A	/ATOUT		to	ATNRQ5*			o B o A o	o B o A o
	LKB9	CPU DRQ0	from	ATNRQ5*			   LK10		   LK5
	LK9C	CPU DRQ0	from	ATNRQ6*
	LK9D	CPU DRQ1	from	ATNRQ6*
	LK9E	CPU DRQ1	from	ATNRQ6*
	LK9F	CPU DRQ1	from	SCC W/ REQB/

Link LK9F when jumpered, allows the SCC to request DMA transfers from the CPU.

Link area 7. SYSRST* to STEbus

								Link 7.

+	LK7	SYSRST* to bus from this board			o o

The SC88PIO must have only one source of a reset; either from the reset switch or from the bus.

Link area 8. Bus Arbitration. Link area 8.

+	LK8A	Ignore arbitration, bus always granted.
		(for single master systems only)
	LK8B	Accept bus acknowledges from external arbiter

lf LK8A is made, an external arbiter cannot be used, and the SC88PIO must be the only master on the STEbus.

Link area 11. Serial input on channel B

								Link area 11.
	LK11A	Serial input from PL4
+	LK11B	Serial input from PL3				o А о В о

Link area 12. Board reset

								Link area 12.
	LK12A	This board is reset from the STEbus
+	LK12B	This board is reset from a switch across PL2	o А о В о

Link area 13. Serial levels on channel A

								Link area 13.
	LK13A	Serial input is at TTL level
+	LK13B	Serial input is at RS232 levels			o А о В о

Note: You must take care if the A position is used: If RS232 levels are input with LK13A made, the SCC will be destroyed.

Link area 14. EPROM pins

								Link area 14.

+	LK14A	EPROMs pin 1 to 5V (all types except 27512)
	LK14B	EPROMs pin 1 to A15 (27512 only)		o А о В о 

Link areas 15 and 16. CPU Counter/timer I/O

								Link	Link
	LK15D	Timer 0 input from PL4				area	area
+	LK15C	Timer 0 input from /EDD delay			16.	15. 
	LK15B	Not used		 
+	LK15A	Timer 1 output to IC5 pin 2			o	o
								A	D
+	LK16A	Timer 1 input from Timer 0 output		o	o
	LK16B	Timer 1 input from PL4				B	C
								o	o 
									B
									o 
									A
									o

Note: Jumpering links 15A, 15C and 16A as shown above enables the STEbus time-out system if suitable software, such as Concurrent DOS, is used.

Link area 17. RAM Size Select

	LK17A	128K RAMs Fitted 				Link area 17.

+	LK17B	32K RAMs Fitted					o В o А о

Note: LK17 Must always be fitted in either position A or B. Failure to do so will give problems with the RAMs.