{
  "board": {
    "3dviewports": [],
    "design_settings": {
      "defaults": {
        "board_outline_line_width": 0.09999999999999999,
        "copper_line_width": 0.19999999999999998,
        "copper_text_italic": false,
        "copper_text_size_h": 1.5,
        "copper_text_size_v": 1.5,
        "copper_text_thickness": 0.3,
        "copper_text_upright": false,
        "courtyard_line_width": 0.049999999999999996,
        "dimension_precision": 4,
        "dimension_units": 3,
        "dimensions": {
          "arrow_length": 1270000,
          "extension_offset": 500000,
          "keep_text_aligned": true,
          "suppress_zeroes": false,
          "text_position": 0,
          "units_format": 1
        },
        "fab_line_width": 0.09999999999999999,
        "fab_text_italic": false,
        "fab_text_size_h": 1.0,
        "fab_text_size_v": 1.0,
        "fab_text_thickness": 0.15,
        "fab_text_upright": false,
        "other_line_width": 0.15,
        "other_text_italic": false,
        "other_text_size_h": 1.0,
        "other_text_size_v": 1.0,
        "other_text_thickness": 0.15,
        "other_text_upright": false,
        "pads": {
          "drill": 0.89,
          "height": 1.446,
          "width": 1.446
        },
        "silk_line_width": 0.15,
        "silk_text_italic": false,
        "silk_text_size_h": 1.0,
        "silk_text_size_v": 1.0,
        "silk_text_thickness": 0.15,
        "silk_text_upright": false,
        "zones": {
          "45_degree_only": false,
          "min_clearance": 0.09999999999999999
        }
      },
      "diff_pair_dimensions": [
        {
          "gap": 0.0,
          "via_gap": 0.0,
          "width": 0.0
        }
      ],
      "drc_exclusions": [],
      "meta": {
        "version": 2
      },
      "rule_severities": {
        "annular_width": "error",
        "clearance": "error",
        "connection_width": "warning",
        "copper_edge_clearance": "error",
        "copper_sliver": "warning",
        "courtyards_overlap": "error",
        "diff_pair_gap_out_of_range": "error",
        "diff_pair_uncoupled_length_too_long": "error",
        "drill_out_of_range": "error",
        "duplicate_footprints": "warning",
        "extra_footprint": "warning",
        "footprint": "error",
        "footprint_type_mismatch": "error",
        "hole_clearance": "error",
        "hole_near_hole": "error",
        "invalid_outline": "error",
        "isolated_copper": "warning",
        "item_on_disabled_layer": "error",
        "items_not_allowed": "error",
        "length_out_of_range": "error",
        "lib_footprint_issues": "warning",
        "lib_footprint_mismatch": "warning",
        "malformed_courtyard": "error",
        "microvia_drill_out_of_range": "error",
        "missing_courtyard": "ignore",
        "missing_footprint": "warning",
        "net_conflict": "warning",
        "npth_inside_courtyard": "ignore",
        "padstack": "error",
        "pth_inside_courtyard": "ignore",
        "shorting_items": "error",
        "silk_edge_clearance": "warning",
        "silk_over_copper": "warning",
        "silk_overlap": "warning",
        "skew_out_of_range": "error",
        "solder_mask_bridge": "error",
        "starved_thermal": "error",
        "text_height": "warning",
        "text_thickness": "warning",
        "through_hole_pad_without_hole": "error",
        "too_many_vias": "error",
        "track_dangling": "warning",
        "track_width": "error",
        "tracks_crossing": "error",
        "unconnected_items": "error",
        "unresolved_variable": "error",
        "via_dangling": "warning",
        "zones_intersect": "error"
      },
      "rules": {
        "allow_blind_buried_vias": false,
        "allow_microvias": false,
        "max_error": 0.005,
        "min_clearance": 0.09999999999999999,
        "min_connection": 0.0,
        "min_copper_edge_clearance": 0.0,
        "min_hole_clearance": 0.18,
        "min_hole_to_hole": 0.16,
        "min_microvia_diameter": 0.19999999999999998,
        "min_microvia_drill": 0.09999999999999999,
        "min_resolved_spokes": 2,
        "min_silk_clearance": 0.0,
        "min_text_height": 0.7999999999999999,
        "min_text_thickness": 0.08,
        "min_through_hole_diameter": 0.19999999999999998,
        "min_track_width": 0.10149999999999999,
        "min_via_annular_width": 0.049999999999999996,
        "min_via_diameter": 0.3,
        "solder_mask_clearance": 0.0,
        "solder_mask_min_width": 0.0,
        "solder_mask_to_copper_clearance": 0.0,
        "use_height_for_length_calcs": true
      },
      "teardrop_options": [
        {
          "td_allow_use_two_tracks": true,
          "td_curve_segcount": 5,
          "td_on_pad_in_zone": false,
          "td_onpadsmd": true,
          "td_onroundshapesonly": false,
          "td_ontrackend": false,
          "td_onviapad": true
        }
      ],
      "teardrop_parameters": [
        {
          "td_curve_segcount": 0,
          "td_height_ratio": 1.0,
          "td_length_ratio": 0.5,
          "td_maxheight": 2.0,
          "td_maxlen": 1.0,
          "td_target_name": "td_round_shape",
          "td_width_to_size_filter_ratio": 0.9
        },
        {
          "td_curve_segcount": 0,
          "td_height_ratio": 1.0,
          "td_length_ratio": 0.5,
          "td_maxheight": 2.0,
          "td_maxlen": 1.0,
          "td_target_name": "td_rect_shape",
          "td_width_to_size_filter_ratio": 0.9
        },
        {
          "td_curve_segcount": 0,
          "td_height_ratio": 1.0,
          "td_length_ratio": 0.5,
          "td_maxheight": 2.0,
          "td_maxlen": 1.0,
          "td_target_name": "td_track_end",
          "td_width_to_size_filter_ratio": 0.9
        }
      ],
      "track_widths": [
        0.0,
        0.1016,
        0.12,
        0.12319,
        0.126,
        0.143,
        0.16,
        0.1778,
        0.2,
        0.25,
        0.35,
        0.5
      ],
      "via_dimensions": [
        {
          "diameter": 0.0,
          "drill": 0.0
        }
      ],
      "zones_allow_external_fillets": false,
      "zones_use_no_outline": true
    },
    "layer_presets": [],
    "viewports": []
  },
  "boards": [],
  "cvpcb": {
    "equivalence_files": []
  },
  "erc": {
    "erc_exclusions": [],
    "meta": {
      "version": 0
    },
    "pin_map": [
      [
        0,
        0,
        0,
        0,
        0,
        0,
        1,
        0,
        0,
        0,
        0,
        2
      ],
      [
        0,
        2,
        0,
        1,
        0,
        0,
        1,
        0,
        2,
        2,
        2,
        2
      ],
      [
        0,
        0,
        0,
        0,
        0,
        0,
        1,
        0,
        1,
        0,
        1,
        2
      ],
      [
        0,
        1,
        0,
        0,
        0,
        0,
        1,
        1,
        2,
        1,
        1,
        2
      ],
      [
        0,
        0,
        0,
        0,
        0,
        0,
        1,
        0,
        0,
        0,
        0,
        2
      ],
      [
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        2
      ],
      [
        1,
        1,
        1,
        1,
        1,
        0,
        1,
        1,
        1,
        1,
        1,
        2
      ],
      [
        0,
        0,
        0,
        1,
        0,
        0,
        1,
        0,
        0,
        0,
        0,
        2
      ],
      [
        0,
        2,
        1,
        2,
        0,
        0,
        1,
        0,
        2,
        2,
        2,
        2
      ],
      [
        0,
        2,
        0,
        1,
        0,
        0,
        1,
        0,
        2,
        0,
        0,
        2
      ],
      [
        0,
        2,
        1,
        1,
        0,
        0,
        1,
        0,
        2,
        0,
        0,
        2
      ],
      [
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2
      ]
    ],
    "rule_severities": {
      "bus_definition_conflict": "error",
      "bus_entry_needed": "error",
      "bus_to_bus_conflict": "error",
      "bus_to_net_conflict": "error",
      "conflicting_netclasses": "error",
      "different_unit_footprint": "error",
      "different_unit_net": "error",
      "duplicate_reference": "error",
      "duplicate_sheet_names": "error",
      "endpoint_off_grid": "warning",
      "extra_units": "error",
      "global_label_dangling": "warning",
      "hier_label_mismatch": "error",
      "label_dangling": "error",
      "lib_symbol_issues": "warning",
      "missing_bidi_pin": "warning",
      "missing_input_pin": "warning",
      "missing_power_pin": "error",
      "missing_unit": "warning",
      "multiple_net_names": "warning",
      "net_not_bus_member": "warning",
      "no_connect_connected": "warning",
      "no_connect_dangling": "warning",
      "pin_not_connected": "error",
      "pin_not_driven": "error",
      "pin_to_pin": "warning",
      "power_pin_not_driven": "error",
      "similar_labels": "warning",
      "simulation_model_issue": "error",
      "unannotated": "error",
      "unit_value_mismatch": "error",
      "unresolved_variable": "error",
      "wire_dangling": "error"
    }
  },
  "libraries": {
    "pinned_footprint_libs": [],
    "pinned_symbol_libs": []
  },
  "meta": {
    "filename": "Board.kicad_pro",
    "version": 1
  },
  "net_settings": {
    "classes": [
      {
        "bus_width": 12,
        "clearance": 0.1016,
        "diff_pair_gap": 0.1016,
        "diff_pair_via_gap": 0.25,
        "diff_pair_width": 0.1016,
        "line_style": 0,
        "microvia_diameter": 0.3,
        "microvia_drill": 0.1,
        "name": "Default",
        "pcb_color": "rgba(0, 0, 0, 0.000)",
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.16,
        "via_diameter": 0.4,
        "via_drill": 0.2,
        "wire_width": 6
      },
      {
        "bus_width": 12,
        "clearance": 0.1016,
        "diff_pair_gap": 0.1016,
        "diff_pair_via_gap": 0.25,
        "diff_pair_width": 0.1016,
        "line_style": 0,
        "microvia_diameter": 0.3,
        "microvia_drill": 0.1,
        "name": "DDR4",
        "pcb_color": "rgba(0, 0, 0, 0.000)",
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.16,
        "via_diameter": 0.4,
        "via_drill": 0.2,
        "wire_width": 6
      },
      {
        "bus_width": 12,
        "clearance": 0.78,
        "diff_pair_gap": 0.1016,
        "diff_pair_via_gap": 0.25,
        "diff_pair_width": 0.1016,
        "line_style": 0,
        "microvia_diameter": 0.3,
        "microvia_drill": 0.1,
        "name": "DPVia",
        "pcb_color": "rgba(0, 0, 0, 0.000)",
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.16,
        "via_diameter": 0.4,
        "via_drill": 0.2,
        "wire_width": 6
      },
      {
        "bus_width": 12,
        "clearance": 0.1016,
        "diff_pair_gap": 0.1016,
        "diff_pair_via_gap": 0.25,
        "diff_pair_width": 0.1016,
        "line_style": 0,
        "microvia_diameter": 0.3,
        "microvia_drill": 0.1,
        "name": "SDRAM",
        "pcb_color": "rgba(0, 0, 0, 0.000)",
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.16,
        "via_diameter": 0.4,
        "via_drill": 0.2,
        "wire_width": 6
      }
    ],
    "meta": {
      "version": 3
    },
    "net_colors": {
      "/BT-USBN": "rgb(0, 255, 0)",
      "/BT-USBP": "rgb(0, 255, 0)",
      "/EMMC_CLK": "rgb(255, 153, 0)",
      "/EMMC_CMD": "rgb(255, 153, 0)",
      "/EMMC_DAT0": "rgb(255, 153, 0)",
      "/EMMC_DAT1": "rgb(255, 153, 0)",
      "/EMMC_DAT2": "rgb(255, 153, 0)",
      "/EMMC_DAT3": "rgb(255, 153, 0)",
      "/EMMC_DAT4": "rgb(255, 153, 0)",
      "/EMMC_DAT5": "rgb(255, 153, 0)",
      "/EMMC_DAT6": "rgb(255, 153, 0)",
      "/EMMC_DAT7": "rgb(255, 153, 0)",
      "/EMMC_DS": "rgb(255, 153, 0)",
      "/GMAC1_TXCLK_M1": "rgb(255, 153, 0)",
      "/GMAC1_TXD0_M1": "rgb(255, 153, 0)",
      "/GMAC1_TXD1_M1": "rgb(255, 153, 0)",
      "/GMAC1_TXD2_M1": "rgb(255, 153, 0)",
      "/GMAC1_TXD3_M1": "rgb(255, 153, 0)",
      "/GMAC1_TXEN_M1": "rgb(255, 153, 0)",
      "/GMAC_MCLKINOUT_M1": "rgb(255, 153, 0)",
      "/GMAC_MDC": "rgb(255, 153, 0)",
      "/GMAC_MDIO": "rgb(255, 153, 0)",
      "/HDMIR_TX0N": "rgb(194, 194, 194)",
      "/HDMIR_TX0P": "rgb(194, 194, 194)",
      "/HDMIR_TX1N": "rgb(194, 194, 194)",
      "/HDMIR_TX1P": "rgb(194, 194, 194)",
      "/HDMIR_TX2N": "rgb(194, 194, 194)",
      "/HDMIR_TX2P": "rgb(194, 194, 194)",
      "/HDMIR_TXCLK+": "rgb(194, 194, 194)",
      "/HDMIR_TXCLK-": "rgb(194, 194, 194)",
      "/HDMI_TX0N": "rgb(194, 194, 194)",
      "/HDMI_TX0P": "rgb(194, 194, 194)",
      "/HDMI_TX1N": "rgb(194, 194, 194)",
      "/HDMI_TX1P": "rgb(194, 194, 194)",
      "/HDMI_TX2N": "rgb(194, 194, 194)",
      "/HDMI_TX2P": "rgb(194, 194, 194)",
      "/HDMI_TXCLK+": "rgb(194, 194, 194)",
      "/HDMI_TXCLK-": "rgb(194, 194, 194)",
      "/LPDDR4_A0_A": "rgb(72, 72, 0)",
      "/LPDDR4_A0_B": "rgb(72, 72, 0)",
      "/LPDDR4_A1_A": "rgb(72, 72, 0)",
      "/LPDDR4_A1_B": "rgb(72, 72, 0)",
      "/LPDDR4_A2_A": "rgb(72, 72, 0)",
      "/LPDDR4_A2_B": "rgb(72, 72, 0)",
      "/LPDDR4_A3_A": "rgb(72, 72, 0)",
      "/LPDDR4_A3_B": "rgb(72, 72, 0)",
      "/LPDDR4_A4_A": "rgb(72, 72, 0)",
      "/LPDDR4_A4_B": "rgb(72, 72, 0)",
      "/LPDDR4_A5_A": "rgb(72, 72, 0)",
      "/LPDDR4_A5_B": "rgb(72, 72, 0)",
      "/LPDDR4_CKE0A": "rgb(72, 72, 0)",
      "/LPDDR4_CKE0B": "rgb(72, 72, 0)",
      "/LPDDR4_CKE1A": "rgb(72, 72, 0)",
      "/LPDDR4_CKE1B": "rgb(72, 72, 0)",
      "/LPDDR4_CLKA_N": "rgb(0, 255, 0)",
      "/LPDDR4_CLKA_P": "rgb(0, 255, 0)",
      "/LPDDR4_CLKB_N": "rgb(0, 255, 0)",
      "/LPDDR4_CLKB_P": "rgb(0, 255, 0)",
      "/LPDDR4_CS0n_A": "rgb(72, 72, 0)",
      "/LPDDR4_CS0n_B": "rgb(72, 72, 0)",
      "/LPDDR4_CS1n_A": "rgb(72, 72, 0)",
      "/LPDDR4_CS1n_B": "rgb(72, 72, 0)",
      "/LPDDR4_DM0_A": "rgb(72, 72, 0)",
      "/LPDDR4_DM0_B": "rgb(72, 72, 0)",
      "/LPDDR4_DM1_A": "rgb(72, 72, 0)",
      "/LPDDR4_DM1_B": "rgb(72, 72, 0)",
      "/LPDDR4_DQ0_A": "rgb(72, 72, 0)",
      "/LPDDR4_DQ0_B": "rgb(72, 72, 0)",
      "/LPDDR4_DQ10_A": "rgb(72, 72, 0)",
      "/LPDDR4_DQ10_B": "rgb(72, 72, 0)",
      "/LPDDR4_DQ11_A": "rgb(72, 72, 0)",
      "/LPDDR4_DQ11_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ12_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ12_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ13_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ13_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ14_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ14_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ15_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ15_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ1_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ1_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ2_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ2_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ3_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ3_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ4_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ4_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ5_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ5_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ6_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ6_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ7_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ7_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ8_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ8_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQ9_A": "rgb(255, 255, 255)",
      "/LPDDR4_DQ9_B": "rgb(255, 255, 255)",
      "/LPDDR4_DQS0_A+": "rgb(0, 255, 0)",
      "/LPDDR4_DQS0_A-": "rgb(0, 255, 0)",
      "/LPDDR4_DQS0_B+": "rgb(0, 255, 0)",
      "/LPDDR4_DQS0_B-": "rgb(0, 255, 0)",
      "/LPDDR4_DQS1_A+": "rgb(0, 255, 0)",
      "/LPDDR4_DQS1_A-": "rgb(0, 255, 0)",
      "/LPDDR4_DQS1_B+": "rgb(0, 255, 0)",
      "/LPDDR4_DQS1_B-": "rgb(0, 255, 0)",
      "/LPDDR4_ODT0_CA_A": "rgb(255, 255, 255)",
      "/LPDDR4_ODT0_CA_B": "rgb(255, 255, 255)",
      "/LPDDR4_Resetn": "rgb(255, 255, 255)",
      "/MDI0_+": "rgb(194, 194, 194)",
      "/MDI0_-": "rgb(194, 194, 194)",
      "/MDI1_+": "rgb(194, 194, 194)",
      "/MDI1_-": "rgb(194, 194, 194)",
      "/MDI2_+": "rgb(194, 194, 194)",
      "/MDI2_-": "rgb(194, 194, 194)",
      "/MDI3_+": "rgb(194, 194, 194)",
      "/MDI3_-": "rgb(194, 194, 194)",
      "/MIPI_RCN": "rgb(194, 194, 194)",
      "/MIPI_RCP": "rgb(194, 194, 194)",
      "/MIPI_RD1N": "rgb(194, 194, 194)",
      "/MIPI_RD1P": "rgb(194, 194, 194)",
      "/MIPI_RD2N": "rgb(194, 194, 194)",
      "/MIPI_RD2P": "rgb(194, 194, 194)",
      "/MIPI_RD3N": "rgb(194, 194, 194)",
      "/MIPI_RD3P": "rgb(194, 194, 194)",
      "/MIPI_RD4N": "rgb(194, 194, 194)",
      "/MIPI_RD4P": "rgb(194, 194, 194)",
      "/MIPI_TX0_CLKN": "rgb(255, 39, 0)",
      "/MIPI_TX0_CLKP": "rgb(255, 39, 0)",
      "/MIPI_TX0_D0N": "rgb(255, 39, 0)",
      "/MIPI_TX0_D0P": "rgb(255, 39, 0)",
      "/MIPI_TX0_D1N": "rgb(255, 39, 0)",
      "/MIPI_TX0_D1P": "rgb(255, 39, 0)",
      "/MIPI_TX0_D2N": "rgb(255, 39, 0)",
      "/MIPI_TX0_D2P": "rgb(255, 39, 0)",
      "/MIPI_TX0_D3N": "rgb(255, 39, 0)",
      "/MIPI_TX0_D3P": "rgb(255, 39, 0)",
      "/PCIE2_CLKN": "rgb(194, 194, 194)",
      "/PCIE2_CLKP": "rgb(194, 194, 194)",
      "/PCIE2_RXN": "rgb(255, 0, 255)",
      "/PCIE2_RXP": "rgb(255, 0, 255)",
      "/PCIE2_TXN": "rgb(255, 0, 255)",
      "/PCIE2_TXP": "rgb(255, 0, 255)",
      "/PHY_RSTN": "rgb(255, 153, 0)",
      "/PHY_RXC_M1": "rgb(255, 153, 0)",
      "/PHY_RXD0_M1": "rgb(255, 153, 0)",
      "/PHY_RXD1_M1": "rgb(255, 153, 0)",
      "/PHY_RXD2_M1": "rgb(255, 153, 0)",
      "/PHY_RXD3_M1": "rgb(255, 153, 0)",
      "/USB_OTG_D+": "rgb(0, 255, 0)",
      "/USB_OTG_D-": "rgb(0, 255, 0)",
      "Net-(U31-+)": "rgb(0, 255, 0)",
      "unconnected-(U22-CLINK_RESET-Pad42)": "rgb(255, 153, 0)",
      "unconnected-(U22-SUSCLK-Pad50)": "rgb(255, 153, 0)",
      "unconnected-(U22-W_DISABLE2#-Pad54)": "rgb(255, 153, 0)"
    },
    "netclass_assignments": null,
    "netclass_patterns": [
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A0_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A0_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A1_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A1_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A2_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A2_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A3_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A3_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A4_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A4_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A5_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_A5_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_CKE0A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_CKE0B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_CKE1A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_CKE1B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_CS0n_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_CS0n_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_CS1n_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_CS1n_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DM0_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DM0_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DM1_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DM1_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ0_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ0_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ10_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ10_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ11_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ11_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ12_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ12_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ13_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ13_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ14_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ14_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ15_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ15_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ1_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ1_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ2_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ2_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ3_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ3_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ4_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ4_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ5_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ5_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ6_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ6_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ7_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ7_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ8_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ8_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ9_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQ9_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQS0_A+"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQS0_A-"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQS0_B+"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQS0_B-"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQS1_A+"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQS1_A-"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQS1_B+"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_DQS1_B-"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_ODT0_CA_A"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_ODT0_CA_B"
      },
      {
        "netclass": "DDR4",
        "pattern": "/LPDDR4_Resetn"
      }
    ]
  },
  "pcbnew": {
    "last_paths": {
      "gencad": "",
      "idf": "",
      "netlist": "",
      "specctra_dsn": "",
      "step": "Board.step",
      "vrml": ""
    },
    "page_layout_descr_file": ""
  },
  "schematic": {
    "annotate_start_num": 0,
    "drawing": {
      "dashed_lines_dash_length_ratio": 12.0,
      "dashed_lines_gap_length_ratio": 3.0,
      "default_line_thickness": 6.0,
      "default_text_size": 50.0,
      "field_names": [],
      "intersheets_ref_own_page": false,
      "intersheets_ref_prefix": "",
      "intersheets_ref_short": false,
      "intersheets_ref_show": false,
      "intersheets_ref_suffix": "",
      "junction_size_choice": 3,
      "label_size_ratio": 0.375,
      "pin_symbol_size": 25.0,
      "text_offset_ratio": 0.15
    },
    "legacy_lib_dir": "",
    "legacy_lib_list": [],
    "meta": {
      "version": 1
    },
    "net_format_name": "",
    "ngspice": {
      "fix_include_paths": true,
      "fix_passive_vals": false,
      "meta": {
        "version": 0
      },
      "model_mode": 0,
      "workbook_filename": ""
    },
    "page_layout_descr_file": "",
    "plot_directory": "",
    "spice_adjust_passive_values": false,
    "spice_current_sheet_as_root": false,
    "spice_external_command": "spice \"%I\"",
    "spice_model_current_sheet_as_root": true,
    "spice_save_all_currents": false,
    "spice_save_all_voltages": false,
    "subpart_first_id": 65,
    "subpart_id_separator": 0
  },
  "sheets": [
    [
      "09cb2abb-ed97-4c35-8024-f5c000632df4",
      ""
    ]
  ],
  "text_variables": {}
}
