-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II 64-Bit Version 13.0 (Build 232 06/12/2013)
-- Created on Fri Dec 26 00:12:24 2025

Library ieee;
Use ieee.std_logic_1164.ALL;

Entity test_bucket is 
	port
	(
		-- Z8001
		nZ			:	 OUT STD_LOGIC;
		nNMI		:	 OUT STD_LOGIC;
		AS			:	 OUT STD_LOGIC;
		nRESET	:	 OUT STD_LOGIC;
		LS			:	 OUT STD_LOGIC_VECTOR(3 downto 0);

		-- PC
		nPC			:	 OUT STD_LOGIC;
		-- Buffer
		BA				:	 OUT STD_LOGIC_VECTOR(10 downto 0);
		nOE_6116		:	 OUT STD_LOGIC;
		nWE			:	 OUT STD_LOGIC;
		nHOLD			:	 OUT STD_LOGIC;

		-- Glue logic
		nCS_2716		:	 OUT STD_LOGIC;

		-- RAM
		nCS_RAM		:	 OUT STD_LOGIC;
		nMRD			:	 OUT STD_LOGIC;
		nMWR			:	 OUT STD_LOGIC;
		nBHE			:	 OUT STD_LOGIC;
		nBLE			:	 OUT STD_LOGIC;

		-- Z8581
		nADDR2		:	 OUT STD_LOGIC		-- wait state for EPROM
	);
end;

Architecture testbench of test_bucket is

COMPONENT TrumpCard
	PORT
	(
		-- Z8001
		OSC		:	 IN STD_LOGIC;
		ST			:	 IN STD_LOGIC_VECTOR(3 downto 0);
		SN			:	 IN STD_LOGIC_VECTOR(6 downto 0);

		nAS		:	 IN STD_LOGIC;
		LA1		:	 IN STD_LOGIC;
		LA0		:	 IN STD_LOGIC;
		nDS		:	 IN STD_LOGIC;
		RnW		:	 IN STD_LOGIC;
		nMREQ		:	 IN STD_LOGIC;
		BnW		:	 IN STD_LOGIC;

		nZ			:	 OUT STD_LOGIC;
		nNMI		:	 OUT STD_LOGIC;
		AS			:	 OUT STD_LOGIC;
		nRESET	:	 OUT STD_LOGIC;
		LS			:	 OUT STD_LOGIC_VECTOR(3 downto 0);

		-- PC
		RESET_DRV	:	 IN STD_LOGIC;
		A				:	 IN STD_LOGIC_VECTOR(9 downto 1);
		nAEN			:	 IN STD_LOGIC;
		nIOW			:	 IN STD_LOGIC;
		nIOR			:	 IN STD_LOGIC;
		PCD0			:	 IN STD_LOGIC;
		nPC			:	 OUT STD_LOGIC;

		-- Buffer
		BA				:	 OUT STD_LOGIC_VECTOR(10 downto 0);
		nOE_6116		:	 OUT STD_LOGIC;
		nWE			:	 OUT STD_LOGIC;
		nHOLD			:	 OUT STD_LOGIC;

		-- Glue logic
		nCS_2716		:	 OUT STD_LOGIC;

		-- RAM
		nCS_RAM		:	 OUT STD_LOGIC;
		nMRD			:	 OUT STD_LOGIC;
		nMWR			:	 OUT STD_LOGIC;
		nBHE			:	 OUT STD_LOGIC;
		nBLE			:	 OUT STD_LOGIC;

		-- Z8581
		nADDR2		:	 OUT STD_LOGIC		-- wait state for EPROM
	);
END COMPONENT;

		-- Z8001
signal OSC		:	 STD_LOGIC;
signal ST		:	 STD_LOGIC_VECTOR(3 downto 0);
signal SN		:	 STD_LOGIC_VECTOR(6 downto 0);

signal nAS		:	 STD_LOGIC;
signal LA1		:	 STD_LOGIC;
signal LA0		:	 STD_LOGIC;
signal nDS		:	 STD_LOGIC;
signal RnW		:	 STD_LOGIC;
signal nMREQ	:	 STD_LOGIC;
signal BnW		:	 STD_LOGIC;

		-- PC
signal RESET_DRV	:	 STD_LOGIC := 1;
signal A				:	 STD_LOGIC_VECTOR(9 downto 1);
signal nAEN			:	 STD_LOGIC;
signal nIOW			:	 STD_LOGIC;
signal nIOR			:	 STD_LOGIC;
signal PCD0			:	 STD_LOGIC;

For U1:TrumpCard Use Entity work.TrumpCard(rtl);
begin
	U1:TrumpCard port map(
		-- Z8001
		OSC,ST,SN,nAS,LA1,LA0,nDS,RnW,nMREQ,BnW,
		nZ,nNMI,AS,nRESET,LS,
		-- PC
		RESET_DRV,A,nAEN,nIOW,nIOR,PCD0,
		nPC,BA,nOE_6116,nWE,nHOLD,

		-- Glue logic
		nCS_2716,nCS_RAM,nMRD,nMWR,nBHE,nBLE,nADDR2)

	-- 20MHz
	OSC <= not OSC after 50 ns;
	RESET_DRV <= 0 after 125 ns;
	

	--process
	--begin
	--end process;
end;
