-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM		"Quartus II 64-Bit"
-- VERSION		"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
-- CREATED		"Fri Dec 26 01:31:16 2025"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY TrumpCard IS 
	PORT
	(
		OSC :  IN  STD_LOGIC;
		A9 :  IN  STD_LOGIC;
		A8 :  IN  STD_LOGIC;
		A7 :  IN  STD_LOGIC;
		A6 :  IN  STD_LOGIC;
		A5 :  IN  STD_LOGIC;
		nAEN :  IN  STD_LOGIC;
		A3 :  IN  STD_LOGIC;
		A4 :  IN  STD_LOGIC;
		nIOW :  IN  STD_LOGIC;
		nIOR :  IN  STD_LOGIC;
		PCD0 :  IN  STD_LOGIC;
		ST0 :  IN  STD_LOGIC;
		ST1 :  IN  STD_LOGIC;
		ST2 :  IN  STD_LOGIC;
		ST3 :  IN  STD_LOGIC;
		nAS :  IN  STD_LOGIC;
		A2 :  IN  STD_LOGIC;
		RESET_DRV :  IN  STD_LOGIC;
		LA1 :  IN  STD_LOGIC;
		nDS :  IN  STD_LOGIC;
		RnW :  IN  STD_LOGIC;
		SN0 :  IN  STD_LOGIC;
		SN1 :  IN  STD_LOGIC;
		SN2 :  IN  STD_LOGIC;
		SN3 :  IN  STD_LOGIC;
		SN4 :  IN  STD_LOGIC;
		SN5 :  IN  STD_LOGIC;
		SN6 :  IN  STD_LOGIC;
		nMREQ :  IN  STD_LOGIC;
		BnW :  IN  STD_LOGIC;
		LA0 :  IN  STD_LOGIC;
		A1 :  IN  STD_LOGIC;
		nZ :  OUT  STD_LOGIC;
		nHOLD :  OUT  STD_LOGIC;
		nOE_6116 :  OUT  STD_LOGIC;
		nNMI :  OUT  STD_LOGIC;
		AS :  OUT  STD_LOGIC;
		nRESET :  OUT  STD_LOGIC;
		nWE :  OUT  STD_LOGIC;
		BA0 :  OUT  STD_LOGIC;
		BA1 :  OUT  STD_LOGIC;
		BA2 :  OUT  STD_LOGIC;
		BA3 :  OUT  STD_LOGIC;
		BA4 :  OUT  STD_LOGIC;
		BA5 :  OUT  STD_LOGIC;
		BA6 :  OUT  STD_LOGIC;
		BA7 :  OUT  STD_LOGIC;
		BA8 :  OUT  STD_LOGIC;
		BA9 :  OUT  STD_LOGIC;
		BA10 :  OUT  STD_LOGIC;
		LS0 :  OUT  STD_LOGIC;
		LS1 :  OUT  STD_LOGIC;
		LS2 :  OUT  STD_LOGIC;
		LS3 :  OUT  STD_LOGIC;
		nCS_2716 :  OUT  STD_LOGIC;
		nCS_RAM :  OUT  STD_LOGIC;
		nMRD :  OUT  STD_LOGIC;
		nMWR :  OUT  STD_LOGIC;
		nBHE :  OUT  STD_LOGIC;
		nBLE :  OUT  STD_LOGIC;
		nADDR2 :  OUT  STD_LOGIC;
		nPC :  OUT  STD_LOGIC
	);
END TrumpCard;

ARCHITECTURE bdf_type OF TrumpCard IS 

ATTRIBUTE black_box : BOOLEAN;
ATTRIBUTE noopt : BOOLEAN;

COMPONENT SN74133_4
	PORT(p13 : IN STD_LOGIC;
		 p12 : IN STD_LOGIC;
		 p11 : IN STD_LOGIC;
		 p10 : IN STD_LOGIC;
		 p9 : IN STD_LOGIC;
		 p7 : IN STD_LOGIC;
		 p8 : IN STD_LOGIC;
		 p6 : IN STD_LOGIC;
		 p2 : IN STD_LOGIC;
		 p3 : IN STD_LOGIC;
		 p14 : IN STD_LOGIC;
		 p5 : IN STD_LOGIC;
		 p4 : IN STD_LOGIC;
		 p1 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF SN\74133_4: COMPONENT IS true;
ATTRIBUTE noopt OF SN\74133_4: COMPONENT IS true;

COMPONENT SN74138_3
	PORT(A : IN STD_LOGIC;
		 B : IN STD_LOGIC;
		 G1 : IN STD_LOGIC;
		 C : IN STD_LOGIC;
		 G2AN : IN STD_LOGIC;
		 G2BN : IN STD_LOGIC;
		 Y2N : OUT STD_LOGIC;
		 Y5N : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF SN74138_3: COMPONENT IS true;
ATTRIBUTE noopt OF SN74138_3: COMPONENT IS true;

COMPONENT SN74373_0
	PORT(D1 : IN STD_LOGIC;
		 D3 : IN STD_LOGIC;
		 D6 : IN STD_LOGIC;
		 D7 : IN STD_LOGIC;
		 D2 : IN STD_LOGIC;
		 G : IN STD_LOGIC;
		 D4 : IN STD_LOGIC;
		 D5 : IN STD_LOGIC;
		 D8 : IN STD_LOGIC;
		 OEN : IN STD_LOGIC;
		 Q3 : OUT STD_LOGIC;
		 Q2 : OUT STD_LOGIC;
		 Q4 : OUT STD_LOGIC;
		 Q5 : OUT STD_LOGIC;
		 Q1 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF SN74373_0: COMPONENT IS true;
ATTRIBUTE noopt OF SN74373_0: COMPONENT IS true;

COMPONENT SN74393m_1
	PORT(CLR : IN STD_LOGIC;
		 CKA : IN STD_LOGIC;
		 QC : OUT STD_LOGIC;
		 QD : OUT STD_LOGIC;
		 QB : OUT STD_LOGIC;
		 QA : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF SN74393m_1: COMPONENT IS true;
ATTRIBUTE noopt OF SN74393m_1: COMPONENT IS true;

COMPONENT SN74393m_2
	PORT(CLR : IN STD_LOGIC;
		 CKA : IN STD_LOGIC;
		 QC : OUT STD_LOGIC;
		 QD : OUT STD_LOGIC;
		 QB : OUT STD_LOGIC;
		 QA : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF SN74393m_2: COMPONENT IS true;
ATTRIBUTE noopt OF SN74393m_2: COMPONENT IS true;

SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_90 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_91 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_92 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_93 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_94 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_95 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_96 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_97 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_98 :  STD_LOGIC;
SIGNAL	DFF_inst3 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_99 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_18 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_19 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_20 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_21 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_22 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_29 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_30 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_100 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_33 :  STD_LOGIC;
SIGNAL	DFF_inst12 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_101 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_38 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_102 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_103 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_43 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_44 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_104 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_46 :  STD_LOGIC;
SIGNAL	DFF_inst19 :  STD_LOGIC;
SIGNAL	DFF_inst8 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_50 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_51 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_52 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_53 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_54 :  STD_LOGIC;
SIGNAL	DFF_inst25 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_105 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_57 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_58 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_59 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_106 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_107 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_67 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_108 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_73 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_109 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_76 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_110 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_80 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_81 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_82 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_84 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_86 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_111 :  STD_LOGIC;


BEGIN 
BA8 <= '0';
BA9 <= '0';
BA10 <= '0';
nZ <= SYNTHESIZED_WIRE_21;
nHOLD <= SYNTHESIZED_WIRE_106;
nNMI <= SYNTHESIZED_WIRE_54;
AS <= SYNTHESIZED_WIRE_14;
nRESET <= SYNTHESIZED_WIRE_20;
BA3 <= SYNTHESIZED_WIRE_67;
nPC <= SYNTHESIZED_WIRE_50;
SYNTHESIZED_WIRE_0 <= '1';
SYNTHESIZED_WIRE_2 <= '1';
SYNTHESIZED_WIRE_98 <= '0';
SYNTHESIZED_WIRE_38 <= '0';
SYNTHESIZED_WIRE_57 <= '1';
SYNTHESIZED_WIRE_59 <= '0';
SYNTHESIZED_WIRE_110 <= '1';
SYNTHESIZED_WIRE_84 <= '1';
SYNTHESIZED_WIRE_86 <= '0';




PROCESS(OSC,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_2)
BEGIN
IF (SYNTHESIZED_WIRE_0 = '0') THEN
	SYNTHESIZED_WIRE_104 <= '0';
ELSIF (SYNTHESIZED_WIRE_2 = '0') THEN
	SYNTHESIZED_WIRE_104 <= '1';
ELSIF (RISING_EDGE(OSC)) THEN
	SYNTHESIZED_WIRE_104 <= SYNTHESIZED_WIRE_90;
END IF;
END PROCESS;



SYNTHESIZED_WIRE_82 <= NOT(A4);



SYNTHESIZED_WIRE_81 <= NOT(nAEN);



SYNTHESIZED_WIRE_80 <= NOT(nIOR AND nIOW);


SYNTHESIZED_WIRE_11 <= SYNTHESIZED_WIRE_91 AND SYNTHESIZED_WIRE_92 AND LA1;


SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_93 AND SYNTHESIZED_WIRE_94 AND SYNTHESIZED_WIRE_95;


SYNTHESIZED_WIRE_106 <= SYNTHESIZED_WIRE_96 AND SYNTHESIZED_WIRE_97;


SYNTHESIZED_WIRE_14 <= NOT(nAS);



SYNTHESIZED_WIRE_100 <= NOT(SYNTHESIZED_WIRE_10 OR SYNTHESIZED_WIRE_11);


nWE <= NOT(SYNTHESIZED_WIRE_12 OR SYNTHESIZED_WIRE_13);


b2v_inst109 : SN74373_0
PORT MAP(D1 => SN0,
		 D3 => SN2,
		 D6 => SN5,
		 D7 => SN6,
		 D2 => SN1,
		 G => SYNTHESIZED_WIRE_14,
		 D4 => SN3,
		 D5 => SN4,
		 D8 => SYNTHESIZED_WIRE_98,
		 OEN => SYNTHESIZED_WIRE_98,
		 Q3 => LS2,
		 Q2 => LS1,
		 Q4 => LS3,
		 Q5 => SYNTHESIZED_WIRE_105,
		 Q1 => LS0);


SYNTHESIZED_WIRE_33 <= NOT(DFF_inst3);



SYNTHESIZED_WIRE_18 <= NOT(A2 OR SYNTHESIZED_WIRE_99);


SYNTHESIZED_WIRE_20 <= NOT(RESET_DRV OR SYNTHESIZED_WIRE_18);


SYNTHESIZED_WIRE_51 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20;


SYNTHESIZED_WIRE_91 <= NOT(nDS OR SYNTHESIZED_WIRE_21);


SYNTHESIZED_WIRE_44 <= SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_91;


SYNTHESIZED_WIRE_43 <= SYNTHESIZED_WIRE_95 AND SYNTHESIZED_WIRE_93;


SYNTHESIZED_WIRE_30 <= SYNTHESIZED_WIRE_91 AND RnW;


SYNTHESIZED_WIRE_29 <= SYNTHESIZED_WIRE_93 AND nIOW;


SYNTHESIZED_WIRE_53 <= NOT(SYNTHESIZED_WIRE_95 OR PCD0);


nOE_6116 <= NOT(SYNTHESIZED_WIRE_29 OR SYNTHESIZED_WIRE_30);


PROCESS(SYNTHESIZED_WIRE_90,SYNTHESIZED_WIRE_100,SYNTHESIZED_WIRE_97)
BEGIN
IF (SYNTHESIZED_WIRE_100 = '0') THEN
	DFF_inst12 <= '0';
ELSIF (SYNTHESIZED_WIRE_97 = '0') THEN
	DFF_inst12 <= '1';
ELSIF (RISING_EDGE(SYNTHESIZED_WIRE_90)) THEN
	DFF_inst12 <= SYNTHESIZED_WIRE_33;
END IF;
END PROCESS;


SYNTHESIZED_WIRE_97 <= NOT(DFF_inst12);



SYNTHESIZED_WIRE_109 <= NOT(nDS);



SYNTHESIZED_WIRE_12 <= SYNTHESIZED_WIRE_93 AND SYNTHESIZED_WIRE_101 AND SYNTHESIZED_WIRE_94;


nADDR2 <= NOT(SYNTHESIZED_WIRE_38 OR SYNTHESIZED_WIRE_102);



SYNTHESIZED_WIRE_21 <= SYNTHESIZED_WIRE_103 OR SYNTHESIZED_WIRE_97;


SYNTHESIZED_WIRE_52 <= SYNTHESIZED_WIRE_99 OR nIOW;


SYNTHESIZED_WIRE_94 <= NOT(nIOW);



SYNTHESIZED_WIRE_101 <= SYNTHESIZED_WIRE_43 OR SYNTHESIZED_WIRE_44;


PROCESS(SYNTHESIZED_WIRE_104,SYNTHESIZED_WIRE_100,SYNTHESIZED_WIRE_96)
BEGIN
IF (SYNTHESIZED_WIRE_100 = '0') THEN
	DFF_inst19 <= '0';
ELSIF (SYNTHESIZED_WIRE_96 = '0') THEN
	DFF_inst19 <= '1';
ELSIF (RISING_EDGE(SYNTHESIZED_WIRE_104)) THEN
	DFF_inst19 <= SYNTHESIZED_WIRE_46;
END IF;
END PROCESS;


SYNTHESIZED_WIRE_90 <= NOT(SYNTHESIZED_WIRE_104);



SYNTHESIZED_WIRE_96 <= NOT(DFF_inst19);




SYNTHESIZED_WIRE_46 <= NOT(DFF_inst8);




SYNTHESIZED_WIRE_50 <= SYNTHESIZED_WIRE_99 OR SYNTHESIZED_WIRE_96;


SYNTHESIZED_WIRE_22 <= NOT(LA1);



SYNTHESIZED_WIRE_93 <= NOT(SYNTHESIZED_WIRE_50);



PROCESS(SYNTHESIZED_WIRE_52,SYNTHESIZED_WIRE_51,SYNTHESIZED_WIRE_54)
BEGIN
IF (SYNTHESIZED_WIRE_51 = '0') THEN
	DFF_inst25 <= '0';
ELSIF (SYNTHESIZED_WIRE_54 = '0') THEN
	DFF_inst25 <= '1';
ELSIF (RISING_EDGE(SYNTHESIZED_WIRE_52)) THEN
	DFF_inst25 <= SYNTHESIZED_WIRE_53;
END IF;
END PROCESS;


SYNTHESIZED_WIRE_54 <= NOT(DFF_inst25);



SYNTHESIZED_WIRE_95 <= NOT(A1);



SYNTHESIZED_WIRE_107 <= NOT(SYNTHESIZED_WIRE_100);



SYNTHESIZED_WIRE_102 <= NOT(SYNTHESIZED_WIRE_105);



PROCESS(SYNTHESIZED_WIRE_58,SYNTHESIZED_WIRE_57,SYNTHESIZED_WIRE_106)
BEGIN
IF (SYNTHESIZED_WIRE_57 = '0') THEN
	DFF_inst3 <= '0';
ELSIF (SYNTHESIZED_WIRE_106 = '0') THEN
	DFF_inst3 <= '1';
ELSIF (RISING_EDGE(SYNTHESIZED_WIRE_58)) THEN
	DFF_inst3 <= SYNTHESIZED_WIRE_59;
END IF;
END PROCESS;


SYNTHESIZED_WIRE_73 <= NOT(RnW);



SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_92 AND SYNTHESIZED_WIRE_101 AND SYNTHESIZED_WIRE_91;


SYNTHESIZED_WIRE_108 <= NOT(nMREQ);



SYNTHESIZED_WIRE_76 <= NOT(LA0);



SYNTHESIZED_WIRE_92 <= NOT(RnW OR nDS);


b2v_inst35 : SN74393m_1
PORT MAP(CLR => SYNTHESIZED_WIRE_107,
		 CKA => SYNTHESIZED_WIRE_101,
		 QC => BA2,
		 QD => SYNTHESIZED_WIRE_67,
		 QB => BA1,
		 QA => BA0);


b2v_inst36 : SN74393m_2
PORT MAP(CLR => SYNTHESIZED_WIRE_107,
		 CKA => SYNTHESIZED_WIRE_67,
		 QC => BA6,
		 QD => BA7,
		 QB => BA5,
		 QA => BA4);




SYNTHESIZED_WIRE_58 <= NOT(SYNTHESIZED_WIRE_103);



nCS_2716 <= NOT(SYNTHESIZED_WIRE_102 AND SYNTHESIZED_WIRE_108);


nCS_RAM <= NOT(SYNTHESIZED_WIRE_105 AND SYNTHESIZED_WIRE_108);


nMWR <= NOT(SYNTHESIZED_WIRE_73 AND SYNTHESIZED_WIRE_109);


nMRD <= NOT(RnW AND SYNTHESIZED_WIRE_109);


nBHE <= BnW AND LA0;


nBLE <= BnW AND SYNTHESIZED_WIRE_76;


b2v_inst5 : SN74138_3
PORT MAP(A => ST0,
		 B => ST1,
		 G1 => nAS,
		 C => ST2,
		 G2AN => ST3,
		 G2BN => ST3,
		 Y2N => SYNTHESIZED_WIRE_103,
		 Y5N => SYNTHESIZED_WIRE_19);



b2v_inst51 : SN74133_4
PORT MAP(p13 => SYNTHESIZED_WIRE_110,
		 p12 => SYNTHESIZED_WIRE_110,
		 p11 => SYNTHESIZED_WIRE_110,
		 p10 => SYNTHESIZED_WIRE_80,
		 p9 => SYNTHESIZED_WIRE_81,
		 p7 => SYNTHESIZED_WIRE_82,
		 p8 => A3,
		 p6 => A5,
		 p2 => A9,
		 p3 => A8,
		 p14 => SYNTHESIZED_WIRE_110,
		 p5 => A6,
		 p4 => A7,
		 p1 => SYNTHESIZED_WIRE_99);



PROCESS(SYNTHESIZED_WIRE_99,SYNTHESIZED_WIRE_84,SYNTHESIZED_WIRE_106)
BEGIN
IF (SYNTHESIZED_WIRE_84 = '0') THEN
	DFF_inst8 <= '0';
ELSIF (SYNTHESIZED_WIRE_106 = '0') THEN
	DFF_inst8 <= '1';
ELSIF (RISING_EDGE(SYNTHESIZED_WIRE_99)) THEN
	DFF_inst8 <= SYNTHESIZED_WIRE_86;
END IF;
END PROCESS;



END bdf_type;