-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM		"Quartus II 64-Bit"
-- VERSION		"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
-- CREATED		"Fri Dec 26 01:31:16 2025"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY altera;
USE altera.maxplus2.all; 

LIBRARY work;

ENTITY 74133_4 IS 
PORT 
( 
	13	:	IN	 STD_LOGIC;
	12	:	IN	 STD_LOGIC;
	11	:	IN	 STD_LOGIC;
	10	:	IN	 STD_LOGIC;
	9	:	IN	 STD_LOGIC;
	7	:	IN	 STD_LOGIC;
	8	:	IN	 STD_LOGIC;
	6	:	IN	 STD_LOGIC;
	2	:	IN	 STD_LOGIC;
	3	:	IN	 STD_LOGIC;
	14	:	IN	 STD_LOGIC;
	5	:	IN	 STD_LOGIC;
	4	:	IN	 STD_LOGIC;
	1	:	OUT	 STD_LOGIC
); 
END 74133_4;

ARCHITECTURE bdf_type OF 74133_4 IS 
BEGIN 

-- instantiate macrofunction 

b2v_inst51 : 74133
PORT MAP(13 => 13,
		 12 => 12,
		 11 => 11,
		 10 => 10,
		 9 => 9,
		 7 => 7,
		 8 => 8,
		 6 => 6,
		 2 => 2,
		 3 => 3,
		 14 => 14,
		 5 => 5,
		 4 => 4,
		 1 => 1);

END bdf_type; 