; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063)
; Copyright (c) National Semiconductor Corporation 1990-1993
; Disassembled from J138_U4.jed. Date: 4-13-126
;
; 2026-04-13 First draft
;

chip J138_U4 PAL16R4

SYSCLK		= 1	; 16 MHz
IO_ADDR		= 2	; AN LS30 indicates most address lines are low
A11		= 3	; must go low
AEN		= 4	; indicates whether this is an STEbus access or a PC DMA access.
			; AEN looks like the DMA controller's equivalent of DATSTB
CM0		= 5	; Read/Write
CM1		= 6	; mem/io
/DATSTB		= 7	; From STEbus via schmitt trigger buffer
TIMEOUT		= 8	; from PC DMA cable
CM2		= 9	; must be high to respond
GND		= 10
/OE		= 11	; tied low on PCB
/DATACK		= 12	; Drives STEbus directly

/CS_FE1200	= 13

/state_pin_14	= 14
/state_pin_15	= 15
/state_pin_16	= 16
/state_pin_17	= 17

/IOW		= 18
/IOR		= 19
VCC		= 20 

; intermediates:

STE_mem		equ	CM2 *  CM1
STE_mem_rd	equ	STE_mem	*  CM0
STE_mem_wr	equ	STE_mem	* /CM0

STE_io		equ	CM2 * /CM1
STE_io_rd	equ	STE_io *  CM0
STE_io_wr	equ	STE_io * /CM0

selecting_FE1200	equ	CM2 * /CM1 * DATSTB * CS_FE1200

STE_io_FE1200		equ	STE_io * selecting_FE1200

equations
;
; Generate select, read and write strobes for the FE2100
;
CS_FE1200 	=  /IO_ADDR * /A11 * /AEN *  DATSTB
;
IOR 		= /AEN * STE_io_rd  *  DATSTB
		+  AEN * STE_mem_wr *  state_pin_16 *  state_pin_15 * /state_pin_14
		+  IOR * STE_mem_wr *  AEN
;
; IOW released when /DATACk goes high, which is sooner than DATSTB being released.
;
IOW 		=  /AEN * STE_io_wr *  DATSTB * /DATACK
		+   AEN * STE_io_rd * /TIMEOUT
;
; I don't know how the state machine works, but here it is.
; I suspect they all go zero in the idle state,
; then 14 changes on a valid cycle:
;

state_pin_14	:= /AEN *  selecting_FE1200  * /state_pin_14
		+   AEN *  STE_mem_wr        * /state_pin_14
;
; then pin 15 changes if pin 14 has gone high
;
state_pin_15	:= /AEN *  selecting_FE1200  * /state_pin_15 *  state_pin_14
		+  /AEN *  selecting_FE1200  *  state_pin_15 * /state_pin_14	; hold 
		+   AEN *  STE_mem_wr        * /state_pin_15 *  state_pin_14
		+   AEN *  STE_mem_wr        *  state_pin_15 * /state_pin_14	; hold 
;
; then pin 16 changes if pin 15 has gone high
;
state_pin_16	:= /AEN *  selecting_FE1200 * /state_pin_16 *  state_pin_15
		+  /AEN *  selecting_FE1200 *  state_pin_16 * /state_pin_15			; hold 
		+  /AEN *  selecting_FE1200 *  state_pin_16 *  state_pin_15 * /state_pin_14	; hold 
		+   AEN *  STE_mem_wr       * /state_pin_16 *  state_pin_15 *  state_pin_14
		+   AEN *  STE_mem_wr       *  state_pin_16 * /state_pin_15			; hold 
		+   AEN *  STE_mem_wr       *  state_pin_16 *  state_pin_15 * /state_pin_14	; hold 
;
; then pin 17 changes if pins 15 has gone high
;

state_pin_17	:= /AEN *  selecting_FE1200 * /state_pin_17 *  state_pin_16 *  state_pin_15 *  state_pin_14 
		+  /AEN *  selecting_FE1200 *  state_pin_17 * /state_pin_16					; hold 
		+   AEN *  STE_mem_wr       * /state_pin_17 *  state_pin_16 *  state_pin_15 *  state_pin_14
		+   AEN *  STE_mem_wr       *  state_pin_17 * /state_pin_16					; hold 
;
; It is probably some kind of shift register somewhat like the LS164?
;
;
; Most pins never go hi-z
;
IOR.oe 		=  vcc
IOW.oe 		=  vcc
state_pin_17.oe 	=  OE
state_pin_16.oe 	=  OE
state_pin_15.oe 	=  OE
state_pin_14.oe 	=  OE
CS_FE1200.oe 	=  vcc
;
;
;
DATACK	 	=  /AEN *  selecting_FE1200 *  state_pin_17	; Acknowledge when selected and state_pin_17 asserted
		+ DATSTB * DATACK				; held while DATSTB asserted
;
; Driven when 
;
DATACK.oe 	=  /AEN *  selecting_FE1200			; driven