`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 23:44:05 03/30/2017 // Design Name: risc // Module Name: F:/Season 1/Hell/HellFixture.v // Project Name: Hell // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: risc // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module HellFixture; // Inputs reg clk; reg reset; // Instantiate the Unit Under Test (UUT) risc uut ( .clk(clk), .reset(reset) ); initial begin // Initialize Inputs clk = 0; reset = 0; // Wait 100 ns for global reset to finish #50 $finish; end // Add stimulus here always #1 clk = !clk; endmodule