library verilog;
use verilog.vl_types.all;
entity spi is
    generic(
        IDLE            : integer := 0;
        START           : integer := 1;
        LOW0            : integer := 2;
        LOW1            : integer := 3;
        HIGH0           : integer := 4;
        HIGH1           : integer := 5;
        SAVE            : integer := 6
    );
    port(
        reset_n         : in     vl_logic;
        clk4x           : in     vl_logic;
        load            : in     vl_logic;
        ready           : out    vl_logic;
        din             : in     vl_logic_vector(7 downto 0);
        dout            : out    vl_logic_vector(7 downto 0);
        sdo             : out    vl_logic;
        sdi             : in     vl_logic;
        sck             : out    vl_logic
    );
end spi;
