library verilog;
use verilog.vl_types.all;
entity cdp1802 is
    generic(
        LOAD            : integer := 0;
        RESET           : integer := 1;
        PAUSE           : integer := 2;
        RUN             : integer := 3;
        S1_RESET        : integer := 0;
        S1_INIT         : integer := 1;
        S0_FETCH        : integer := 2;
        S1_EXEC         : integer := 3;
        S2_DMA          : integer := 4;
        S3_INT          : integer := 5;
        S1_LOAD         : integer := 6
    );
    port(
        clk             : in     vl_logic;
        clr_n           : in     vl_logic;
        wait_n          : in     vl_logic;
        dmai_n          : in     vl_logic;
        dmao_n          : in     vl_logic;
        int_n           : in     vl_logic;
        ef1_n           : in     vl_logic;
        ef2_n           : in     vl_logic;
        ef3_n           : in     vl_logic;
        ef4_n           : in     vl_logic;
        data_in         : in     vl_logic_vector(7 downto 0);
        xtal_n          : out    vl_logic;
        tpa             : out    vl_logic;
        tpb             : out    vl_logic;
        mwr_n           : out    vl_logic;
        mrd_n           : out    vl_logic;
        sc              : out    vl_logic_vector(1 downto 0);
        q               : out    vl_logic;
        n_out           : out    vl_logic_vector(2 downto 0);
        data_out        : out    vl_logic_vector(7 downto 0);
        ma              : out    vl_logic_vector(7 downto 0);
        ma1             : out    vl_logic_vector(7 downto 0);
        oe_n            : out    vl_logic;
        cycle_out       : out    vl_logic_vector(2 downto 0)
    );
end cdp1802;
