library verilog;
use verilog.vl_types.all;
entity clockgen is
    generic(
        Nbits           : integer := 3;
        Divisor         : integer := 8
    );
    port(
        reset_n         : in     vl_logic;
        enable          : in     vl_logic;
        clkin           : in     vl_logic;
        clkout          : out    vl_logic;
        pulse           : out    vl_logic
    );
end clockgen;
