library verilog;
use verilog.vl_types.all;
entity ports is
    port(
        n               : in     vl_logic_vector(2 downto 0);
        n0              : out    vl_logic;
        mrd_n           : in     vl_logic;
        tpb             : in     vl_logic;
        din             : in     vl_logic_vector(7 downto 0);
        dout            : out    vl_logic_vector(7 downto 0);
        in_enb1         : out    vl_logic;
        out_stb1        : out    vl_logic;
        out_stb2        : out    vl_logic;
        out_stb3        : out    vl_logic;
        out_stb4        : out    vl_logic;
        out_stb5        : out    vl_logic;
        out_stb6        : out    vl_logic;
        out_stb7        : out    vl_logic;
        out_data2       : out    vl_logic_vector(3 downto 0);
        out_data3       : out    vl_logic_vector(7 downto 0);
        out_data4       : out    vl_logic_vector(7 downto 0);
        out_data5       : out    vl_logic_vector(7 downto 0);
        out_data6       : out    vl_logic_vector(7 downto 0);
        out_data7       : out    vl_logic_vector(7 downto 0);
        in_data2        : in     vl_logic_vector(7 downto 0);
        in_data3        : in     vl_logic_vector(7 downto 0);
        in_data4        : in     vl_logic_vector(7 downto 0);
        in_data5        : in     vl_logic_vector(7 downto 0);
        in_data6        : in     vl_logic_vector(7 downto 0);
        in_data7        : in     vl_logic_vector(7 downto 0)
    );
end ports;
