library verilog;
use verilog.vl_types.all;
entity registers is
    port(
        sel             : in     vl_logic_vector(3 downto 0);
        wr1             : in     vl_logic;
        wr0             : in     vl_logic;
        rin1            : in     vl_logic_vector(7 downto 0);
        rin0            : in     vl_logic_vector(7 downto 0);
        rout1           : out    vl_logic_vector(7 downto 0);
        rout0           : out    vl_logic_vector(7 downto 0)
    );
end registers;
