|MicroVIP
inclk0_sig => inclk0_sig.IN2
ext_por_n => ext_por_n.IN1
run_sw => CLEAR_N.IN0
ef_n[2] => EF2_N.IN1
ef_n[3] => EF3_N.IN1
ef_n[4] => EF4_N.IN1
gpio_in[0] => gpio_in[0].IN1
gpio_in[1] => gpio_in[1].IN1
gpio_in[2] => gpio_in[2].IN1
gpio_in[3] => gpio_in[3].IN1
gpio_in[4] => gpio_in[4].IN1
gpio_in[5] => gpio_in[5].IN1
gpio_in[6] => gpio_in[6].IN1
gpio_in[7] => gpio_in[7].IN1
flash_miso => flash_miso.IN1
pbtn => alt_rom.IN1


|MicroVIP|pll_clock:MCLK
areset => areset.IN1
inclk0 => sub_wire4[0].IN1


|MicroVIP|pll_clock:MCLK|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>


|MicroVIP|clockgen:X1
reset_n => count_reset.OUTPUTSELECT
reset_n => always2.IN1
reset_n => clkout~reg0.ACLR
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
clkin => counter[0].CLK
clkin => counter[1].CLK
clkin => counter[2].CLK
clkin => counter[3].CLK
clkin => counter[4].CLK
clkin => counter[5].CLK
clkin => counter[6].CLK
clkin => clkout~reg0.CLK
clkin => pulse~reg0.CLK


|MicroVIP|cdp1802:U1
clk => idle.CLK
clk => forceS1.CLK
clk => int_en.CLK
clk => q_r.CLK
clk => asel.CLK
clk => rwr1.CLK
clk => rwr0.CLK
clk => xclk.CLK
clk => tclk.CLK
clk => pclk.CLK
clk => inclk.CLK
clk => dclk.CLK
clk => bclk.CLK
clk => aclk.CLK
clk => ef_in[0].CLK
clk => ef_in[1].CLK
clk => ef_in[2].CLK
clk => ef_in[3].CLK
clk => mrd_n_r.CLK
clk => tpb_r.CLK
clk => power_up.CLK
clk => cycle[0].CLK
clk => cycle[1].CLK
clk => cycle[2].CLK
clk => mode[0].CLK
clk => mode[1].CLK
clk => dma_out.CLK
clk => dma_in.CLK
clk => int_in.CLK
clk => xtal_n.DATAIN
clk => state~7.DATAIN
clr_n => clr_n.IN1
wait_n => mode[0].DATAIN
dmai_n => dma_in.DATAIN
dmao_n => dma_out.DATAIN
int_n => int_in.DATAIN
ef1_n => ef_in[0].DATAIN
ef2_n => ef_in[1].DATAIN
ef3_n => ef_in[2].DATAIN
ef4_n => ef_in[3].DATAIN
data_in[0] => data_in[0].IN1
data_in[1] => data_in[1].IN1
data_in[2] => data_in[2].IN1
data_in[3] => data_in[3].IN1
data_in[4] => data_in[4].IN1
data_in[5] => data_in[5].IN1
data_in[6] => data_in[6].IN1
data_in[7] => data_in[7].IN1


|MicroVIP|cdp1802:U1|datapath:dp
clr_n => nreg[0].ACLR
clr_n => nreg[1].ACLR
clr_n => nreg[2].ACLR
clr_n => nreg[3].ACLR
clr_n => ireg[0].ACLR
clr_n => ireg[1].ACLR
clr_n => ireg[2].ACLR
clr_n => ireg[3].ACLR
clr_n => df_r.ACLR
clr_n => dreg[0].ACLR
clr_n => dreg[1].ACLR
clr_n => dreg[2].ACLR
clr_n => dreg[3].ACLR
clr_n => dreg[4].ACLR
clr_n => dreg[5].ACLR
clr_n => dreg[6].ACLR
clr_n => dreg[7].ACLR
clr_n => preg[0].ACLR
clr_n => preg[1].ACLR
clr_n => preg[2].ACLR
clr_n => preg[3].ACLR
clr_n => xreg[0].ACLR
clr_n => xreg[1].ACLR
clr_n => xreg[2].ACLR
clr_n => xreg[3].ACLR
load => ma_r.OUTPUTSELECT
load => ma_r.OUTPUTSELECT
load => ma_r.OUTPUTSELECT
load => ma_r.OUTPUTSELECT
load => ma_r.OUTPUTSELECT
load => ma_r.OUTPUTSELECT
load => ma_r.OUTPUTSELECT
load => ma_r.OUTPUTSELECT
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
clocks[0] => areg[0].CLK
clocks[0] => areg[1].CLK
clocks[0] => areg[2].CLK
clocks[0] => areg[3].CLK
clocks[0] => areg[4].CLK
clocks[0] => areg[5].CLK
clocks[0] => areg[6].CLK
clocks[0] => areg[7].CLK
clocks[0] => areg[8].CLK
clocks[0] => areg[9].CLK
clocks[0] => areg[10].CLK
clocks[0] => areg[11].CLK
clocks[0] => areg[12].CLK
clocks[0] => areg[13].CLK
clocks[0] => areg[14].CLK
clocks[0] => areg[15].CLK
clocks[1] => breg[0].CLK
clocks[1] => breg[1].CLK
clocks[1] => breg[2].CLK
clocks[1] => breg[3].CLK
clocks[1] => breg[4].CLK
clocks[1] => breg[5].CLK
clocks[1] => breg[6].CLK
clocks[1] => breg[7].CLK
clocks[2] => df_r.CLK
clocks[2] => dreg[0].CLK
clocks[2] => dreg[1].CLK
clocks[2] => dreg[2].CLK
clocks[2] => dreg[3].CLK
clocks[2] => dreg[4].CLK
clocks[2] => dreg[5].CLK
clocks[2] => dreg[6].CLK
clocks[2] => dreg[7].CLK
clocks[3] => nreg[0].CLK
clocks[3] => nreg[1].CLK
clocks[3] => nreg[2].CLK
clocks[3] => nreg[3].CLK
clocks[3] => ireg[0].CLK
clocks[3] => ireg[1].CLK
clocks[3] => ireg[2].CLK
clocks[3] => ireg[3].CLK
clocks[4] => preg[0].CLK
clocks[4] => preg[1].CLK
clocks[4] => preg[2].CLK
clocks[4] => preg[3].CLK
clocks[5] => treg[0].CLK
clocks[5] => treg[1].CLK
clocks[5] => treg[2].CLK
clocks[5] => treg[3].CLK
clocks[5] => treg[4].CLK
clocks[5] => treg[5].CLK
clocks[5] => treg[6].CLK
clocks[5] => treg[7].CLK
clocks[6] => xreg[0].CLK
clocks[6] => xreg[1].CLK
clocks[6] => xreg[2].CLK
clocks[6] => xreg[3].CLK
clocks[7] => rwr0.IN1
clocks[8] => rwr1.IN1
clocks[9] => ~NO_FANOUT~
selects[0] => ma_r.OUTPUTSELECT
selects[0] => ma_r.OUTPUTSELECT
selects[0] => ma_r.OUTPUTSELECT
selects[0] => ma_r.OUTPUTSELECT
selects[0] => ma_r.OUTPUTSELECT
selects[0] => ma_r.OUTPUTSELECT
selects[0] => ma_r.OUTPUTSELECT
selects[0] => ma_r.OUTPUTSELECT
selects[1] => Mux0.IN2
selects[1] => Mux1.IN2
selects[1] => Mux2.IN2
selects[1] => Mux3.IN2
selects[1] => Mux4.IN2
selects[1] => Mux5.IN2
selects[1] => Mux6.IN2
selects[1] => Mux7.IN2
selects[2] => Mux0.IN1
selects[2] => Mux1.IN1
selects[2] => Mux2.IN1
selects[2] => Mux3.IN1
selects[2] => Mux4.IN1
selects[2] => Mux5.IN1
selects[2] => Mux6.IN1
selects[2] => Mux7.IN1
selects[3] => Mux8.IN4
selects[3] => Mux9.IN4
selects[3] => Mux10.IN4
selects[3] => Mux11.IN4
selects[4] => Mux8.IN3
selects[4] => Mux9.IN3
selects[4] => Mux10.IN3
selects[4] => Mux11.IN3
selects[5] => Mux12.IN3
selects[5] => Mux13.IN3
selects[5] => Mux14.IN3
selects[5] => Mux15.IN3
selects[6] => Mux12.IN2
selects[6] => Mux13.IN2
selects[6] => Mux14.IN2
selects[6] => Mux15.IN2
selects[7] => Mux36.IN2
selects[7] => Mux37.IN2
selects[7] => Mux38.IN2
selects[7] => Mux39.IN2
selects[7] => Mux40.IN2
selects[7] => Mux41.IN2
selects[7] => Mux42.IN2
selects[7] => Mux43.IN2
selects[8] => Mux36.IN1
selects[8] => Mux37.IN1
selects[8] => Mux38.IN1
selects[8] => Mux39.IN1
selects[8] => Mux40.IN1
selects[8] => Mux41.IN1
selects[8] => Mux42.IN1
selects[8] => Mux43.IN1
selects[9] => Mux20.IN6
selects[9] => Mux21.IN6
selects[9] => Mux22.IN6
selects[9] => Mux23.IN6
selects[9] => Mux24.IN6
selects[9] => Mux25.IN6
selects[9] => Mux26.IN6
selects[9] => Mux27.IN6
selects[9] => Mux28.IN7
selects[9] => Mux29.IN7
selects[9] => Mux30.IN7
selects[9] => Mux31.IN7
selects[9] => Mux32.IN7
selects[9] => Mux33.IN7
selects[9] => Mux34.IN7
selects[9] => Mux35.IN7
selects[10] => Mux20.IN5
selects[10] => Mux21.IN5
selects[10] => Mux22.IN5
selects[10] => Mux23.IN5
selects[10] => Mux24.IN5
selects[10] => Mux25.IN5
selects[10] => Mux26.IN5
selects[10] => Mux27.IN5
selects[10] => Mux28.IN6
selects[10] => Mux29.IN6
selects[10] => Mux30.IN6
selects[10] => Mux31.IN6
selects[10] => Mux32.IN6
selects[10] => Mux33.IN6
selects[10] => Mux34.IN6
selects[10] => Mux35.IN6
selects[11] => Mux20.IN4
selects[11] => Mux21.IN4
selects[11] => Mux22.IN4
selects[11] => Mux23.IN4
selects[11] => Mux24.IN4
selects[11] => Mux25.IN4
selects[11] => Mux26.IN4
selects[11] => Mux27.IN4
selects[11] => Mux28.IN5
selects[11] => Mux29.IN5
selects[11] => Mux30.IN5
selects[11] => Mux31.IN5
selects[11] => Mux32.IN5
selects[11] => Mux33.IN5
selects[11] => Mux34.IN5
selects[11] => Mux35.IN5
selects[12] => Mux16.IN4
selects[12] => Mux17.IN4
selects[12] => Mux18.IN4
selects[12] => Mux19.IN4
selects[13] => Mux16.IN3
selects[13] => Mux17.IN3
selects[13] => Mux18.IN3
selects[13] => Mux19.IN3
selects[14] => Mux16.IN2
selects[14] => Mux17.IN2
selects[14] => Mux18.IN2
selects[14] => Mux19.IN2
selects[15] => ~NO_FANOUT~


|MicroVIP|cdp1802:U1|datapath:dp|registers:ScratchPad
sel[0] => scr1.waddr_a[0].DATAIN
sel[0] => scr0.waddr_a[0].DATAIN
sel[0] => scr1.WADDR
sel[0] => scr1.RADDR
sel[0] => scr0.WADDR
sel[0] => scr0.RADDR
sel[1] => scr1.waddr_a[1].DATAIN
sel[1] => scr0.waddr_a[1].DATAIN
sel[1] => scr1.WADDR1
sel[1] => scr1.RADDR1
sel[1] => scr0.WADDR1
sel[1] => scr0.RADDR1
sel[2] => scr1.waddr_a[2].DATAIN
sel[2] => scr0.waddr_a[2].DATAIN
sel[2] => scr1.WADDR2
sel[2] => scr1.RADDR2
sel[2] => scr0.WADDR2
sel[2] => scr0.RADDR2
sel[3] => scr1.waddr_a[3].DATAIN
sel[3] => scr0.waddr_a[3].DATAIN
sel[3] => scr1.WADDR3
sel[3] => scr1.RADDR3
sel[3] => scr0.WADDR3
sel[3] => scr0.RADDR3
wr1 => scr1.we_a.CLK
wr1 => scr1.waddr_a[3].CLK
wr1 => scr1.waddr_a[2].CLK
wr1 => scr1.waddr_a[1].CLK
wr1 => scr1.waddr_a[0].CLK
wr1 => scr1.data_a[7].CLK
wr1 => scr1.data_a[6].CLK
wr1 => scr1.data_a[5].CLK
wr1 => scr1.data_a[4].CLK
wr1 => scr1.data_a[3].CLK
wr1 => scr1.data_a[2].CLK
wr1 => scr1.data_a[1].CLK
wr1 => scr1.data_a[0].CLK
wr1 => scr1.CLK0
wr0 => scr0.we_a.CLK
wr0 => scr0.waddr_a[3].CLK
wr0 => scr0.waddr_a[2].CLK
wr0 => scr0.waddr_a[1].CLK
wr0 => scr0.waddr_a[0].CLK
wr0 => scr0.data_a[7].CLK
wr0 => scr0.data_a[6].CLK
wr0 => scr0.data_a[5].CLK
wr0 => scr0.data_a[4].CLK
wr0 => scr0.data_a[3].CLK
wr0 => scr0.data_a[2].CLK
wr0 => scr0.data_a[1].CLK
wr0 => scr0.data_a[0].CLK
wr0 => scr0.CLK0
rin1[0] => scr1.data_a[0].DATAIN
rin1[0] => scr1.DATAIN
rin1[1] => scr1.data_a[1].DATAIN
rin1[1] => scr1.DATAIN1
rin1[2] => scr1.data_a[2].DATAIN
rin1[2] => scr1.DATAIN2
rin1[3] => scr1.data_a[3].DATAIN
rin1[3] => scr1.DATAIN3
rin1[4] => scr1.data_a[4].DATAIN
rin1[4] => scr1.DATAIN4
rin1[5] => scr1.data_a[5].DATAIN
rin1[5] => scr1.DATAIN5
rin1[6] => scr1.data_a[6].DATAIN
rin1[6] => scr1.DATAIN6
rin1[7] => scr1.data_a[7].DATAIN
rin1[7] => scr1.DATAIN7
rin0[0] => scr0.data_a[0].DATAIN
rin0[0] => scr0.DATAIN
rin0[1] => scr0.data_a[1].DATAIN
rin0[1] => scr0.DATAIN1
rin0[2] => scr0.data_a[2].DATAIN
rin0[2] => scr0.DATAIN2
rin0[3] => scr0.data_a[3].DATAIN
rin0[3] => scr0.DATAIN3
rin0[4] => scr0.data_a[4].DATAIN
rin0[4] => scr0.DATAIN4
rin0[5] => scr0.data_a[5].DATAIN
rin0[5] => scr0.DATAIN5
rin0[6] => scr0.data_a[6].DATAIN
rin0[6] => scr0.DATAIN6
rin0[7] => scr0.data_a[7].DATAIN
rin0[7] => scr0.DATAIN7


|MicroVIP|cdp1802:U1|datapath:dp|alu:ALU
op[0] => Mux0.IN9
op[0] => Mux1.IN13
op[0] => Mux2.IN12
op[0] => Mux3.IN12
op[0] => Mux4.IN12
op[0] => Mux5.IN12
op[0] => Mux6.IN12
op[0] => Mux7.IN12
op[0] => Mux8.IN13
op[1] => Mux0.IN8
op[1] => Mux1.IN12
op[1] => Mux2.IN11
op[1] => Mux3.IN11
op[1] => Mux4.IN11
op[1] => Mux5.IN11
op[1] => Mux6.IN11
op[1] => Mux7.IN11
op[1] => Mux8.IN12
op[2] => Mux0.IN7
op[2] => Mux1.IN11
op[2] => Mux2.IN10
op[2] => Mux3.IN10
op[2] => Mux4.IN10
op[2] => Mux5.IN10
op[2] => Mux6.IN10
op[2] => Mux7.IN10
op[2] => Mux8.IN11
op[3] => Mux0.IN6
op[3] => Mux1.IN10
op[3] => Mux2.IN9
op[3] => Mux3.IN9
op[3] => Mux4.IN9
op[3] => Mux5.IN9
op[3] => Mux6.IN9
op[3] => Mux7.IN9
op[3] => Mux8.IN10
d[0] => lac4.IN1
d[0] => lac4.IN1
d[0] => lac4.IN0
d[0] => Mux0.IN12
d[0] => Mux0.IN13
d[0] => alu_calc.IN0
d[0] => alu_calc.IN0
d[0] => alu_calc.IN0
d[0] => Add30.IN16
d[0] => Add31.IN8
d[0] => Add35.IN16
d[0] => Mux7.IN18
d[0] => Mux7.IN19
d[0] => Mux8.IN16
d[0] => Mux8.IN17
d[0] => Mux8.IN18
d[0] => Add33.IN8
d[0] => Add29.IN8
d[0] => lac4.IN1
d[0] => lac4.IN0
d[1] => lac4.IN1
d[1] => lac4.IN1
d[1] => lac4.IN0
d[1] => alu_calc.IN0
d[1] => alu_calc.IN0
d[1] => alu_calc.IN0
d[1] => Add30.IN15
d[1] => Add31.IN7
d[1] => Add35.IN15
d[1] => Mux6.IN18
d[1] => Mux6.IN19
d[1] => Mux7.IN15
d[1] => Mux7.IN16
d[1] => Mux7.IN17
d[1] => Mux8.IN14
d[1] => Mux8.IN15
d[1] => Add33.IN7
d[1] => Add29.IN7
d[1] => lac4.IN1
d[1] => lac4.IN0
d[2] => lac4.IN1
d[2] => lac4.IN1
d[2] => lac4.IN0
d[2] => alu_calc.IN0
d[2] => alu_calc.IN0
d[2] => alu_calc.IN0
d[2] => Add30.IN14
d[2] => Add31.IN6
d[2] => Add35.IN14
d[2] => Mux5.IN18
d[2] => Mux5.IN19
d[2] => Mux6.IN15
d[2] => Mux6.IN16
d[2] => Mux6.IN17
d[2] => Mux7.IN13
d[2] => Mux7.IN14
d[2] => lac4.IN1
d[2] => lac4.IN0
d[2] => Add33.IN4
d[2] => Add29.IN4
d[3] => lac4.IN0
d[3] => lac4.IN0
d[3] => alu_calc.IN0
d[3] => alu_calc.IN0
d[3] => alu_calc.IN0
d[3] => Add30.IN13
d[3] => Add31.IN5
d[3] => Add35.IN13
d[3] => Mux4.IN18
d[3] => Mux4.IN19
d[3] => Mux5.IN15
d[3] => Mux5.IN16
d[3] => Mux5.IN17
d[3] => Mux6.IN13
d[3] => Mux6.IN14
d[3] => lac4.IN0
d[3] => lac4.IN0
d[3] => Add33.IN3
d[3] => Add29.IN3
d[4] => lac4.IN1
d[4] => lac4.IN1
d[4] => lac4.IN0
d[4] => alu_calc.IN0
d[4] => alu_calc.IN0
d[4] => alu_calc.IN0
d[4] => Add30.IN12
d[4] => Add31.IN4
d[4] => Add35.IN12
d[4] => Mux3.IN18
d[4] => Mux3.IN19
d[4] => Mux4.IN15
d[4] => Mux4.IN16
d[4] => Mux4.IN17
d[4] => Mux5.IN13
d[4] => Mux5.IN14
d[4] => Add33.IN6
d[4] => Add29.IN6
d[4] => lac4.IN1
d[4] => lac4.IN0
d[5] => lac4.IN1
d[5] => lac4.IN1
d[5] => lac4.IN0
d[5] => alu_calc.IN0
d[5] => alu_calc.IN0
d[5] => alu_calc.IN0
d[5] => Add30.IN11
d[5] => Add31.IN3
d[5] => Add35.IN11
d[5] => Mux2.IN18
d[5] => Mux2.IN19
d[5] => Mux3.IN15
d[5] => Mux3.IN16
d[5] => Mux3.IN17
d[5] => Mux4.IN13
d[5] => Mux4.IN14
d[5] => Add33.IN5
d[5] => Add29.IN5
d[5] => lac4.IN1
d[5] => lac4.IN0
d[6] => lac4.IN1
d[6] => lac4.IN1
d[6] => lac4.IN0
d[6] => alu_calc.IN0
d[6] => alu_calc.IN0
d[6] => alu_calc.IN0
d[6] => Add30.IN10
d[6] => Add31.IN2
d[6] => Add35.IN10
d[6] => Mux1.IN17
d[6] => Mux1.IN18
d[6] => Mux2.IN15
d[6] => Mux2.IN16
d[6] => Mux2.IN17
d[6] => Mux3.IN13
d[6] => Mux3.IN14
d[6] => lac4.IN1
d[6] => lac4.IN0
d[6] => Add33.IN2
d[6] => Add29.IN2
d[7] => lac4.IN0
d[7] => lac4.IN0
d[7] => Mux0.IN10
d[7] => Mux0.IN11
d[7] => alu_calc.IN0
d[7] => alu_calc.IN0
d[7] => alu_calc.IN0
d[7] => Add30.IN9
d[7] => Add31.IN1
d[7] => Add35.IN9
d[7] => Mux1.IN14
d[7] => Mux1.IN15
d[7] => Mux1.IN16
d[7] => Mux2.IN13
d[7] => Mux2.IN14
d[7] => lac4.IN0
d[7] => lac4.IN0
d[7] => Add33.IN1
d[7] => Add29.IN1
m[0] => lac4.IN1
m[0] => lac4.IN1
m[0] => lac4.IN1
m[0] => alu_calc.IN1
m[0] => alu_calc.IN1
m[0] => alu_calc.IN1
m[0] => Add29.IN16
m[0] => Add31.IN16
m[0] => Add33.IN16
m[0] => Add35.IN8
m[0] => Add30.IN8
m[0] => lac4.IN1
m[0] => lac4.IN1
m[1] => lac4.IN1
m[1] => lac4.IN1
m[1] => lac4.IN1
m[1] => alu_calc.IN1
m[1] => alu_calc.IN1
m[1] => alu_calc.IN1
m[1] => Add29.IN15
m[1] => Add31.IN15
m[1] => Add33.IN15
m[1] => Add35.IN7
m[1] => Add30.IN7
m[1] => lac4.IN1
m[1] => lac4.IN1
m[2] => lac4.IN1
m[2] => lac4.IN1
m[2] => lac4.IN1
m[2] => alu_calc.IN1
m[2] => alu_calc.IN1
m[2] => alu_calc.IN1
m[2] => Add29.IN14
m[2] => Add31.IN14
m[2] => Add33.IN14
m[2] => lac4.IN1
m[2] => lac4.IN1
m[2] => Add35.IN4
m[2] => Add30.IN4
m[3] => lac4.IN1
m[3] => lac4.IN1
m[3] => alu_calc.IN1
m[3] => alu_calc.IN1
m[3] => alu_calc.IN1
m[3] => Add29.IN13
m[3] => Add31.IN13
m[3] => Add33.IN13
m[3] => lac4.IN1
m[3] => lac4.IN1
m[3] => Add35.IN3
m[3] => Add30.IN3
m[4] => lac4.IN1
m[4] => lac4.IN1
m[4] => lac4.IN1
m[4] => alu_calc.IN1
m[4] => alu_calc.IN1
m[4] => alu_calc.IN1
m[4] => Add29.IN12
m[4] => Add31.IN12
m[4] => Add33.IN12
m[4] => Add35.IN6
m[4] => Add30.IN6
m[4] => lac4.IN1
m[4] => lac4.IN1
m[5] => lac4.IN1
m[5] => lac4.IN1
m[5] => lac4.IN1
m[5] => alu_calc.IN1
m[5] => alu_calc.IN1
m[5] => alu_calc.IN1
m[5] => Add29.IN11
m[5] => Add31.IN11
m[5] => Add33.IN11
m[5] => Add35.IN5
m[5] => Add30.IN5
m[5] => lac4.IN1
m[5] => lac4.IN1
m[6] => lac4.IN1
m[6] => lac4.IN1
m[6] => lac4.IN1
m[6] => alu_calc.IN1
m[6] => alu_calc.IN1
m[6] => alu_calc.IN1
m[6] => Add29.IN10
m[6] => Add31.IN10
m[6] => Add33.IN10
m[6] => lac4.IN1
m[6] => lac4.IN1
m[6] => Add35.IN2
m[6] => Add30.IN2
m[7] => lac4.IN1
m[7] => lac4.IN1
m[7] => alu_calc.IN1
m[7] => alu_calc.IN1
m[7] => alu_calc.IN1
m[7] => Add29.IN9
m[7] => Add31.IN9
m[7] => Add33.IN9
m[7] => lac4.IN1
m[7] => lac4.IN1
m[7] => Add35.IN1
m[7] => Add30.IN1
cin => lac4.IN1
cin => Mux0.IN14
cin => Mux0.IN15
cin => Mux0.IN16
cin => Mux0.IN17
cin => Mux0.IN18
cin => Mux0.IN19
cin => Add32.IN16
cin => Add34.IN16
cin => Add36.IN16
cin => Mux1.IN19
cin => Mux8.IN19
cin => lac4.IN1
cin => lac4.IN1


|MicroVIP|sync_rom_vip:U2A
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
addr[0] => memdata.RADDR
addr[1] => memdata.RADDR1
addr[2] => memdata.RADDR2
addr[3] => memdata.RADDR3
addr[4] => memdata.RADDR4
addr[5] => memdata.RADDR5
addr[6] => memdata.RADDR6
addr[7] => memdata.RADDR7
addr[8] => memdata.RADDR8
clk => q[0]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[6]~reg0.CLK
clk => q[7]~reg0.CLK


|MicroVIP|sync_rom_ut4:U2B
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
addr[0] => memdata.RADDR
addr[1] => memdata.RADDR1
addr[2] => memdata.RADDR2
addr[3] => memdata.RADDR3
addr[4] => memdata.RADDR4
addr[5] => memdata.RADDR5
addr[6] => memdata.RADDR6
addr[7] => memdata.RADDR7
addr[8] => memdata.RADDR8
clk => q[0]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[6]~reg0.CLK
clk => q[7]~reg0.CLK


|MicroVIP|sync_ram_1024:U3
data[0] => memdata.data_a[0].DATAIN
data[0] => memdata.DATAIN
data[1] => memdata.data_a[1].DATAIN
data[1] => memdata.DATAIN1
data[2] => memdata.data_a[2].DATAIN
data[2] => memdata.DATAIN2
data[3] => memdata.data_a[3].DATAIN
data[3] => memdata.DATAIN3
data[4] => memdata.data_a[4].DATAIN
data[4] => memdata.DATAIN4
data[5] => memdata.data_a[5].DATAIN
data[5] => memdata.DATAIN5
data[6] => memdata.data_a[6].DATAIN
data[6] => memdata.DATAIN6
data[7] => memdata.data_a[7].DATAIN
data[7] => memdata.DATAIN7
addr[0] => memdata.waddr_a[0].DATAIN
addr[0] => addr_reg[0].DATAIN
addr[0] => memdata.WADDR
addr[1] => memdata.waddr_a[1].DATAIN
addr[1] => addr_reg[1].DATAIN
addr[1] => memdata.WADDR1
addr[2] => memdata.waddr_a[2].DATAIN
addr[2] => addr_reg[2].DATAIN
addr[2] => memdata.WADDR2
addr[3] => memdata.waddr_a[3].DATAIN
addr[3] => addr_reg[3].DATAIN
addr[3] => memdata.WADDR3
addr[4] => memdata.waddr_a[4].DATAIN
addr[4] => addr_reg[4].DATAIN
addr[4] => memdata.WADDR4
addr[5] => memdata.waddr_a[5].DATAIN
addr[5] => addr_reg[5].DATAIN
addr[5] => memdata.WADDR5
addr[6] => memdata.waddr_a[6].DATAIN
addr[6] => addr_reg[6].DATAIN
addr[6] => memdata.WADDR6
addr[7] => memdata.waddr_a[7].DATAIN
addr[7] => addr_reg[7].DATAIN
addr[7] => memdata.WADDR7
addr[8] => memdata.waddr_a[8].DATAIN
addr[8] => addr_reg[8].DATAIN
addr[8] => memdata.WADDR8
addr[9] => memdata.waddr_a[9].DATAIN
addr[9] => addr_reg[9].DATAIN
addr[9] => memdata.WADDR9
we => memdata.we_a.DATAIN
we => memdata.WE
clk => memdata.we_a.CLK
clk => memdata.waddr_a[9].CLK
clk => memdata.waddr_a[8].CLK
clk => memdata.waddr_a[7].CLK
clk => memdata.waddr_a[6].CLK
clk => memdata.waddr_a[5].CLK
clk => memdata.waddr_a[4].CLK
clk => memdata.waddr_a[3].CLK
clk => memdata.waddr_a[2].CLK
clk => memdata.waddr_a[1].CLK
clk => memdata.waddr_a[0].CLK
clk => memdata.data_a[7].CLK
clk => memdata.data_a[6].CLK
clk => memdata.data_a[5].CLK
clk => memdata.data_a[4].CLK
clk => memdata.data_a[3].CLK
clk => memdata.data_a[2].CLK
clk => memdata.data_a[1].CLK
clk => memdata.data_a[0].CLK
clk => addr_reg[0].CLK
clk => addr_reg[1].CLK
clk => addr_reg[2].CLK
clk => addr_reg[3].CLK
clk => addr_reg[4].CLK
clk => addr_reg[5].CLK
clk => addr_reg[6].CLK
clk => addr_reg[7].CLK
clk => addr_reg[8].CLK
clk => addr_reg[9].CLK
clk => memdata.CLK0


|MicroVIP|sync_ram:U4
data[0] => memdata.data_a[0].DATAIN
data[0] => memdata.DATAIN
data[1] => memdata.data_a[1].DATAIN
data[1] => memdata.DATAIN1
data[2] => memdata.data_a[2].DATAIN
data[2] => memdata.DATAIN2
data[3] => memdata.data_a[3].DATAIN
data[3] => memdata.DATAIN3
data[4] => memdata.data_a[4].DATAIN
data[4] => memdata.DATAIN4
data[5] => memdata.data_a[5].DATAIN
data[5] => memdata.DATAIN5
data[6] => memdata.data_a[6].DATAIN
data[6] => memdata.DATAIN6
data[7] => memdata.data_a[7].DATAIN
data[7] => memdata.DATAIN7
addr[0] => memdata.waddr_a[0].DATAIN
addr[0] => addr_reg[0].DATAIN
addr[0] => memdata.WADDR
addr[1] => memdata.waddr_a[1].DATAIN
addr[1] => addr_reg[1].DATAIN
addr[1] => memdata.WADDR1
addr[2] => memdata.waddr_a[2].DATAIN
addr[2] => addr_reg[2].DATAIN
addr[2] => memdata.WADDR2
addr[3] => memdata.waddr_a[3].DATAIN
addr[3] => addr_reg[3].DATAIN
addr[3] => memdata.WADDR3
addr[4] => memdata.waddr_a[4].DATAIN
addr[4] => addr_reg[4].DATAIN
addr[4] => memdata.WADDR4
addr[5] => memdata.waddr_a[5].DATAIN
addr[5] => addr_reg[5].DATAIN
addr[5] => memdata.WADDR5
addr[6] => memdata.waddr_a[6].DATAIN
addr[6] => addr_reg[6].DATAIN
addr[6] => memdata.WADDR6
addr[7] => memdata.waddr_a[7].DATAIN
addr[7] => addr_reg[7].DATAIN
addr[7] => memdata.WADDR7
addr[8] => memdata.waddr_a[8].DATAIN
addr[8] => addr_reg[8].DATAIN
addr[8] => memdata.WADDR8
addr[9] => memdata.waddr_a[9].DATAIN
addr[9] => addr_reg[9].DATAIN
addr[9] => memdata.WADDR9
addr[10] => memdata.waddr_a[10].DATAIN
addr[10] => addr_reg[10].DATAIN
addr[10] => memdata.WADDR10
addr[11] => memdata.waddr_a[11].DATAIN
addr[11] => addr_reg[11].DATAIN
addr[11] => memdata.WADDR11
we => memdata.we_a.DATAIN
we => memdata.WE
clk => memdata.we_a.CLK
clk => memdata.waddr_a[11].CLK
clk => memdata.waddr_a[10].CLK
clk => memdata.waddr_a[9].CLK
clk => memdata.waddr_a[8].CLK
clk => memdata.waddr_a[7].CLK
clk => memdata.waddr_a[6].CLK
clk => memdata.waddr_a[5].CLK
clk => memdata.waddr_a[4].CLK
clk => memdata.waddr_a[3].CLK
clk => memdata.waddr_a[2].CLK
clk => memdata.waddr_a[1].CLK
clk => memdata.waddr_a[0].CLK
clk => memdata.data_a[7].CLK
clk => memdata.data_a[6].CLK
clk => memdata.data_a[5].CLK
clk => memdata.data_a[4].CLK
clk => memdata.data_a[3].CLK
clk => memdata.data_a[2].CLK
clk => memdata.data_a[1].CLK
clk => memdata.data_a[0].CLK
clk => addr_reg[0].CLK
clk => addr_reg[1].CLK
clk => addr_reg[2].CLK
clk => addr_reg[3].CLK
clk => addr_reg[4].CLK
clk => addr_reg[5].CLK
clk => addr_reg[6].CLK
clk => addr_reg[7].CLK
clk => addr_reg[8].CLK
clk => addr_reg[9].CLK
clk => addr_reg[10].CLK
clk => addr_reg[11].CLK
clk => memdata.CLK0


|MicroVIP|cbi:BMUX
addr[0] => Equal0.IN6
addr[0] => Equal1.IN1
addr[1] => Equal0.IN5
addr[1] => Equal1.IN6
addr[2] => Equal0.IN4
addr[2] => Equal1.IN5
addr[3] => Equal0.IN3
addr[3] => Equal1.IN4
addr[4] => Equal0.IN2
addr[4] => Equal1.IN3
addr[4] => Equal2.IN2
addr[4] => Equal3.IN2
addr[4] => Equal4.IN2
addr[5] => Equal0.IN1
addr[5] => Equal1.IN2
addr[5] => Equal2.IN1
addr[5] => Equal3.IN1
addr[5] => Equal4.IN1
addr[6] => ram_we.IN0
addr[6] => Equal0.IN0
addr[6] => Equal1.IN0
addr[6] => Equal2.IN0
addr[6] => Equal3.IN0
addr[6] => Equal4.IN0
mwr_n => ram_we.IN1
mwr_n => aux_we.IN1
rom_map => rom_data.IN0
rom_map => rom_data.IN0
rom_map => memory_data.IN1
rom_map => ram_we.IN1
rom_map => aux_we.IN1
alt_rom => rom_data.IN1
alt_rom => rom_data.IN1
n0 => cbi_to_ram_data.OUTPUTSELECT
n0 => cbi_to_ram_data.OUTPUTSELECT
n0 => cbi_to_ram_data.OUTPUTSELECT
n0 => cbi_to_ram_data.OUTPUTSELECT
n0 => cbi_to_ram_data.OUTPUTSELECT
n0 => cbi_to_ram_data.OUTPUTSELECT
n0 => cbi_to_ram_data.OUTPUTSELECT
n0 => cbi_to_ram_data.OUTPUTSELECT
n0 => cbi_to_aux_data.OUTPUTSELECT
n0 => cbi_to_aux_data.OUTPUTSELECT
n0 => cbi_to_aux_data.OUTPUTSELECT
n0 => cbi_to_aux_data.OUTPUTSELECT
n0 => cbi_to_aux_data.OUTPUTSELECT
n0 => cbi_to_aux_data.OUTPUTSELECT
n0 => cbi_to_aux_data.OUTPUTSELECT
n0 => cbi_to_aux_data.OUTPUTSELECT
n0 => cbi_to_up_data.OUTPUTSELECT
n0 => cbi_to_up_data.OUTPUTSELECT
n0 => cbi_to_up_data.OUTPUTSELECT
n0 => cbi_to_up_data.OUTPUTSELECT
n0 => cbi_to_up_data.OUTPUTSELECT
n0 => cbi_to_up_data.OUTPUTSELECT
n0 => cbi_to_up_data.OUTPUTSELECT
n0 => cbi_to_up_data.OUTPUTSELECT
up_to_cbi_data[0] => cbi_to_ram_data.DATAB
up_to_cbi_data[0] => cbi_to_aux_data.DATAB
up_to_cbi_data[1] => cbi_to_ram_data.DATAB
up_to_cbi_data[1] => cbi_to_aux_data.DATAB
up_to_cbi_data[2] => cbi_to_ram_data.DATAB
up_to_cbi_data[2] => cbi_to_aux_data.DATAB
up_to_cbi_data[3] => cbi_to_ram_data.DATAB
up_to_cbi_data[3] => cbi_to_aux_data.DATAB
up_to_cbi_data[4] => cbi_to_ram_data.DATAB
up_to_cbi_data[4] => cbi_to_aux_data.DATAB
up_to_cbi_data[5] => cbi_to_ram_data.DATAB
up_to_cbi_data[5] => cbi_to_aux_data.DATAB
up_to_cbi_data[6] => cbi_to_ram_data.DATAB
up_to_cbi_data[6] => cbi_to_aux_data.DATAB
up_to_cbi_data[7] => cbi_to_ram_data.DATAB
up_to_cbi_data[7] => cbi_to_aux_data.DATAB
rom1_to_cbi_data[0] => rom_data[0].DATAB
rom1_to_cbi_data[1] => rom_data[1].DATAB
rom1_to_cbi_data[2] => rom_data[2].DATAB
rom1_to_cbi_data[3] => rom_data[3].DATAB
rom1_to_cbi_data[4] => rom_data[4].DATAB
rom1_to_cbi_data[5] => rom_data[5].DATAB
rom1_to_cbi_data[6] => rom_data[6].DATAB
rom1_to_cbi_data[7] => rom_data[7].DATAB
rom2_to_cbi_data[0] => rom_data.DATAB
rom2_to_cbi_data[1] => rom_data.DATAB
rom2_to_cbi_data[2] => rom_data.DATAB
rom2_to_cbi_data[3] => rom_data.DATAB
rom2_to_cbi_data[4] => rom_data.DATAB
rom2_to_cbi_data[5] => rom_data.DATAB
rom2_to_cbi_data[6] => rom_data.DATAB
rom2_to_cbi_data[7] => rom_data.DATAB
rom3_to_cbi_data[0] => rom_data.DATAA
rom3_to_cbi_data[1] => rom_data.DATAA
rom3_to_cbi_data[2] => rom_data.DATAA
rom3_to_cbi_data[3] => rom_data.DATAA
rom3_to_cbi_data[4] => rom_data.DATAA
rom3_to_cbi_data[5] => rom_data.DATAA
rom3_to_cbi_data[6] => rom_data.DATAA
rom3_to_cbi_data[7] => rom_data.DATAA
ram_to_cbi_data[0] => memory_data.DATAB
ram_to_cbi_data[1] => memory_data.DATAB
ram_to_cbi_data[2] => memory_data.DATAB
ram_to_cbi_data[3] => memory_data.DATAB
ram_to_cbi_data[4] => memory_data.DATAB
ram_to_cbi_data[5] => memory_data.DATAB
ram_to_cbi_data[6] => memory_data.DATAB
ram_to_cbi_data[7] => memory_data.DATAB
aux_to_cbi_data[0] => memory_data.DATAB
aux_to_cbi_data[1] => memory_data.DATAB
aux_to_cbi_data[2] => memory_data.DATAB
aux_to_cbi_data[3] => memory_data.DATAB
aux_to_cbi_data[4] => memory_data.DATAB
aux_to_cbi_data[5] => memory_data.DATAB
aux_to_cbi_data[6] => memory_data.DATAB
aux_to_cbi_data[7] => memory_data.DATAB
port_to_cbi_data[0] => cbi_to_up_data.DATAB
port_to_cbi_data[0] => cbi_to_ram_data.DATAA
port_to_cbi_data[0] => cbi_to_aux_data.DATAA
port_to_cbi_data[1] => cbi_to_up_data.DATAB
port_to_cbi_data[1] => cbi_to_ram_data.DATAA
port_to_cbi_data[1] => cbi_to_aux_data.DATAA
port_to_cbi_data[2] => cbi_to_up_data.DATAB
port_to_cbi_data[2] => cbi_to_ram_data.DATAA
port_to_cbi_data[2] => cbi_to_aux_data.DATAA
port_to_cbi_data[3] => cbi_to_up_data.DATAB
port_to_cbi_data[3] => cbi_to_ram_data.DATAA
port_to_cbi_data[3] => cbi_to_aux_data.DATAA
port_to_cbi_data[4] => cbi_to_up_data.DATAB
port_to_cbi_data[4] => cbi_to_ram_data.DATAA
port_to_cbi_data[4] => cbi_to_aux_data.DATAA
port_to_cbi_data[5] => cbi_to_up_data.DATAB
port_to_cbi_data[5] => cbi_to_ram_data.DATAA
port_to_cbi_data[5] => cbi_to_aux_data.DATAA
port_to_cbi_data[6] => cbi_to_up_data.DATAB
port_to_cbi_data[6] => cbi_to_ram_data.DATAA
port_to_cbi_data[6] => cbi_to_aux_data.DATAA
port_to_cbi_data[7] => cbi_to_up_data.DATAB
port_to_cbi_data[7] => cbi_to_ram_data.DATAA
port_to_cbi_data[7] => cbi_to_aux_data.DATAA


|MicroVIP|ports:PMUX
n[0] => Equal0.IN0
n[0] => Equal1.IN2
n[0] => Equal2.IN1
n[0] => Equal3.IN2
n[0] => Equal4.IN1
n[0] => Equal5.IN2
n[0] => Equal6.IN2
n[0] => Equal7.IN2
n[1] => Equal0.IN2
n[1] => Equal1.IN0
n[1] => Equal2.IN0
n[1] => Equal3.IN1
n[1] => Equal4.IN2
n[1] => Equal5.IN1
n[1] => Equal6.IN1
n[1] => Equal7.IN1
n[2] => Equal0.IN1
n[2] => Equal1.IN1
n[2] => Equal2.IN2
n[2] => Equal3.IN0
n[2] => Equal4.IN0
n[2] => Equal5.IN0
n[2] => Equal6.IN0
n[2] => Equal7.IN0
mrd_n => in_enb1.IN1
mrd_n => out_stb1.IN1
mrd_n => out_stb2.IN1
mrd_n => out_stb3.IN1
mrd_n => out_stb4.IN1
mrd_n => out_stb5.IN1
mrd_n => out_stb6.IN1
mrd_n => out_stb7.IN1
tpb => in_enb1.IN1
tpb => out_stb1.IN1
tpb => out_stb2.IN1
tpb => out_stb3.IN1
tpb => out_stb4.IN1
tpb => out_stb5.IN1
tpb => out_stb6.IN1
tpb => out_stb7.IN1
tpb => in_data3_latch[0].CLK
tpb => in_data3_latch[1].CLK
tpb => in_data3_latch[2].CLK
tpb => in_data3_latch[3].CLK
tpb => in_data3_latch[4].CLK
tpb => in_data3_latch[5].CLK
tpb => in_data3_latch[6].CLK
tpb => in_data3_latch[7].CLK
din[0] => out_data7[0].DATAIN
din[0] => out_data2[0].DATAIN
din[0] => out_data3[0].DATAIN
din[0] => out_data4[0].DATAIN
din[0] => out_data5[0].DATAIN
din[0] => out_data6[0].DATAIN
din[1] => out_data7[1].DATAIN
din[1] => out_data2[1].DATAIN
din[1] => out_data3[1].DATAIN
din[1] => out_data4[1].DATAIN
din[1] => out_data5[1].DATAIN
din[1] => out_data6[1].DATAIN
din[2] => out_data7[2].DATAIN
din[2] => out_data2[2].DATAIN
din[2] => out_data3[2].DATAIN
din[2] => out_data4[2].DATAIN
din[2] => out_data5[2].DATAIN
din[2] => out_data6[2].DATAIN
din[3] => out_data7[3].DATAIN
din[3] => out_data2[3].DATAIN
din[3] => out_data3[3].DATAIN
din[3] => out_data4[3].DATAIN
din[3] => out_data5[3].DATAIN
din[3] => out_data6[3].DATAIN
din[4] => out_data7[4].DATAIN
din[4] => out_data3[4].DATAIN
din[4] => out_data4[4].DATAIN
din[4] => out_data5[4].DATAIN
din[4] => out_data6[4].DATAIN
din[5] => out_data7[5].DATAIN
din[5] => out_data3[5].DATAIN
din[5] => out_data4[5].DATAIN
din[5] => out_data5[5].DATAIN
din[5] => out_data6[5].DATAIN
din[6] => out_data7[6].DATAIN
din[6] => out_data3[6].DATAIN
din[6] => out_data4[6].DATAIN
din[6] => out_data5[6].DATAIN
din[6] => out_data6[6].DATAIN
din[7] => out_data7[7].DATAIN
din[7] => out_data3[7].DATAIN
din[7] => out_data4[7].DATAIN
din[7] => out_data5[7].DATAIN
din[7] => out_data6[7].DATAIN
in_data2[0] => dout.DATAB
in_data2[1] => dout.DATAB
in_data2[2] => dout.DATAB
in_data2[3] => dout.DATAB
in_data2[4] => dout.DATAB
in_data2[5] => dout.DATAB
in_data2[6] => dout.DATAB
in_data2[7] => dout.DATAB
in_data3[0] => in_data3_latch[0].DATAIN
in_data3[1] => in_data3_latch[1].DATAIN
in_data3[2] => in_data3_latch[2].DATAIN
in_data3[3] => in_data3_latch[3].DATAIN
in_data3[4] => in_data3_latch[4].DATAIN
in_data3[5] => in_data3_latch[5].DATAIN
in_data3[6] => in_data3_latch[6].DATAIN
in_data3[7] => in_data3_latch[7].DATAIN
in_data4[0] => dout.DATAB
in_data4[1] => dout.DATAB
in_data4[2] => dout.DATAB
in_data4[3] => dout.DATAB
in_data4[4] => dout.DATAB
in_data4[5] => dout.DATAB
in_data4[6] => dout.DATAB
in_data4[7] => dout.DATAB
in_data5[0] => dout.DATAB
in_data5[1] => dout.DATAB
in_data5[2] => dout.DATAB
in_data5[3] => dout.DATAB
in_data5[4] => dout.DATAB
in_data5[5] => dout.DATAB
in_data5[6] => dout.DATAB
in_data5[7] => dout.DATAB
in_data6[0] => dout.DATAB
in_data6[1] => dout.DATAB
in_data6[2] => dout.DATAB
in_data6[3] => dout.DATAB
in_data6[4] => dout.DATAB
in_data6[5] => dout.DATAB
in_data6[6] => dout.DATAB
in_data6[7] => dout.DATAB
in_data7[0] => dout.DATAB
in_data7[1] => dout.DATAB
in_data7[2] => dout.DATAB
in_data7[3] => dout.DATAB
in_data7[4] => dout.DATAB
in_data7[5] => dout.DATAB
in_data7[6] => dout.DATAB
in_data7[7] => dout.DATAB


|MicroVIP|keypad:SWITCHES
stb => switch[0]~reg0.CLK
stb => switch[1]~reg0.CLK
stb => switch[2]~reg0.CLK
stb => switch[3]~reg0.CLK
stb => switch[4]~reg0.CLK
stb => switch[5]~reg0.CLK
stb => switch[6]~reg0.CLK
stb => switch[7]~reg0.CLK
stb => switch[8]~reg0.CLK
stb => switch[9]~reg0.CLK
stb => switch[10]~reg0.CLK
stb => switch[11]~reg0.CLK
stb => switch[12]~reg0.CLK
stb => switch[13]~reg0.CLK
stb => switch[14]~reg0.CLK
stb => switch[15]~reg0.CLK
select[0] => Decoder0.IN3
select[1] => Decoder0.IN2
select[2] => Decoder0.IN1
select[3] => Decoder0.IN0


|MicroVIP|tone:TONEGEN
clock => counter[0].CLK
clock => counter[1].CLK
clock => counter[2].CLK
clock => counter[3].CLK
clock => counter[4].CLK
clock => counter[5].CLK
clock => counter[6].CLK
clock => counter[7].CLK
clock => counter[8].CLK
clock => counter[9].CLK
clock => counter[10].CLK
enable => tone_out.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT
enable => counter.OUTPUTSELECT


|MicroVIP|pixie:PIXIE
clock_n => video_reg[0].CLK
clock_n => video_reg[1].CLK
clock_n => video_reg[2].CLK
clock_n => video_reg[3].CLK
clock_n => video_reg[4].CLK
clock_n => video_reg[5].CLK
clock_n => video_reg[6].CLK
clock_n => video_reg[7].CLK
clock_n => display_enable.CLK
clock_n => mc[0].CLK
clock_n => mc[1].CLK
clock_n => mc[2].CLK
clock_n => mc[3].CLK
clock_n => video~reg0.CLK
clock_n => state[0].CLK
clock_n => state[1].CLK
clock_n => state[2].CLK
clock_n => state[3].CLK
reset_n => clear_n.DATAIN
reset_n => lc[0].ACLR
reset_n => lc[1].ACLR
reset_n => lc[2].ACLR
reset_n => lc[3].ACLR
reset_n => lc[4].ACLR
reset_n => lc[5].ACLR
reset_n => lc[6].ACLR
reset_n => lc[7].ACLR
reset_n => lc[8].ACLR
reset_n => mc.OUTPUTSELECT
reset_n => mc.OUTPUTSELECT
reset_n => mc.OUTPUTSELECT
reset_n => mc.OUTPUTSELECT
reset_n => always0.IN0
reset_n => spulse.ACLR
reset_n => state.OUTPUTSELECT
reset_n => state.OUTPUTSELECT
reset_n => state.OUTPUTSELECT
reset_n => state.OUTPUTSELECT
reset_n => always5.IN1
sc[0] => Equal1.IN1
sc[0] => Equal12.IN1
sc[1] => Equal1.IN0
sc[1] => Equal12.IN0
tpa => mc.OUTPUTSELECT
tpa => mc.OUTPUTSELECT
tpa => mc.OUTPUTSELECT
tpa => mc.OUTPUTSELECT
tpa => state.OUTPUTSELECT
tpa => state.OUTPUTSELECT
tpa => state.OUTPUTSELECT
tpa => state.OUTPUTSELECT
tpa => rpulse.CLK
tpa => rpulse0.CLK
tpb => load.IN1
tpb => spulse.CLK
disp_on => display_enable.OUTPUTSELECT
disp_off => always0.IN1
di[0] => video_reg.DATAB
di[1] => video_reg.DATAB
di[2] => video_reg.DATAB
di[3] => video_reg.DATAB
di[4] => video_reg.DATAB
di[5] => video_reg.DATAB
di[6] => video_reg.DATAB
di[7] => video_reg.DATAB


|MicroVIP|spi:FLASH
reset_n => dout.OUTPUTSELECT
reset_n => dout.OUTPUTSELECT
reset_n => dout.OUTPUTSELECT
reset_n => dout.OUTPUTSELECT
reset_n => dout.OUTPUTSELECT
reset_n => dout.OUTPUTSELECT
reset_n => dout.OUTPUTSELECT
reset_n => dout.OUTPUTSELECT
reset_n => sdo.OUTPUTSELECT
reset_n => rxreg.OUTPUTSELECT
reset_n => rxreg.OUTPUTSELECT
reset_n => rxreg.OUTPUTSELECT
reset_n => rxreg.OUTPUTSELECT
reset_n => rxreg.OUTPUTSELECT
reset_n => rxreg.OUTPUTSELECT
reset_n => rxreg.OUTPUTSELECT
reset_n => rxreg.OUTPUTSELECT
reset_n => current.OUTPUTSELECT
reset_n => current.OUTPUTSELECT
reset_n => current.OUTPUTSELECT
reset_n => current.OUTPUTSELECT
reset_n => current.OUTPUTSELECT
reset_n => current.OUTPUTSELECT
reset_n => current.OUTPUTSELECT
reset_n => txreg.OUTPUTSELECT
reset_n => txreg.OUTPUTSELECT
reset_n => txreg.OUTPUTSELECT
reset_n => txreg.OUTPUTSELECT
reset_n => txreg.OUTPUTSELECT
reset_n => txreg.OUTPUTSELECT
reset_n => txreg.OUTPUTSELECT
reset_n => txreg.OUTPUTSELECT
clk4x => rxreg[0].CLK
clk4x => rxreg[1].CLK
clk4x => rxreg[2].CLK
clk4x => rxreg[3].CLK
clk4x => rxreg[4].CLK
clk4x => rxreg[5].CLK
clk4x => rxreg[6].CLK
clk4x => rxreg[7].CLK
clk4x => txreg[0].CLK
clk4x => txreg[1].CLK
clk4x => txreg[2].CLK
clk4x => txreg[3].CLK
clk4x => txreg[4].CLK
clk4x => txreg[5].CLK
clk4x => txreg[6].CLK
clk4x => txreg[7].CLK
clk4x => BitCount[0].CLK
clk4x => BitCount[1].CLK
clk4x => BitCount[2].CLK
clk4x => BitCount[3].CLK
clk4x => dout[0]~reg0.CLK
clk4x => dout[1]~reg0.CLK
clk4x => dout[2]~reg0.CLK
clk4x => dout[3]~reg0.CLK
clk4x => dout[4]~reg0.CLK
clk4x => dout[5]~reg0.CLK
clk4x => dout[6]~reg0.CLK
clk4x => dout[7]~reg0.CLK
clk4x => load_sync.CLK
clk4x => current~1.DATAIN
load => load_sync.DATAIN
din[0] => txreg.DATAB
din[1] => txreg.DATAB
din[2] => txreg.DATAB
din[3] => txreg.DATAB
din[4] => txreg.DATAB
din[5] => txreg.DATAB
din[6] => txreg.DATAB
din[7] => txreg.DATAB
sdi => rxreg.DATAB


