library verilog;
use verilog.vl_types.all;
entity pixie is
    generic(
        FETCH           : integer := 0;
        EXEC            : integer := 1;
        DMA             : integer := 2;
        INT             : integer := 3
    );
    port(
        clock_n         : in     vl_logic;
        reset_n         : in     vl_logic;
        sc              : in     vl_logic_vector(1 downto 0);
        tpa             : in     vl_logic;
        tpb             : in     vl_logic;
        disp_on         : in     vl_logic;
        disp_off        : in     vl_logic;
        di              : in     vl_logic_vector(7 downto 0);
        clear_n         : out    vl_logic;
        int_n           : out    vl_logic;
        efx_n           : out    vl_logic;
        dmao_n          : out    vl_logic;
        comp_sync_n     : out    vl_logic;
        video           : out    vl_logic;
        vsync_out       : out    vl_logic
    );
end pixie;
