// sync_ram.v
// (c) 2016-2017 David R. Hunter
// 02/07/16   D. Hunter
// 08/12/17		DH	- changed to 4K
//
// synchronous single port 4K byte RAM
// using the Altera TriMatrix memory
//

module sync_ram(data,addr,we,clk,q);
	 input	[7:0] data;
	 input	[11:0] addr;
	 input	we,clk;
	 output	[7:0] q;
	 
	 // initialize RAM with the CHIP-8 program
//	(* ram_init_file = "chip8.mif" *) reg [7:0] memdata[0:4095];
    reg     [7:0] memdata[0:4095];
    
	 // Variable to hold the registered read address
	 reg		[11:0] addr_reg;
	 
	 always @(posedge clk)
		begin
			if (we)
				memdata[addr] <= data;
			
			addr_reg <= addr;
		end
	 
	 // Continuous assignment implies read returns NEW data;
	 assign q = memdata[addr_reg];

endmodule
