library verilog;
use verilog.vl_types.all;
entity cbi is
    port(
        addr            : in     vl_logic_vector(6 downto 0);
        mwr_n           : in     vl_logic;
        rom_map         : in     vl_logic;
        alt_rom         : in     vl_logic;
        n0              : in     vl_logic;
        cbi_to_up_data  : out    vl_logic_vector(7 downto 0);
        up_to_cbi_data  : in     vl_logic_vector(7 downto 0);
        rom1_to_cbi_data: in     vl_logic_vector(7 downto 0);
        rom2_to_cbi_data: in     vl_logic_vector(7 downto 0);
        rom3_to_cbi_data: in     vl_logic_vector(7 downto 0);
        ram_to_cbi_data : in     vl_logic_vector(7 downto 0);
        aux_to_cbi_data : in     vl_logic_vector(7 downto 0);
        port_to_cbi_data: in     vl_logic_vector(7 downto 0);
        cbi_to_ram_data : out    vl_logic_vector(7 downto 0);
        cbi_to_aux_data : out    vl_logic_vector(7 downto 0);
        cbi_to_port_data: out    vl_logic_vector(7 downto 0);
        ram_we          : out    vl_logic;
        aux_we          : out    vl_logic
    );
end cbi;
