// sync_rom_ut4.v
// (c) 2017 David R. Hunter
// 08/11/17   D. Hunter
//
// synchronous single port 512 byte RAM
// using the Altera TriMatrix memory
//
//`define SIM

module sync_rom_ut4(data,addr,we,clk,q);
	 input	[7:0] data;
	 input	[8:0] addr;
	 input	we,clk;
	 output	[7:0] q;
	 
	 // initialize RAM with the UT4 monitor program

	// use this for simulation
`ifdef SIM
   reg     [7:0] memdata[0:511];

	initial
	begin
		$readmemh("math.mem",memdata);

	end
`else	
	(* ram_init_file = "ut4v.mif" *) reg [7:0] memdata[0:511];
`endif
	

	 
	 // Variable to hold the registered read address
	 reg		[8:0] addr_reg;
	 
	 always @(posedge clk)
		begin
			if (we)
				memdata[addr] <= data;
			
			addr_reg <= addr;
		end
	 
	 // Continuous assignment implies read returns NEW data;
	 assign q = memdata[addr_reg];

endmodule
