// sync_rom_ut4.v
// (c) 2017 David R. Hunter
// 09/01/17   D. Hunter
//
// synchronous single port 512 byte RAM acting as a ROM
// using the Altera TriMatrix memory
//

module sync_rom_ut4(data,addr,clk,q);
	 input		[7:0] data;
	 input		[8:0] addr;
	 input		clk;
	 output reg [7:0] q;
	 
	 // initialize RAM with the UT4 monitor program
	(* ram_init_file = "ut4v.mif" *) reg [7:0] memdata[0:511];
	 
	 always @(posedge clk)
		begin	
			q <= memdata[addr];
		end

endmodule
