library verilog;
use verilog.vl_types.all;
entity datapath is
    generic(
        OP_NOP          : integer := 0;
        OP_OR           : integer := 1;
        OP_AND          : integer := 2;
        OP_XOR          : integer := 3;
        OP_ADD          : integer := 4;
        OP_SD           : integer := 5;
        OP_SHR          : integer := 6;
        OP_SM           : integer := 7;
        OP_SHL          : integer := 8;
        OP_SLC          : integer := 9;
        OP_ADC          : integer := 12;
        OP_SDB          : integer := 13;
        OP_SRC          : integer := 14;
        OP_SMB          : integer := 15
    );
    port(
        clr_n           : in     vl_logic;
        load            : in     vl_logic;
        din             : in     vl_logic_vector(7 downto 0);
        clocks          : in     vl_logic_vector(9 downto 0);
        selects         : in     vl_logic_vector(15 downto 0);
        i               : out    vl_logic_vector(3 downto 0);
        n               : out    vl_logic_vector(3 downto 0);
        zf              : out    vl_logic;
        df              : out    vl_logic;
        dout            : out    vl_logic_vector(7 downto 0);
        ma              : out    vl_logic_vector(7 downto 0);
        ma1             : out    vl_logic_vector(7 downto 0)
    );
end datapath;
