# opcodes.py
# CDP1802 opcodes
# D. Hunter    6/17/14

# each instruction mnemonic contains a tuple (opcode, type)

# the opcode is the hex value of the instruction
# the type indicates the type of opcode
# types:
#	ctl	1 byte instruction
#       io      1 byte instruction with parameter
#	reg	1 byte instruction with register parameter
#	imm	2 byte instruction with immediate value following opcode
#	br	2 byte instruction with branch address low byte following opcode
#	lbr	3 byte instruction with full branch address following opcode

# note, alternate forms of instructions are included based on the 
# RCA MPM-201A User Manual for the CDP1802 COSMAC Microprocessor


TYPE_CTL = 0
TYPE_IO  = 1
TYPE_REG = 2
TYPE_IMM = 3
TYPE_BR  = 4
TYPE_LBR = 5

# opcode dictionary
ops = {	'IDL' :(0x00,TYPE_CTL),
	'LDN' :(0x00,TYPE_REG),
	'INC' :(0x10,TYPE_REG),
	'DEC' :(0x20,TYPE_REG),
	'BR'  :(0x30,TYPE_BR),
	'BQ'  :(0x31,TYPE_BR),
	'BZ'  :(0x32,TYPE_BR),
	'BDF' :(0x33,TYPE_BR),
	'BPZ' :(0x33,TYPE_BR),
	'BGE' :(0x33,TYPE_BR),
	'B1'  :(0x34,TYPE_BR),
	'B2'  :(0x35,TYPE_BR),
	'B3'  :(0x36,TYPE_BR),
	'B4'  :(0x37,TYPE_BR),
	'NBR' :(0x38,TYPE_BR),
	'SKP' :(0x38,TYPE_CTL),
	'BNQ' :(0x39,TYPE_BR),
	'BNZ' :(0x3A,TYPE_BR),
	'BNF' :(0x3B,TYPE_BR),
	'BM'  :(0x3B,TYPE_BR),
	'BL'  :(0x3B,TYPE_BR),
	'BN1' :(0x3C,TYPE_BR),
	'BN2' :(0x3D,TYPE_BR),
	'BN3' :(0x3E,TYPE_BR),
	'BN4' :(0x3F,TYPE_BR),
	'LDA' :(0x40,TYPE_REG),
	'STR' :(0x50,TYPE_REG),
	'IRX' :(0x60,TYPE_CTL),
	'OUT' :(0x60,TYPE_IO),
	'OUT1':(0x61,TYPE_CTL),
	'OUT2':(0x62,TYPE_CTL),
	'OUT3':(0x63,TYPE_CTL),
	'OUT4':(0x64,TYPE_CTL),
	'OUT5':(0x65,TYPE_CTL),
	'OUT6':(0x66,TYPE_CTL),
	'OUT7':(0x67,TYPE_CTL),
	'INP' :(0x68,TYPE_IO),
	'INP1':(0x69,TYPE_CTL),
	'INP2':(0x6A,TYPE_CTL),
	'INP3':(0x6B,TYPE_CTL),
	'INP4':(0x6C,TYPE_CTL),
	'INP5':(0x6D,TYPE_CTL),
	'INP6':(0x6E,TYPE_CTL),
	'INP7':(0x6F,TYPE_CTL),
	'RET' :(0x70,TYPE_CTL),
	'DIS' :(0x71,TYPE_CTL),
	'LDXA':(0x72,TYPE_CTL),
	'STXD':(0x73,TYPE_CTL),
	'ADC' :(0x74,TYPE_CTL),
	'SDB' :(0x75,TYPE_CTL),
	'SHRC':(0x76,TYPE_CTL),
	'RSHR':(0x76,TYPE_CTL),
	'SMB' :(0x77,TYPE_CTL),
	'SAV' :(0x78,TYPE_CTL),
	'MARK':(0x79,TYPE_CTL),
	'SEQ' :(0x7A,TYPE_CTL),
	'REQ' :(0x7B,TYPE_CTL),
	'ADDI':(0x7C,TYPE_IMM),
	'SDBI':(0x7D,TYPE_IMM),
	'SHLC':(0x7E,TYPE_CTL),
	'RSHL':(0x7E,TYPE_CTL),
	'SMBI':(0x7F,TYPE_IMM),
	'GLO' :(0x80,TYPE_REG),
	'GHI' :(0x90,TYPE_REG),
	'PLO' :(0xA0,TYPE_REG),
	'PHI' :(0xB0,TYPE_REG),
	'LBR' :(0xC0,TYPE_LBR),
	'LBQ' :(0xC1,TYPE_LBR),
	'LBZ' :(0xC2,TYPE_LBR),
	'LBDF':(0xC3,TYPE_LBR),
	'NOP' :(0xC4,TYPE_CTL),
	'LSNQ':(0xC5,TYPE_CTL),
	'LSNZ':(0xC6,TYPE_CTL),
	'LSNF':(0xC7,TYPE_CTL),
	'LSKP':(0xC8,TYPE_CTL),
	'NLBR':(0xC8,TYPE_LBR),
	'LBNQ':(0xC9,TYPE_LBR),
	'LBNZ':(0xCA,TYPE_LBR),
	'LBNF':(0xCB,TYPE_LBR),
	'LSIE':(0xCC,TYPE_CTL),
	'LSQ' :(0xCD,TYPE_CTL),
	'LSZ' :(0xCE,TYPE_CTL),
	'LSDF':(0xCF,TYPE_CTL),
	'SEP' :(0xD0,TYPE_REG),
	'SEX' :(0xE0,TYPE_REG),
	'LDX' :(0xF0,TYPE_CTL),
	'OR'  :(0xF1,TYPE_CTL),
	'AND' :(0xF2,TYPE_CTL),
	'XOR' :(0xF3,TYPE_CTL),
	'ADD' :(0xF4,TYPE_CTL),
	'SD'  :(0xF5,TYPE_CTL),
	'SHR' :(0xF6,TYPE_CTL),
	'SM'  :(0xF7,TYPE_CTL),
	'LDI' :(0xF8,TYPE_IMM),
	'ORI' :(0xF9,TYPE_IMM),
	'ANI' :(0xFA,TYPE_IMM),
	'XRI' :(0xFB,TYPE_IMM),
	'ADI' :(0xFC,TYPE_IMM),
	'SDI' :(0xFD,TYPE_IMM),
	'SHL' :(0xFE,TYPE_CTL),
	'SMI' :(0xFF,TYPE_IMM)
	}

# names of registers
register_names = {
		'R0': 0x00,
		'R1': 0x01,
		'R2': 0x02,
		'R3': 0x03,
		'R4': 0x04,
		'R5': 0x05,
		'R6': 0x06,
		'R7': 0x07,
		'R8': 0x08,
		'R9': 0x09,
		'RA': 0x0A,
		'RB': 0x0B,
		'RC': 0x0C,
		'RD': 0x0D,
		'RE': 0x0E,
		'RF': 0x0F
		}

# I/O port names
port_names = {
		'1': 0x01,
		'2': 0x02,
		'3': 0x03,
		'4': 0x04,
		'5': 0x05,
		'6': 0x06,
		'7': 0x07
		}