# output.py
# D. Hunter	9/7/14
# 10/23/14	drh - changed  genVerilogFile  to handle 32 bit words
# 10/25/14	drh - added zero option, added extended address record for intel hex
# 01/11/15	drh - moved from rasm.py.   change genVerilogFile back to bytes
# 08/12/17	drh - fix generator bug when zero flag and address jumps


# generate different file formats
# binary data consists of a list of tuples
#	[ (startAddr: binary string), (startAddr: binary string), ...]

# write binary file

# pad unused bytes with FFh
def genBinFile(filename, bdata):
	file = open(filename,'wb')
	lastAddr = 0
	for (a,bytes) in bdata:
		if a != lastAddr:
			for i in range(a - lastAddr):
				file.write('\xFF')			# pad with 'FF' (erased value in an EPROM)
		file.write(bytes)
		lastAddr = a + len(bytes)
	file.close()
	return

# write Intel Hex file
def genHexRecord(record, addr, type):
	reclen = len(record)
	cksum = 0
	
	outStr = ':%02X%04X%02X' % (reclen,addr,type)
	cksum = cksum + reclen
	cksum = cksum + (addr >> 8)
	cksum = cksum + (addr % 256)
	cksum = cksum + type
	
	for r in record:
		cksum = (cksum + ord(r)) % 256
		outStr = outStr + '%02X' %(ord(r))

	cksum = (-1*cksum) % 256
	outStr = outStr + '%02X' % (cksum)
	return(outStr)

def genHexFile(filename, bdata, zflg = False):
	file = open(filename, 'w')
	
	(a,bytes) = bdata[0]			# get first record	
	offset = a				# determine zero offset from first address
	
	for (a,bytes) in bdata:
		if (a > 0xFFFF):		# if larger than 16 bits
			xStr = ''
			xStr = xStr + chr((a >> 24) & 0xFF)
			xStr = xStr + chr((a >> 16) & 0xFF)	# get upper 16 bits
			outStr = genHexRecord(xStr,0,0x04)		# create extended addr record
			file.write(outStr+'\n')
			addr = a & 0xFFFF			# truncate address to lower 16 bits
		else:
			if zflg:
				addr = a - offset	# remove offset from address
			else:
				addr = a			

		records = []
		
		# break data into 16 byte records
		numbytes = len(bytes)
		numrec = numbytes / 16
		if (numrec * 16) < len(bytes):
			numrec = numrec + 1

		index = 0
		for i in range(numrec):
			rec = bytes[index:index+16]
			records.append(rec)
			index = index + 16
		
		# write the records out
		
		for r in records:
			outStr = genHexRecord(r,addr,0x00)
			file.write(outStr+'\n')
			addr = addr + len(r)
	
	# write end of file record
	outStr = genHexRecord('',0,0x01)
	file.write(outStr+'\n')
	
	file.close()
	return
	
	
# write verilog file
def genVerilogFile(filename, bdata, zflg = False):
	file = open(filename,'w')
	file.write('// Verilog Memory File\n')
	
	(a,bytes) = bdata[0]			# get first record	
	offset = a				# determine zero offset from first address
	
	for (a,bytes) in bdata:
		if not(zflg):
			file.write('@%04X\n' % (a))		# write address of record
		else:
			file.write('@%04X\n' % (a-offset))	# write address of record removing offset
		bcnt = 0					# byte count
		word = ''
		for b in bytes:
			file.write('%02X\n' % ord(b))
	file.close()
	return

	
# write Altera MIF format

# pad unused bytes with 00h 
def genAlteraFile(filename, bdata, zflg = False):
	file = open(filename,'w')
	
	#find start of data
	(a,bytes) = bdata[0]
	startAddr = a
	# find end of data
	(a,bytes) = bdata[-1]
	endAddr = a + len(bytes) 
		
	numbytes = endAddr - startAddr
	
	file.write('-- Memory Initialization File\n')
	file.write('DEPTH = %d;\n'%(numbytes))			# set size of memory
	file.write('WIDTH = 8;\n')					# always 8 bits/word
	file.write('ADDRESS_RADIX = HEX;\n')
	file.write('DATA_RADIX = HEX;\n')
	file.write('CONTENT\n')
	file.write('BEGIN\n')

	lastAddr = 0

	offset = startAddr			# determine zero offset from first address
	
	for (a,bytes) in bdata:
		if not(zflg):
			addr = a
		else:
			addr = a - offset

		if addr != lastAddr:
			padAddr = lastAddr
			for i in range(addr - lastAddr):
				file.write('%X : 00;\n' % (padAddr))	# pad empty space with '00'
				padAddr = padAddr + 1

		for b in bytes:
			file.write('%X : %02X;\n' % (addr,ord(b)))
			addr = addr + 1
		lastAddr = addr

	file.write('END;\n')
	file.close()
	return


# standard hex dump for verifying binary file
def dumpfile(data):
	addr = 0
	dataStr = str(data)
	print '%04X: ' % (addr),
	for d in dataStr:
		print '%02X ' % ord(d),
		addr = addr + 1
		if (addr % 16) == 0:
			print ''
			print '%04x: ' % (addr),
	print

# test
if __name__ == '__main__':
	bdata = 'The Quick Brown Fox Jumped Over The Lazy Dogs\r\n 012345'
	
	data= [(16,bdata),(160,bdata)]
	
	print 'creating binary file test.bin'
	genBinFile('test.bin',data)
	print 'done'

	print 'dumping binary file'
	file = open('test.bin','rb')
	bindata = file.read()
	file.close()
	dumpfile(bindata)
	
	print 'creating MIF file test.mif'
	genAlteraFile('test.mif',data)
	print 'done'
	
	print 'creating HEX file test.hex'
	genHexFile('test.hex',data)
	print 'done'
	
	print 'creating memh file test.mem'
	genVerilogFile('test.mem',data)
	print 'done'