/* Author : Gaurav Sharma h2016075@pilani.bits-pilani.ac.in
						Himanshu Shekhar h2016071@pilani.bits-pilani.ac.in. */

#ifndef __TIMER_H
#define __TIMER_H


#include <lpc214x.h>


/*Timer related stuff.*/
#define PLOCK 0x00000400
#define PRESCALE 60  //60000 PCLK clock cycles to increment TC by 1 

void _delay_us(long long);
void initClocks(void);
void initTimer0(void);
void setupPLL0(void);
void feedSeq(void);
void connectPLL0(void);
void _delay_ms(long long);


void _delay_ms(long long ms) {
	_delay_us(ms*1000);
}




void initTimer0(void)
{
    /*Assuming that PLL0 has been setup with CCLK = 60Mhz and PCLK also = 60Mhz.*/
   
    T0CTCR = 0x0;
    T0PR = PRESCALE-1; //(Value in Decimal!) - Increment T0TC at every 60 clock cycles
                     //Count begins from zero hence subtracting 1
                     //60 clock cycles @60Mhz = 1 uS

	T0TCR = 0x02; //Reset Timer
}

void _delay_us(long long microseconds) //Using Timer0
{
	T0TCR = 0x02; //Reset Timer

    T0TCR = 0x01; //Enable timer
   
    while(T0TC < microseconds); //wait until timer counter reaches the desired delay
   
    T0TCR = 0x00; //Disable timer
}

void initClocks(void)
{
    setupPLL0();
    feedSeq(); //sequence for locking PLL to desired freq.
    connectPLL0();
    feedSeq(); //sequence for connecting the PLL as system clock
   
    //SysClock is now ticking @ 60Mhz!
       
    VPBDIV = 0x01; // PCLK is same as CCLK i.e 60Mhz
}


//---------PLL Related Functions :---------------

void setupPLL0(void)
{
    //Note : Assuming 12Mhz Xtal is connected to LPC2148.
	
	PLL0CON = 0x01; // PPLE=1 & PPLC=0 so it will be enabled
                    // but not connected after FEED sequence
    PLL0CFG = 0x24; // set the multipler to 5 (i.e actually 4)
                    // i.e 12x5 = 60 Mhz (M - 1 = 4)!!!
                    // Set P=2 since we want FCCO in range!!!
                    // So , Assign PSEL =01 in PLL0CFG as per the table.
}

void feedSeq(void)
{
    PLL0FEED = 0xAA;
    PLL0FEED = 0x55;
}

void connectPLL0(void)
{
    // check whether PLL has locked on to the  desired freq by reading the lock bit
    // in the PPL0STAT register

    while( !( PLL0STAT & PLOCK ));

    // now enable(again) and connect
    PLL0CON = 0x03;
}
#endif