Name J090-U11 ; PartNo 00 ; Date 2019-02-22 ; Revision 01 ; Designer Engineer ; Company None ; Assembly J090 ; Location U11; Device g16v8a; /* ; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063) ; Copyright (c) National Semiconductor Corporation 1990-1993 ; Disassembled from J090-U11.JED. Date: 2-22-119 ;$GALMODE REGISTERED chip J090-U11 GAL16V8 ; ; This chip taken from SC88T version 1 issue 3. ; The SC88T went through several refinements ; and this is not the last one. ; ; This is the pinout for version 2 issue 3 ; 16V8-25 PLCC ; ; inputs: ; */ pin 1 = CPU_CLKOUT ; /* From CPU pin 56 via R9 */ pin 2 = !LK4 ; /* Selects 8K/32K decoding */ pin 3 = !PCS3 ; /* From CPU pin 29 */ pin 4 = !WR ; /* From CPU pin 63 */ pin 5 = BA13 ; /* For 8K memory chips */ pin 6 = !LCS ; /* From CPU pin 33 */ pin 7 = !BD0 ; /* From CPU D0 */ pin 8 = RESET ; /* From CPU */ pin 9 = BA15 ; /* For 32K memory chips */ pin 10 = GND ; pin 11 = !OE_GROUNDED ; /* */ /* ; these may be in or out: */ pin 12 = !CS_RAM0 ; /* U15 pin 20 == */ pin 13 = !CS_RAM1 ; /* U17 pin 20 == */ pin 14 = unused14 ; /* */ pin 15 = assert_ATOUT ; /* registered function. */ pin 16 = unused16 ; /* */ pin 17 = CLOCK_4MHZ ; /* SCC PCLK PLCC44 pin 23 (DIP40 pin 20) */ pin 18 = !PCS3_WRITE ; /* */ pin 19 = !ATOUT ; /* LK1 pin 1 == */ pin 20 = VCC ; /* */ /* ; My version 1 issue 3 board may have a different pinout. ; Pin 13 is an output, ; Equations look like the pinout is the same for both boards. */ PCS3_WRITE = PCS3 & WR ; /* 8 MHz CPU clock divided by 2 to drive SCC clock */ CLOCK_4MHZ.d = !CLOCK_4MHZ ; /* Writing a byte with D0 = 1 asserts /ATOUT (low) Do not read, as D0 will not be predictable. */ assert_ATOUT.d = PCS3_WRITE & !BD0 & !RESET /* assert */ # !PCS3_WRITE & !assert_ATOUT & !RESET ; /* latch it */ /* make it open-collector */ ATOUT = assert_ATOUT ; !ATOUT.oe = assert_ATOUT ; /* Link 4 selects RAM size. + LK4 open 8k RAM chips installed (e.g. 6264 or similar) LK4 made 32k RAM chips installed Could be replaced by using LCS to select one 512K RAM chip. */ CS_RAM0 = LCS & !LK4 & !BA15 /* 32K */ # LCS & LK4 & !BA13 ; /* 8K */ CS_RAM1 = LCS & !LK4 & BA15 /* 32K */ # LCS & LK4 & BA13 ; /* 8K */ /* Always true: CLOCK_4MHZ.oe = OE ; assert_ATOUT.oe = OE ; PCS3_WRITE.oe = vcc ; !CS_RAM1.oe = vcc ; !CS_RAM0.oe = vcc ; */ /* Always false: /unused16 = gnd ; unused16.oe = gnd ; /unused14 = gnd ; unused14.oe = gnd ; */