J041 SCPUB
The 16 MHz system clock is generated by part of IC7, divided by 4 by IC8 and buffered to NMOS levels by TR4 and 5, to drive the Z80 (IC15), DART (IC17) and CTC (IC16). An optional 16 MHz bus clock is also provided.
Logic array IC19 generates memory chip selects and wait states, based on the address, the state of LK5 A and B and the state of Q4 and Q5 of IC6. These bits when high disable on-board EPROM and RAM respectively. The lower 4 bits of IC6 (Q3-0) set the top 4 bits (A19-16) of the STE address bus. Logic array IC13 generates I/O chip selects, processes wait states and decides whether a bus access is to be made.
The Z80 takes 3 clock cycles for a data byte fetch compared to 4 clock cycles for a machine-code instruction fetch and decode. However, these 4 clock cycles include a dummy memory access for refreshing dynamic RAMs. Thus the opcode access time is shorter than the data byte access time. IC19 inserts one wait state to extend the opcode access time and so allow machine code to be run on slower EPROMs. If the EPROM has an access time less than 340ns then making LK5A removes these wait states and so accelerates machine-code on the SCPUB.
EPROMs (IC22, 23) can be 4, 8, or 16K, and there is one jumper per EPROM to set whether pin 26 is +5V or A13, depending on EPROM size. RAMs (IC20, 21) can be 2K or 8K, but both RAMs must be the same size. RAM power can either be from the +5V line on board, or from the standby power line for battery back-up.
The DART, IC17, is wired to connector PL3 via RS232 buffers IC12 and 18. Unbuffered lines at TTL levels also go from the DART to PL3. The CTC has counters 0 and 1 providing the baud rates for channels A and B respectively. The input of counter 2 is wired to /M1, for single-stepping and multiple-stepping through machine code. It does this by counting down on each instruction fetch and interrupting the Z80 after 1 to 256 instructions. Its output can be sent either to PL3 or to an ATNRQ* line on the bus for interrupt generation. The output of counter 3 does not go to an external pin on the CTC, so this counter can only generate interrupts. Its input can come from PL3 or an ATNRQ* line on the bus. The CTC has a higher interrupt priority than the DART.
Address and data lines on the bus are driven by IC1, 3, 4 and 5, with IC2 driving the strobes. Incoming bus signals are buffered by IC10. SYSRST* is an open collector line, driven by the on-board reset circuit (IC11, TR3), and other boards on the STEbus such as the SYSCON. IC11 will assert SYSRST* on power-up or manual reset or if the 5V supply falls below about 4.75V.