Links and Options
Note:
+ = the standard jumper connection
* = The signal is active-Low
There are many different ways in which you can configure the
SCPUB; they are selected by jumpering across links on the board.
The standard configuration is indicated by a + sign, and the
board is described as seen from the component side of the board,
with the 64-way bus connector to the right. A single asterisk (*)
against a signal name means that it is active-low.
Figure 1. SCPUB Link Positions

Link area 1. Bus
request/acknowledge level |
LK1 |
D Level request is on
BUSRQ0* |
o D o |
C Level request is on BUSRQ1* |
o C o |
B Acknowledge is from
BUSAK0* |
o B o |
A Acknowledge is from
BUSAK1* |
o A o |
NOTES
- Request and acknowledge must both be on the same level.
- You do not need to set these jumpers if LK6A1 is set.
- Standard configuration does not have any links in this area.
Link area 2. Attention requests
and bus clock
A ATNRQ0* to CPU non-maskable interrupt
+ B1 ATNRQ0* to ATIN line (see LK4)
B2 ATNRQ0* from ATOUT line (see LK4)
C1 ATNRQ1* to ATIN
+ C2 ATNRQ1* from ATOUT
D1 ATNRQ2* to ATIN
D2 ATNRQ2* from ATOUT
E1 ATNRQ3* to ATIN
E2 ATNRQ3* from ATOUT
+ F SYSCLK is from this CPU
|
LK2
|
Link area 4. CTC, I/O and memory
jumpering
A TRG3 input from PL3 pin 19
+ B TRG3 input from ATIN line (see LK2)
+ C ZC2 output to ATOUT line
D ZC2 output to PL3 pin 20
+ E1 RAM power is 5V on-board supply
E2 RAM power is standby line
+ F1 EPROM IC22 pin 26 to +5V - 2732 only
F2 EPROM IC22 pin 26 to A13 - 2764, 27128
+ G1 EPROM IC23 pin 26 to +5V - 2732 only
G2 EPROM IC23 pin 26 to A13 - 2764, 27128 only
|
LK4
o
G1
o
G2
o |
o
F1
o
F2
o |
o
E1
o
E2
o |
|
|
|
|
Link area 5 RAM size and EPROM
wait states
A 8K
B no wait states on EPROM
|
|
For RAM size refer also to LK6.
Link area 6 external bus
arbitration and RAM size (see also LK4)
+ A1 Do not use external arbiter
Note: This option is only possible if this CPU is
the only bus master. External arbitration must be
used if there is more than one CPU or other type
of bus master in the system. This is available
from the SCPUA board.
A2 Take in BUSACK from external arbiter
+ B1 RAM pins 23 are /WR (2K RAMs)
B2 RAM pins 23 are A11 (8K RAMs) CPU
|
|
CAUTION
Changes to link area 7 should only be carried out by suitably
qualified service personnel since poor workmanship may invalidate
the guarantee.
Link area 7 serial input on
channel A of the DART
LK7
+ A Serial input is at RS232 Levels. The link is hard-wired in this position.
B Serial input is inverted and at TTL Levels.
This allows a serial encoded keyboard to be used.
CAUTION
If an RS232 device is connected to the input with the link in
this state, the DART will be destroyed.
Connector PL4 Reset Options
A Connect a normally open pushbutton switch across A for manual reset.
B Insert a jumper across these pins to take in SYSRST* from the bus.
C Insert a jumper across these pins to send SYSRST* to the bus.
The SCPUB must have only one source of a reset; either from
the reset switch or from the bus.