J041 SCPUB

STEbus Interface

The SCPUB has an STEbus interface (IEEE1000). Here is a summary of the features of the bus with some notes on the implementation on the SCPUB.

Table 1. STEbus Interface on the SCPUB

Key:	*	= signal is active low
	3s	= tri-state 
	tp	= totem-pole 
	o/c	= open-collector
Signal In/Out type description implementation
A0-19 O 3s 20-bit memory address A15-0 are driven directly from the Z80.
A19-16 are bank-switch bits Q3-0 from the control latch.
A0-11 O 3s 12-bit I/O address Driven direct from the Z80. Note that the top 4 bits will depend on the I/O instruction used. To ensure they are set to a known value, use an indirect I/O instruction such as OUT (C),reg . These instructions put the BC register pair on A15-0.
A0-2 O 3s 3-bit acknowledge address The SCPUB does not handle bus-vectored interrupts, so it does not generate acknowledge cycles. It does respond to non-vectored interrupts on lines ATNRQ0*-ATNRQ3* if appropriately jumpered.
D0-7 I/O 3s 8-bit data bus Driven by the CPU on write cycles, or by the slave on read cycles.
ADRSTB* O 3s Address strobe Addresses must be valid thoughout ADRSTB* active.
DATSTB* O 3s Data strobe Initiates the transfer of data.
CM2—0 O 3s   Command modifiers indicating the type of bus cycle, according to the following table.
CM2,1,0
  1 1 1 memory read
  1 1 0   " write
  1 0 1 I/O read
  1 0 0  " write
  0 1 1 acknowledge
  0 1 0 )
  0 0 1 )reserved
  0 0 0 )

(note: the acknowledge cycle is not generated by the SCPUB )

BUSRQ0-1* O o/c Bus request Potential (temporary) bus masters request the bus from the arbiter on either of these lines. BUSRQ0* has a higher priority than BUSRQ1*
BUSAK0-1* I in Bus acknowledge The arbiter acknowledges a request from one of two potential masters on these lines. A potential master may drive the bus only after it has received an acknowledge on the line corresponding to its request.

The SCPUB can be jumpered either to take control of the bus completely, or it can be set up as a potential master that requests the bus from the permanent master or a separate arbiter. If it is set up to take complete control of the bus it ignores the BUSAK* lines, and assumes that it always has control of the bus whenever it wants it. In this case the SCPUB must be the only master on the bus. If you wish to use more than one SCPUB on the bus then you must have an external arbiter, such as the SYSCON board. See "Links and Options" for details of how to set up the board.

Signal In/Out type description implementation
DATACK* I o/c Handshake The slave addressed by the master asserts this line to indicate data accepted (write cycle) or data valid (read cycle).
TRFERR* I o/c Handshake If data from the slave are wrong ( for example a parity error ) the slave asserts TRFERR* instead of DATACK*. The SCPUB responds identically to both signals, as if no error had occurred. This signal exists in the specification for compatibility with future advances in system design.
ATNRQ0~7* I o/c Interrupts Attention request lines.
It is suggested that ATNRQ0—3 are reserved for interrupts, and
ATNRQ3-7* reserved for DMA, with ATNRQ0* having highest priority.
ATNRQ3-7* are ignored by the SCPUB.
SYSCLK O tp Clock 16MHz system clock.
May be generated by the SCPUB, or taken from the bus.
SYSRST* O o/c Reset System reset. The SCPUB may either generate this signal or take it from the bus.

It is quite easy to use the SCPUB on the STEbus. You will need a terminated backplane and one or more slave (peripheral) boards, such as A/D converters. In order to comply fully with the specification, the impedance of each backplane line should be 60 ohms +/- 10%. However, a short backplane is not likely to cause any malfunction even if its impedance varies considerably from this. A terminator is necessary because some of the lines are open-collector, and timing is critical on the strobes. Suitable terminated backplanes are available from Arcom.

An SCPUB configured as standard will generate all necessary bus signals as a permanent master. All that is required to generate a bus access is that you try to read or write to a memory or I/O location that the on-board logic defines as on the bus. See the "Memory Map" and "I/O Devices" sections for details on which addresses are on-board and which are not.

Note: If the slave board which you are attempting to access does not respond, for example if you used the wrong address, the SCPUB will "hang" in a wait state. To get out of this you can short DATACK* (see Appendix B) to ground temporarily.

The STEbus has a 12-bit I/O address space and the Z80 normally uses 8-bit I/O addressing, but by using indirect I/O instructions (e.g. IN reg,(C) or OUT (C),reg ) the register pair BC appears on A15-A0, allowing the Z80 to access a 12-bit I/O space.

Note that some Z80 block I/O instructions will use register B as a counter, and direct I/O instructions (such as IN A,(n) or OUT (n),A ) place the contents of the accumulator on A15-A8. Arcom I/O boards can be set up to ignore these address lines to permit these instructions and thus ease programming.

IF THE SCPUB 'HANGS' ON A BUS ACCESS

Check the following:

Is DATSTB* permanently low and DATACK* and TRFERR* high ?

If so this means the SCPUB is waiting for a slave to respond.
Check the slave is residing at the correct I/O address.
This is the most common mistake.

If the slave is present at the right address then check that SYSCLK is present on the bus, as many slave boards require this for timing, and check also that SYSCLK is coming from only one source, if you have two CPUs on the bus.

Are the address and data lines enabled?

If not, the SCPUB has not gained access to the bus. This may be because some other master already has access to the bus and has not released it. Check the state of BUSRQ* and BUSAK* ,and jumper LK6.