J041 SCPUB
The SCPUB was designed in the early 1980's, when SRAM was expensive. It took a pair of 2K or 8K SRAM chips, located in the high addresses (F000 or C000 hex). EPROM began at 0000 hex. CP/M requires RAM from 0000 hex upward. When switched out, the ROM area becomes STEbus accesses, so CP/M required STEbus RAM
See the original memory map.
The SCPUB was designed in the early 1980's, when SRAM was expensive. It took a pair of 2K or 8K SRAM chips, located in the high addresses (F000 or C000 hex). EPROM began at 0000 hex. CP/M requires RAM from 0000 hex upward. When switched out, the ROM area becomes STEbus accesses, so CP/M required a STEbus RAM board.
The memory map can be altered by three options:
The memory map can be altered by three options:
Start End | Cold boot All ROM |
After first jump A15 high |
After ROM disabled |
Paged 16K active | |||
0K | 0000 7FFF |
IC20 (32K ROM) | IC22 (32K RAM) | ||||
16K | 4000 7FFF |
||||||
32K | 8000 BFFF |
IC20 (32K ROM) | IC23 (32K RAM) | Paged RAM |
Paged ROM |
Paged STEbus |
|
48K | C000 FFFF |
IC20 or IC23 (top 16K) |
1. Cold Boot
The ROM begins at address 0000 hex.
The Acorn Z80 2nd processor does this:
RESET: ; ; On RESET, ROM is paged into low memory. ; ; ROM is paged out by an instruction fetch ; from an address in the top 32K of memory. ; ; Copy code from low memory to high memory: ; DI LD DE,RESET ; Destination in high memory LD HL,&0000 ; Source in low memory LD BC,&1000 ; Byte Count is 4K LDIR ; Copy code JP STARTUP ; Enter code in high memory
The address that is put on the bus during memory bus accesses is the same as the Z80 address: there is no translation. The Z80 address is 16 bits, however, and the STEbus address is 20 bits. The extra four bits come from the control latch, and these should be set to the correct value before the bus access is attempted.
Avoid switching memory from a program running in an area of memory that will be switched out, because the program will disappear as soon as the memory is switched!