J041 SCPUB

Introduction

The SCPUB board is a low-cost, expandable Z80A processor board. It has enough processing power to act as the main CPU in a large control system, and uses the industry-standard STEbus. A lot of software exists for the popular Z80 microprocessor, especially under the CP/M operating system. A machine-code monitor EPROM (EAMON), a BASIC language interpreter, and a BASIC compiler (both in EPROM or disk) are available for the SCPUB.

The SCPUB is a general-purpose computer, and can be used for any application (given the right software) from word processing to plant control. The board is optimised for use as the 'target' machine in a control system. That is, software will probably be developed on a 'host' system with disks and high-level languages or assemblers, then blown into EPROM or downloaded into RAM on the SCPUB for debugging. When the software is fully de-bugged, it can be blown into EPROM so that the SCPUB is a stand-alone controller. To reduce the cost of the board, it is supplied without software. The machine-code monitor is useful for hex entry and debugging of small amounts of machine code. The BASIC compiler is used when the development does not warrant a separate host system. The program is written in BASIC in RAM, then saved in EPROM using the STEbus EPROM programmer.

The SCPUB itself can be used as the 'host' system, by the addition of extra RAM, disk drives, floppy disk controller, operating system and terminal. Software development toots can be obtained from the vast CP/M library.

The SCPUB has a large memory capacity. Up to 32K EPROM and 16K RAM can be used on the board, as two EPROMs of 4,8 or 16K each and two CMOS or NMOS RAMS of 2K or 8K. As standard, the board is supplied with two 2K RAMs. A powerful feature of the memory system is the ability to switch on-board EPROM or RAM out of the memory map under software control so that memory accesses are made via the bus. This at lows the SCPUB to access up to 1MB of external memory.

On-board I/O is designed for communications and real-time control. There is a dual asynchronous receiver-transmitter (DART) which gives two serial channels with RS232 buffers. Baud-rates can be set from software by using the counter-timer circuit (CTC), which has four counter-timers. Two of these are normally used for baud-rate generation, leaving the other two free for generating or receiving bus or I/O interrupts or counting instruction cycles.

The sophisticated Z80 daisy-chain interrupt system is used on-board the SCPUB, with bus interrupts ("Attention requests") going into the CTC so that a vector can be generated automatically. This means that interrupt-driven systems with real time clocks can be implemented with no extra hardware.

The STEbus interface is an important feature of the SCPUB. The bus has the IEEE designation P1000, and is designed as a processor- and manufacturer-independent, asynchronous, multiprocessing bus. The asynchronous nature of the bus means that the SCPUB must wait until the stave board (memory or I/O) must acknowledge commands. This allows any speed of peripheral board to be accessed by any speed of CPU board, an important feature in 'future-proofing' the STEbus The multiprocessing ability allows several CPU boards to share peripherals on the same bus. This is explained in greater detail later on.