J041 SCPUB
There are three I/O devices on the board - the control latch, the DART and the CTC. The following table shows the addresses of I/O devices.
I/O Address | ||
Decimal | Hex | |
0 | 00 | Control Latch |
4 | 04 | DART |
8 | 08 | CTC |
12 | 0C | Not used |
16 | 10 | Repeat of 00-0F |
32 | 20 | Repeat of 00-0F |
48 | 30 | Repeat of 00-0F |
64 to 255 |
40 FF |
STEbus |
The control latch is at I/O address 0, and sets the top 4 bits of the STEbus memory address and whether on-board RAM and EPROM are enabled. At reset the latch is zeroed, enabling on-board memory and setting the bus address to zero.
0 | Control latch | ||||||||||||||||||||||||||||||||||||||||||||||||||||
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1 | Control latch also appears here, | ||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | here, | ||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | and here. | ||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | DART channel B control | ||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | DART channel A control | ||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | DART channel B data | ||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | DART channel A data | ||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | CTC counter timer 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | CTC counter timer 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||
A | CTC counter timer 2 | ||||||||||||||||||||||||||||||||||||||||||||||||||||
B | CTC counter timer 3 |
It is recommended that you obtain the Zilog CTC Technical Manual and the Zilog DART Technical Manual before programming the CTC and DART.
The chip selects for the on-board I/O devices are not fully decoded, so they can be accessed at addresses from 0 to 3F (all addresses are in hexadecimal). Any attempt to access an I/O location above 40 will result in a bus access. Note that STEbus I/O addresses are 12 bits, whereas the Z80 has an 8 bit I/O address range. As explained in Section 3, it is possible to generate the top 4 bits for a bus I/O access. If there is no device on the bus that can respond to the address, the CPU will go into a wait state - in an emergency, short the DATACK* line to ground temporarily.