; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063) ; Copyright (c) National Semiconductor Corporation 1990-1993 ; Disassembled from J041-U13.jed. Date: 2012-10-28 ; ; This chip taken from SCPUB version 1 issue 5. ; ; chip J041-U13 PAL20L10 /RD = 1 ; from CPU DTACK = 2 DTERR = 3 A2 = 4 ; from CPU A3 = 5 ; from CPU /IORQ = 6 ; from CPU /MBUS = 7 ; from PAL, U19 /BG = 8 ; from STEbus, Bus Grant. /ENDEL = 9 ; /ENDR delayed by >= 40ns /MREQ = 10 ; from CPU A6 = 11 ; from CPU GND = 12 A7 = 13 ; from CPU /LAT = 14 ; /AS = 15 ; /BUS = 16 ; /ENDR = 17 ; /DS = 18 ; /DART = 19 ; to DART CS /CTC = 20 ; to CTC CS /CYEND = 21 /M1 = 22 ; from CPU /BWT = 23 ; Bus Wait VCC = 24 equations ; ; Bus wait ; BWT = BUS * /BG * + BUS * BG * /CYEND + MBUS * /BG ; ; Cycle end ; CYEND = BUS * DTACK * BG + BUS * DTERR * BG + BUS * CYEND ; ; Onboard Counter/Timer chip ; CTC = IORQ * /M1 * /A7 * /A6 * A3 * /A2 ; ; Onboard serial I/O ; DART = IORQ * /M1 * /A7 * /A6 * /A3 * A2 ENDR = /CYEND * BG * BUS + AS ; ; Detect valid STEbus ; BUS = IORQ * /M1 * A7 + IORQ * /M1 * /A7 * A6 + MBUS ; ; STEbus Address Strobe ; AS = /DTACK * /DTERR * /CYEND * ENDEL * BUS + DS * IORQ ; hold if data strobe I/O + DS * MREQ ; hold if data strobe memory ; ; STEbus Data Strobe ; DS = BG * BUS * AS * /RD * /CYEND * ENDR + BG * BUS * AS * RD * IORQ + BG * BUS * AS * RD * MREQ ; ; Onboard control latch. ; LAT = /M1 * IORQ * /A7 * /A6 * /A3 * /A2 /BWT.oe = vcc /CYEND.oe = vcc /CTC.oe = vcc /DART.oe = vcc /DS.oe = vcc /ENDR.oe = vcc /BUS.oe = vcc /AS.oe = vcc /LAT.oe = vcc