; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063) ; Copyright (c) National Semiconductor Corporation 1990-1993 ; Disassembled from J191-V1-DATACK-U11-AMDPALCE22V10H-25-CS10F72.JED. Date: 2022-03-12 ; Board: J191 version 1 issue 3 ; ; Location: U11 ; ; Function: data bus interface manager ; ; This seems to be complicated logic for converting ; 16-bit CPU accesses into two STEbus cycles when required. ; One byte needs to be held in a latch (U1, a 74ACT646) ; while the other is transferred. ; ; Status: disassembled from JEDEC data from PAL, partially analysed, not tested yet. ; ; chip J191-U11 PAL22V10 ; ; CLK =1 ; TRFERR =2 ; DATACK =3 ; LK15 =4 ; permanently grounded /UDS =5 ; CPU pin 7 /LDS =6 ; CPU pin 8 /STEbus =7 ; U23 pin 21 /AS =8 ; CPU pin 6 RnW =9 ; i10 =10 ; i11 =11 ; GND =12 ; /bus_granted =13 ; U13 pin 19 /STE_data_enable =14 ; STEbus data buffer enable CPAB_of_U1 =15 ; read STEbus D15..8 to the latch ? /G_of_U1 =16 ; enable the latch ? /q17 =17 ; /f18 =18 ; /f19 =19 ; f20 =20 ; /STE_address_enable =21 ; STEbus address buffer enable ADRSTB =22 ; STEbus DATSTB =23 ; STEbus VCC =24 equations ; ; Intermediate expressions: ; lower_byte_transfer = /UDS * LDS upper_byte_transfer = UDS * /LDS whole_word_transfer = UDS * LDS reading = RnW writing = /RnW DATSTB = STE_address_enable * upper_byte_transfer * ADRSTB * STEbus + STE_address_enable * lower_byte_transfer * ADRSTB * STEbus + STE_address_enable * whole_word_transfer * ADRSTB * STEbus * /f20 * /DATACK * /CPAB_of_U1 + STE_address_enable * whole_word_transfer * ADRSTB * STEbus * f20 + STE_address_enable * whole_word_transfer * DATSTB * STEbus * f20 ADRSTB := STE_address_enable * upper_byte_transfer * AS * STEbus + STE_address_enable * lower_byte_transfer * AS * STEbus + STE_address_enable * whole_word_transfer * AS * /f20 * /CPAB_of_U1 + STE_address_enable * whole_word_transfer * AS * f20 * /ADRSTB * /DATACK + DATSTB * ADRSTB STE_address_enable = STEbus * bus_granted + ADRSTB * STE_address_enable ; latching if ADRSTB f20 = lower_byte_transfer * STEbus + whole_word_transfer * STEbus * /ADRSTB * CPAB_of_U1 + f20 * CPAB_of_U1 + ADRSTB * f20 ; latching f19 = UDS * DATSTB * TRFERR * STEbus + LDS * DATSTB * TRFERR * STEbus + UDS * /LK15 * i10 * i11 + LDS * /LK15 * i10 * i11 + LDS * f19 ; latching + UDS * f19 ; latching f18 = upper_byte_transfer * DATSTB * DATACK + lower_byte_transfer * DATSTB * DATACK + whole_word_transfer * DATSTB * DATACK * f20 + UDS * f18 ; latching + LDS * f18 ; latching /f18.oe = STEbus * AS q17 := LDS * STEbus * bus_granted * DATSTB + upper_byte_transfer * STEbus * bus_granted * DATSTB + LDS * /STEbus + upper_byte_transfer * /STEbus ; ; enable the 74ACT646 latch/buffer ; G_of_U1 = upper_byte_transfer * STEbus * bus_granted + whole_word_transfer * STEbus * bus_granted * writing* /f20 + whole_word_transfer * STEbus * bus_granted * reading + UDS * G_of_U1 * DATSTB * writing * /f20 + UDS * G_of_U1 * DATSTB * reading ; ; clock pulse (A to B side) of the 74ACT646 latch/buffer. ; A side is STEbus, B side is D0-7 of CPU. ; ; The STEbus spec says you may only present one LS TTL load. ; This design uses an ACT '646 and the '245 which present smaller loads than LS logic. ; CPAB_of_U1 = STEbus * DATACK * ADRSTB + STEbus * CPAB_of_U1 ; latch this signal STE_data_enable = lower_byte_transfer * STEbus * bus_granted + whole_word_transfer * STEbus * bus_granted * writing * f20 + whole_word_transfer * STEbus * bus_granted * reading + LDS * reading * STE_data_enable * DATSTB + LDS * writing * STE_data_enable * DATSTB * f20 /STE_data_enable.oe = vcc /f19.oe = vcc /q17.oe = vcc f20.oe = vcc CPAB_of_U1.oe = vcc /G_of_U1.oe = vcc DATSTB.oe = vcc ADRSTB.oe = vcc /STE_address_enable.oe = vcc