; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063)
; Copyright (c) National Semiconductor Corporation 1990-1993
; Disassembled from J191-V1-I3-U7-Cypress-PALCE16V8-15P-CS51C5.jed. Date: 2022-03-12
;$GALMODE REGISTERED
;
; Board: J191 version 1 issue 3
; 
; Location: U7
;
; Function: interrupt priority encoder.
;
; Status: disassembled from JEDEC data from PAL, but not tested yet.
;
; IPLn signals are clocked, unlike the 68008 board PAL.
;
chip J191-U7 GAL16V8
;
;
CLK	=1 
/AS	=2	; CPU address strobe

/ATN0	=3	; from LK9
/ATN1	=4	; from LK8
/ATN2	=5	; from LK7
/ATN3	=6	; from LK6
/ATN4	=7	; from LK5
/ATN5	=8	; from LK4
/ATN6	=9	; from LK3

GND	=10	; 
/OE	=11	; grounded on the board, so always enabled.
FC2	=12	; input
FC1	=13	; input

/IPL0	=14
/IPL1	=15
/IPL2	=16	; interrupt priority level

/INTA	=17	; output to CPU /VPA  

FC0=18	; input

/FC210_INTACK=	19	; FC0 * FC1 * FC2

VCC=20 

@ues 4488782a8001fe00
@ptd unused

equations
;
; intermediate
interrupt_acknowledge_cycle	=	FC2 * FC1 * FC0
;
; Goes to PAL 23 and 24.
;
FC210_INTACK	= interrupt_acknowledge_cycle

INTA	= /AS * IPL2 * interrupt_acknowledge_cycle
	+ /AS * IPL1 * interrupt_acknowledge_cycle
	+ /AS * IPL0 * interrupt_acknowledge_cycle
	+ AS * INTA


; IPL	ATN
; 210	0 1 2 3 4 5 6 7		ATN	IPL
;
; 111	1 x x x x x x x		0	7	; highest priority
; 110	0 1 x x x x x x		1	6
; 101	0 0 1 x x x x x		2	5
; 100	0 0 0 1 x x x x		3	4
; 011	0 0 0 0 1 x x x		4	3
; 010	0 0 0 0 0 1 x x		5	2
; 001	0 0 0 0 0 0 1 x		6	1
; 000	0 0 0 0 0 0 0 1		7	0
; 
;
IPL2	:= ATN0
	+ ATN1
	+ ATN2
	+ ATN3


IPL1	:= ATN0
	+ ATN1
	+ /ATN2 * /ATN3 * ATN4
	+ /ATN2 * /ATN3 * ATN5

IPL0	:= ATN0
	+ /ATN1 * ATN2
	+ /ATN1 * /ATN3 * ATN4
	+ /ATN1 * /ATN3 * /ATN5 * ATN6

/FC210_INTACK.oe	= vcc
/INTA.oe		= vcc

/IPL2.oe	= OE
/IPL1.oe	= OE
/IPL0.oe	= OE

/FC0	= gnd
FC0.oe	= gnd
/FC1	= gnd
FC1.oe	= gnd
/FC2	= gnd
FC2.oe	= gnd