The Arcom SFDC is a floppy disk controller board for STEbus based computer systems. It can control up to four disk drives, each of which can be 3.5 inch or 5.25 inch double sided, double density or 8-inch single sided, single density. The SFDC has onboard a bank of 8 switches that processors can read to select these options when booted.
One big advantage of having a separate disk drive controller in a system is that the development and target systems can use the same processor(s) and peripherals, the only difference being that in some target systems there is no need for mass storage, and so the floppy disk controller board can be left out, thus reducing the target system cost.
The I/O address of the board is determined by the jumpers in LK3. When connected they each pull one input of IC2 – an octal comparator – low; when disconnected the inputs are pulled high by RP1. IC2 compares these inputs with address lines A11 to A4, and when they are equal and it is enabled by ADRSTB* going low (signifying a valid address), it activates the ADR* input of IC4, a custom PAL chip. IC4 starts the cycle if the CM lines, address lines A1 to A3, and DATSTB* line are correct, sending its TRIG* output low. IC9 – a D-type flip flop – gates this signal with DATSTB* (to ensure that the STE timing requirements for the removal of DATSTB* are maintained) and sends it to the serial inputs of IC11 – a shift register – from where three outputs return to the PAL to provide timing information for the cycle.
Depending on the state of the three address lines during the cycle, three types of access are supported:
(at BASE to BASE+3); A normal read/write operation to the SFDC chip is performed, regardless of its internal state (as indicated by INTRQ and DRQ on pins 39 and 38 of IC10).
(at BASE+4 to BASE+7): The access to the SFDC 'hangs' until the chip indicates either that it has finished the last command (INTRQ going high), or that it needs more data (DRQ going high). These two lines are logically 'OR'd and fed to pin 4 of IC4 as 'XRQ'. Once this signal has been given, the access continues as normal.
(at BASE+8): Writing to this location controls the four DRIVE SELECT outputs, double density enable, side select, 5.25" or 8" operation and enabling of the interrupt response. IC5 and IC8 form a bi-directional octal buffer, and are enabled by IC4 during an access. IC13 and associated circuitry provides a programmable divide-by-8 or divide-by-16 clock to the FDC chip.
Reading this location returns a binary value corresponding to the state of the eight DIL switches on the board. This is intended to allow any CPU using the board to determine the system configuration on power-up for example, drive type, step rate etc. Arcom reserves the right to allocate its own meaning to these switches.
Check the appropriate software manual for details of how to set these switches.
NOTE: The rather unusual step of using unidirectional buffers (IC5 and IC8) instead of a bidirectional buffer such as a 74LS245 (see appendix A and D) was taken because there are four types of disk controller chip that can be used with the SFDC board, and two of these have inverting data buses, and two don't. There is no inverting equivalent of the 'LS245 currently available, so two separate buffers had to be used. This was all done to ensure that the supply of boards from Arcom will not be affected by a shortage of any one of these controller chips.