J64 SFDC

Appendix D. 279X Disk Controller IC Data

This appendix contains information for those software design engineers who need to go deeper into the working of the disk controller board hardware for specialist applications. For normal use of the board, sufficient information is provided in Section 5.

The Arcom SFDC has been designed to accept any of the four 279X series of floppy disk controller ICs during manufacture, to avoid production supply problems. The function of the board is always the same and software will run with any controller IC provided that the two restrictions noted at the end of Table 5 are observed. Those features not present on certain versions of the ICs are always implemented on the board. The differences between the four ICs are detailed in the table below:

Table 4. Controller IC Features.

Features 2791 2793 2795 2797
Single Density (FM) * * * *
Double Density (MFM) * * * *
True Data Bus   *   *
Inverted Data Bus *   *  
Side Select Out     * *
Internal CLK Divide * *    

The inverted/ true data bus options provided by the 279X chip. are catered for by varying IC5 and IC8 (see Appendix A). The main difference between the 2791/3 and the 2795/7 is the function of pin 25. On the 2791/3 it is used as an ENMF (enable mini-floppy) input i.e. 5.25 inch as opposed to 8 inch drives. A logic Low on this input enables an internal divide by 2 of the Master Clock. This allows both 5.25 inch and 8 inch drive operation with a single 2MHz clock. For a 1MHz clock on pin 24 of the IC this pin must be left open or tied to a logic 1. On the 2795/7 the function of pin 25 is different. It is used as a side select output for double-sided drives. On the Arcom SFDC these functions are controlled by setting bits in the Port Control Register on the board. Further information regarding the controller IC including command and status descriptions can be found in the data sheet for the 2797 controller IC. The 2791/3 i.c.'s have a slightly different command summary than the 2795/7 ICs. The command register is located at address BASE (refer to Section 5).

Command Description

The WD2797 will accept eleven commands. Command words should only be loaded in the Command Register when the Busy status bit is off (Status bit 0). The one exception is the Force interrupt command. Whenever a command is being executed, the Busy status bit is set. When a command is completed, an interrupt is generated and the Busy status bit is reset The Status Register indicates whether the completed command encountered an error or was fault free. For ease of discussion, commands are divided into four types. Commands and types are summarised below.

Table 5. Command Summary.

			For 2791, 2793		For 2795, 2797
Type	Command		bit			bit
			7 6 5 4  3  2  1  0	7 6 5 4  3  2  1  0

I	Restore		0 0 0 0  h  V r1 r0	0 0 0 0  h  V r1 r0
I	Seek		0 0 0 1  h  V rl r0	0 0 0 1  h  V r1 r0
I	Step		0 0 1 T  h  V rl r0	0 0 1 T  h  V r1 r0
I	Step-in		0 1 0 T  h  V rl r0	0 1 0 T  h  V r1 r0
I	Step-out	0 1 1 T  h  V r1 r0	0 1 1 T  h  V r1 r0

II	Read Sector	1 0 0 m  S  E  C  0	1 0 0 m  L  E  U  0
II	Write Sector	1 0 1 m  S  E  C a0	1 0 1 m  L  E  U a0

III	Read Address	1 1 0 0 0 E 0 0		1 1 0 0  0  E  U 0
III	Read Track	1 1 1 0 0 E 0 0		1 1 1 0  0  E  U 0
III	Write Track	1 1 1 1 0 E 0 0		1 1 1 1  0  E  U 0

IV	Force Interrupt	1 1 0 1 I3 I2 I1 I0	1 1 0 1 I3 I2 I1 I0

Note that the commands for two ICs are almost identical, thus to maintain compatibility between different versions of the SFDC IC the following restrictions must be observed:

In type II commands (read and write sector)

  1. Bit 3 (S and L in the above table) must be set to 1.

  2. Bit 1 (C and U in the above table) must be set to the side to be selected (0 or 1).