; Z8000 glue logic
; Based on 4sun5bu's TTL design
; with minor mod regarding MREQ signal.
; 
; Date: 2021-11-11 first draft
;
; Not enough output pins to support all logic,
; so the !AS to ALE inverter left out.
;
;
chip Z8001-GLUE GAL22V10

;	!AS	=	1 	; Address strobe

!DS	=	2	; Data strobe
ST0	=	3 	; 
ST1	=	4 	; 
ST2	=	5 	; 
ST3	=	6	; 
A4	=	7 	; 
A5	=	8	; 
R_not_W	=	9 	; 
B_not_W	=	10	; 
!MREQ	=	11	; Memory Request
;
GND	=	12 
VCC	=	24
;
; Right-hand side of GAL:
;
;	ALE		=	23	; to '573 transparent latches
;
!IDE		=	23	; to IDE/CF interface
!INTACK		=	22	; to SCC and CIO
!RD		=	21	; to RAM and I/O chips
!WR		=	20	; to RAM and I/O chips
COMMS_CS	=	19	; to SCC or USB module
CIO_CS		=	18	; to CIO
RAM_CS_ODD	=	17	; to RAM, odd bank
RAM_CS_EVEN	=	16	; to RAM, even bank
A19		=	15	; from address MSB
A18		=	14
A0		=	13	; from address LSB
;

equations

;
; Internal variables:
;
status_0	=	!ST3	&	!ST2	&	!ST1	&	!ST0;
status_1	=	!ST3	&	!ST2	&	!ST1	&	 ST0;
status_2	=	!ST3	&	!ST2	&	 ST1	&	!ST0;
status_3	=	!ST3	&	!ST2	&	 ST1	&	 ST0;
status_4	=	!ST3	&	 ST2	&	!ST1	&	!ST0;
status_5	=	!ST3	&	 ST2	&	!ST1	&	 ST0;
status_6	=	!ST3	&	 ST2	&	 ST1	&	!ST0;
status_7	=	!ST3	&	 ST2	&	 ST1	&	 ST0;
;
refresh	=	status_1		; not used
io	=	status_2		; was U7, pin 13
;
;	ST3-0	Definition
;	0000	Internal Operation
;	0001	Memory Refresh
;	0010	I/O Reference
;	0011	Special I/O Reference
;	0100	Segment Trap Acknowledge
;	0101	Nonmaskable Interrupt Acknowledge
;	0110	Nonvectored Interrupt Acknowledge
;	0111	Vectored Interrupt Acknowledge
;	1000	Data Memory Request
;	1001	Stack Memory Request
;	1010	Data Memory Request (EPU)
;	1011	Stack Memory Request (EPU)
;	1100	Instruction Space Access
;	1101	Instruction Fetch, First Word
;	1110	Transfer between EPU and CPU
;	1111	Test and Set Data Access (Z8003 and Z8004 only)
;
read	=	 R_not_W;
write	=	!R_not_W;
byte	=	 B_not_W;
word	=	!B_not_W;
;
; Both chips read at once, whether byte or word cycle.
;
even	=	read			; was U3C pin 6
	+	byte	&	!A0	; was U9A pin 3

odd	=	read			; was U3C pin 6
	+	byte	&	 A0	; was U9A pin 6
;
; Drive output pins:
;
; ALE		=	AS			; simple inverter
;
INTACK		=	status_7		; was U7, pin 7
;
RD		=	DS & read		; was U8A pin 3
WR		=	DS & write		; was U8A pin 6
;
COMMS_CS	=	io & !A5 & !A4		; was U14A, pin 4
CIO_CS		=	io & !A5 &  A4		; was U14A, pin 5
IDE_CS		=	io &  A5 & !A4		; was U14A, pin 6
;
RAM_CS_ODD	=	MREQ & !A19 & !A18 & odd	; was U11A, pin 4
RAM_CS_EVEN	=	MREQ & !A19 & !A18 & even	; was U11B, pin 12
;
; NB I have added MREQ to the RAM_CS equations above
; so that an inverter and output pin is not required
; to drive the active-high CS signal on the RAM chips.
; That pin can be tied high.
; This also allows the use of smaller RAM chips,
; which do not have an active-high CS pin.
;
;