PARTNO    hsync;
                NAME      hsync;
                DATE      1998-11-12;
                REV       01 ;
                DESIGNER  isb ;
device v750;
pin 1 = clk6in;  	       /* from crystal */
pin 2 = a0;      	       /* from CPU */
pin 3 = a1;      	       /* from CPU */
pin 4 = !rd;    	       /* from CPU */
pin 5 = !wr;    	       /* from CPU */
pin 6 = !iorq;   	       /* from CPU */
pin 7 = !m1;     	       /* from CPU */
pin 8 = roma14; 	       /* from SW1 */
pin 9 = roma15;  	       /* from SW2 */
pin 10 = invert; 	       /* from SW5 */
pin 11 = !hardwarehsyncenable; /* from SW7 */
pin 23 = clk6;           /* to crystal and SHIFT pld */
pin 22 = !clk3;          /* to CPU */
pin 21 = !vsync;         /* to DECODE pld */
pin 20 = !nmi;           /* to CPU and DECODE pld */
pin 19 = !csync;         /* to video out circuit */
pin 18 = !nmienable;     /* to DECODE pld */
pin 17 = hreset;         /* unconnected */
pin 16 = !blankedinvert; /* to SHIFT pld */
pin 15 = hsync;          /* to decode PLD */
pin 14 = tapesync;       /* to cassette ouput circuit */
pin 13 = !special;       /* to SW8 */
pinnode 34 = q1;
pinnode 33 = sync1;
pinnode 32 = q3;
pinnode 31 = q5;
pinnode 30 = q7;
pinnode 29 = q6;
pinnode 28 = q4;
pinnode 27 = q2;
pinnode 26 = sync2;
pinnode 25 = q0;
romzx80 =  roma14 & roma15;
romzx81 = !roma14 & roma15;
romlambdazx81 =  roma14 & !roma15;
romlambdastandard = !roma14 & !roma15;
zxhardware = roma15;
lambdahardware = !roma15;
zx80 = romzx80
     # romzx81 & special;
hardwarehsync = lambdahardware & !special
              # hardwarehsyncenable;
clk6=!clk6in;
clk3.ck=!clk6;
clk3.d=!clk3;
field vcount=[q7..q0];
[q0..7].ck = !clk3;
hreset = vcount:['d'207]
       # !hardwarehsync & !tapesync & !nmienable
       #  hardwarehsync & zxhardware & vsync;
q0.d= !hreset & !q0
    #  hreset & !lambdahardware;
q1.d= !hreset & (q1 $ q0);
q2.d= !hreset & (q2 $ (q0 & q1));
q3.d= !hreset & (q3 $ (q0 & q1 & q2));
q4.d= !hreset & (q4 $ (q0 & q1 & q2 & q3));
q5.d= !hreset & (q5 $ (q0 & q1 & q2 & q3 & q4));
q6.d= !hreset & (q6 $ (q0 & q1 & q2 & q3 & q4 & q5));
q7.d= !hreset & (q7 $ (q0 & q1 & q2 & q3 & q4 & q5 & q6));
nmienable.ar = romzx80;
nmienable.ck = iorq & wr;
nmienable.d = !zx80 & nmienable & a0 & a1
            # !zx80 & nmienable & !a0 & !a1
            # !zx80 & !a0 & a1;
vsync.ar = iorq & wr;
vsync.ck = iorq & rd;
vsync.d =  a0 & vsync
        # !a0 & !nmienable;
sync1.ar = !tapesync;
sync1.ck = iorq;
sync1.d = !nmienable;
sync2.ck = m1;
sync2.d = !sync1;
tapesync.ar = vsync;
tapesync.ck = m1;
tapesync.d = sync2;
counterhsync = vcount:['d'188..'d'207];
hsync.ck = !clk3;   /* latch hsync to eliminate glitches */
hsync.d = !nmienable & !tapesync
        #  nmienable & counterhsync;
nmi.ck = !clk3;     /* latch nmi to co-time with hsync */
nmi.d = nmienable & vcount:['d'186..'d'205];  /* nmi decreased by 2 */
                                              /* 1 for alignment and 1 to */
                                              /* account for latch delay */
blankedinvert.ck = !clk3;   /* latch blankedinvert to co-time with hsync */
blankedinvert.d = !(vcount:['d'184..'d'207]
                # vcount:['d'0..15]
                # !invert);
csync = !hardwarehsync & hsync
      #  hardwarehsync & (counterhsync # vsync);