default setup of address space this could change if software changes it $00 0000 - CSBOOT, 1MB, onboard boot ROM $10 0000 - CS0, 1MB, card 1 & 2, addon ROM card $40 0000 - CS1, 1MB, card 3 & 4, onboard DRAM $5C 0000 - CS8, 256KB, card 8, onboard SRAM $60 0000 - CS2, 1MB, card 5 & 6, SRAM card $B0 0000 - CS7, 1MB, 8 bit port, videochip $D0 0000 - CS5, 16KB, I/O $E0 0000 - CS9, 2KB, 8 bit port $F0 0000 - CS10, 64KB, 8 bit port, I/O $FF E000 - TPURAM, 2K $FF F000 - internal CPU on-chip registers CS5 controls U210, a 74AC138 for address decode CS9 goes to a pin on J3, and nowhere else as far as I can tell. CS10 goes to U25, a 74AC138 for address decode. also goes to pin on JA1 for daughterboard. hardware I/O addresses: CS5:0-7FF - UART1 This is the base address for the 68C681 on the mainboard. The base set of registers is repeated to fill the block of addresses. CS5:802 - LEDS - doesn't clear IRQ CS5:800 - PPORT - clears IRQ This write address controls the parallel port output pins and the 4 onboard LEDs. Bit 15, 14, 13, and 12 control CR 50, 51, 52, and 53 respectively. Bit 11 controls the /SELECT_PRINTER line. Bit 10 controls the RESET line. Bit 9 controls the /LF line. Bit 8 controls the /STROBE line. The lower 8 bits control the data outputs. This address is repeated in the range 800-FFF everytime ADDR2 is 0. If any address in this range is read or written which has ADDR1=0 then the /ACK interrupt is also cleared. TODO: figure out how to read the status lines for the parallel port, should be U57 CS5:1800-1FFF - J4 CS5:2000-27FF - RTC Base address for Epson RTC registers CS5:2000-2800 - EEPROM CS5:3800-3FFF - DRAMC_CNTL This address is used to write U719 (74AC573), an 8 bit latch. The actual chip seems to have the data lines hooked up backwards from the numbering in the datasheet, and it's attached to the high bits of the CPU data bus. The output of this latch is enabled or disabled by TPU channel 15. A 0 on the TPUCH15 pin on the 68332 enables output from this latch. Bit 6 and 7 appear to be unused. Bit 5 controls the DRAM controller /DISRFSH line. Bit 4 controls the DRAM controller /ML line. Bit 3 and 2 go to the PSU connector. Bit 1 and bit 0 seem to mask interrupt sources from the power supply board. A 1 masks the interrupts. The interrupts share a single interrupt latch flip flop and use IRQ1. They are cleared by a reset or reading this address. CS7:0-FFFFF - ISA bus/SVGA controller The SVGA controller is mapped here. 0-7FFFF seems to be mapped to I/O reads and writes (not confirmed) while 80000-FFFFF seem to be mapped to memory reads and writes. This is necessary because the video chip is made to work on an ISA bus which has separate memory and I/O spaces while the 68K does not. chip is setup for MCLK on MCLK pin ISA bus Symmetric DRAM single WE, multiple CAS 6 MCLK RAS cycle 44.74431MHz MCLK 32K ROM BIOS at C0000-C7FFF 8 bit BIOS ROM Internal MCLK 3C3h is video system sleep register CS7:02000-02007, 02406-02407 - ATA registers This is piggybacked into the pseudo ISA bus used for the VGA controller. Decoding is done using a 74ACT138 decoding the top 6 address lines (A15-A10). CS10:0-3FF - UART2 This is the base address for the 68C681 on the daughtercard. The base set of registers is repeated to fill the block of addresses. This also reappears at 2000-23FF CS10:400-7FF - KB controller odd addresses are status/command, even addresses are data. These registers may be repeated at 2400-27FF CS10:800-BFF - MTR_CNTRL This address writes to U18 (74AC573) on the daughtercard. It's bits control various motor functions on the daughtercard. Bit 7 seems to be disconnected by a jumper. If the bit 7 jumper were closed, bit 7 is ORed with J9 pin 3 and the resultant signal selectively inverts bit 4 of this same register. Bit 6 is connected to J8 pin 10. Bit 5 is the enable line for U6 and U7 (H-bridge motor controllers) which are driven by TPUCH6 and TPUCH7 respectively. Bit 4 controls the enable line of U15 and U16 (also H-bridge motor controllers). U15 and U16 seem to drive the same motor. The motor is stepped by TPUCH9 and the direction is controlled by TPUCH8. Bit 3, 2, 1 and 0 go to J3 pin 7, pin 19, pin 1, and pin 2 respectively. CS10:C00-FFF - U20 bit 6 and 7 are not stored. Bit 5 is stored, but not used. Bit 4, 3, 2, 1, and 0 are connected through a 200 ohm resistor to J10 (batch) pin 6, 5, 4, 2, and 3 respectively. These IO addresses may be repeated at 2C00-2FFF CS10:3800-3FFF This selects a small PROM on the addon ROM board. Not all of the PROM is even mapped into the address space (many address lines are tied to VCC or VSS). see schematic. IRQs: IRQ7 - goes to J3 and U27 pin 13. appears to be used for expansion, possibly the optional floppy drive interface. IRQ6 - JA1 pin 26, KBD controller output buffer full interrupt, pin 35, U26 pin 10 IRQ5 - UART1 interrupt request IRQ4 - JA1 pin 5, UART2 interrupt request IRQ3 - RTC periodic interrupt, U26 pin 13 IRQ2 - U26 pin 4, parallel port /ACK interrupt. Indicates printer is ready for more data. IRQ1 - JA1 pin 6, causes U14 on daughterboard to latch, U26 pin 2, used for 3 interrupt sources on the PSU board, two maskable, the third not. U29 is interrupt acknowledge decoder. For this to work, FC0, FC1, and ADDR19 must be enabled in place of CS3, 4, and 6. IRQA7 - AVEC IRQA6 - AVEC IRQA5 - UART1 IACK IRQA4 - JA1 pin 25, UART2 IACK IRQA3 - AVEC IRQA2 - AVEC IRQA1 - AVEC Periodic Interrupt Timer - IRQ5, vector $40 by original ROM QSCI - normally disabled by original ROM, pins not connected QSPI - IRQ6, vector $50 by original ROM TPU - IRQ1, vectors $60-$6F by original ROM TPU channels: 0 - used with ch 1 for stepper motor control. goes to U710 pin 2 1 - used with ch 0 for stepper motor control. goes to U710 pin 12 2 - used with ch 3 for stepper motor control. goes to U78 pin 2 and U76 pin 13 3 - used with ch 2 for stepper motor control. goes to U78 pin 10 and U76 pin 11 4 - used with ch 5 for stepper motor control. goes to U79 pin 2 and U76 pin 9 5 - used with ch 4 for stepper motor control. goes to U79 pin 10 and U76 pin 1 6 - used with ch 7 for stepper motor control. goes to JA1 pin 36 7 - used with ch 6 for stepper motor control. goes to JA1 pin 16 8 - used as direction control for stepper motor controlled by ch 9. goes to JA1 pin 35 9 - used to control the rate of movement of a stepper motor. goes to JA1 pin 15 10 - discrete I/O, seems to control beeper, 1 for on, 0 for off 11 - unknown. may be disconnected entirely. 12 - discrete I/O, goes to U67 pin 11 13 - unknown, may be disconnected entirely. 14 - U717 pin 3 15 - see section on DRAM. ISA bus: implemented for access to the SVGA chip. U44 GAL22V10 used for signal decoding. pin 2 - CPU clock pin 3 - NC pin 4 - NC pin 5 - /AS pin 6 - R/W pin 7 - U41 pin 3, OR of ADDR19 and CS7. must be IO select pin 9 - OR of (NOT ADDR19) and CS7. Must be memory select pin 10 - NC pin 11 - NC pin 12 - IOCHRDY pin 13 - NC pin 16 - NC pin 17 - NC pin 18 - NC pin 19 - BALE pin 20 - MEMW pin 21 - MEMR pin 23 - IOW pin 24 - IOR- pin 25 - NC pin 26 - DSACK0 through U45 pin 27 - NC to convert to 16 bit, DSACK0 must be cut. /IOCS16 must be OR'ed with /IO (pin 7 of GAL), /MCS16 must be OR'ed with /MEM (pin 9 of GAL), and the resulting two signals ANDed or NANDed. Of course, further logic simplification says that we could replace the two ORs and AND with all NORs and obtain an equivalent circuit using 3 NORs, thus potentially saving a chip. The resulting signal will then be latched on the falling edge of BALE. The Q output of the latch can then be NORed with SIZ0 to determine whether a 16 bit transfer occured. if the 16 bit transfer did occur, then DSACK output on the GAL is gated to generate DSACK1, otherwise it is gated to generate DSACK0. of course, this means the upper data bus of the 68332 needs to be connected to the lower data bus of the ISA peripheral(s) (this swap fixes endianess issues), /SBHE needs to be connected to SIZ0, and the 16 bit select lines must have pullup resistors connected. QSM: TX and RX (SCI stuff) appear to be disconnected. PQS6/PCS3 goes to U66, an OR gate which has the other pin going to an open jumper, JP70. PQS5/PCS2 is used for U64 ADC channel 1/2 select PQS4/PCS1 U67 pin 4 PQS3/PCS0/SS U66 pin 4 PQS2/SCK U68 pin 3 and sclk on U64 ADC PQS1/MOSI U64 ADC SDATA output PQS0/MISO appears to not be connected. J4 pinout pin closest to LEDs is pin 1. zigzag 1 - NC 2 - NC 3 - GND 4 - 5V 5 - RESET (active high) 6 - NC 7 - ADDR2 8 - RESET (active high) 9 - ADDR1 10 - NC 11 - ADDR0 12 - NC 13 - /WRS (write strobe) 14 - /WRS 15 - /RDS (read strobe) 16 - DATA14 17 - GND 18 - 5V 19 - DATA15 20 - NC 21 - DATA14 22 - CS5:1800-1FFF select (active low) 23 - DATA13 24 - ADDR18 25 - DATA12 26 - NC 27 - DATA11 28 - ADDR0 29 - DATA10 30 - ADDR0 31 - DATA9 32 - /WRS 33 - DATA8 34 - /WRS 35 - GND 36 - 5V