-- bram.vhdl : un bloc générique de mémoire à un port. -- version dim. août 16 00:13:05 CEST 2015 whygee@f-cpu.org library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bram is generic ( WIDTH : integer := 16; ADRBITS : integer := 10 ); port ( reset : in std_logic := '1'; a_clk, a_wr_en : in std_logic; a_addr : in std_logic_vector(ADRBITS-1 downto 0); a_din : in std_logic_vector(WIDTH-1 downto 0); a_dout : out std_logic_vector(WIDTH-1 downto 0) ); end bram; architecture rtl of bram is type mem_type is array ( (2**ADRBITS)-1 downto 0) of std_logic_vector(WIDTH-1 downto 0); shared variable mem: mem_type; begin process(a_clk, reset) variable ad : integer; begin if (reset='0') then a_dout <= (a_dout'range=>'0'); else if rising_edge(a_clk) then ad := to_integer(unsigned(a_addr)); a_dout <= mem(ad); if a_wr_en='0' then mem(ad) := a_din; report " WRITE " & integer'image(to_integer(unsigned(a_din))) & " @ " & integer'image(ad); end if; end if; end if; end process; end rtl;