SafeTI™ Diagnostic Library: Safety Manual for the SafeTI™ Hercules™ Diagnostic Library

SafeTI™ Diagnostic Library 2.2.0
SafeTI™ Diagnostic Library for the Hercules processors
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Safety Manual for the SafeTI™ Hercules™ Diagnostic Library

TI Hercules MCU Safety Overview

The Hercules MCU family of processors share a common safety architecture concept called a "Safe Island" philosophy. The basic concept involves a balance between application of hardware diagnostics and software diagnostics to manage functional safety, while balancing cost concerns. In the "safe island" approach, a core set of elements are allocated continuously operating hardware safety mechanisms. This core set of elements, including power & clock, reset, CPU , Flash memory, SRAM and associated interconnect, is needed to assure any functionally correct execution of software. Once correct operation of these elements is confirmed, software execution can begin on these elements in order to provide software-based diagnostics on other device elements, such as peripherals.

The Hercules architecture also provides various safety mechanisms and technical recommendations for the use of safety mechanisms. The Diagnostic Library provides interfaces to these safety mechanisms. Based on the final system requirements the system integrator can use these APIs to incorporate appropriate mechanisms in the final system to meet safety requirements.

The following figure illustrates the Safe Island approach overlaid to superset configuration of the Hercules product architecture (ARM Cortex R4 device variants)

The following figure illustrates the Safe Island approach overlaid to superset configuration of the Hercules product architecture (ARM Cortex R5 device variants)

SafeTI™ Hercules™ Diagnostic Library Overview

Following diagram shows the Software stack in the perspective of the Diagnostic Library. Hardware Abstraction Layer (HAL) is the lowest software layer. It contains software modules with direct access to MCU and is responsible for system initialisation. Diagnostic Library is a collection of functions for access to Safety Functions and response handlers for various safety mechanisms. Diagnostic Library runs in the context of the caller's protection environment and all responses are handled in the the context of interrupt or exception.

Initialization

Startup block is responsible for configuring the safety mechanisms and detecting any failures at system boot (via Safety Tests). This block has a few Initialization API and depends on APIs of other blocks to execute various functions at self test (Self-Test, PBIST, LBIST, Configuration via HAL). The application may follow an initialization sequence as described in the application note in Reference#9

Exception Handler

The R4/R5 CPU branches to an exception handler for handling failures at runtime. Following exceptions are handled:

  • Prefetch Aborts (Precise)
  • Data Abort (Precise & Imprecise)
  • Undefined instructions

These handlers are typically defined by the RTOS/HAL layers and are hence not provided by the library. However, a reference implementation is provided for handling of the errors resulting in CPU exceptions.

ESM Handler

ESM handler block is responsible to handling various errors at run time. The errors are processed for additional information and intimated to application via registered callbacks. Based on system�s safety requirements the application can use the provided information to take necessary steps.

Self Tests and Fault Injection API

Diagnostic Library API can be called in fault injection and selftest modes.

  • Fault Injections allows the application to induce faults and verify the fault handling in their application.
  • Selftest is mechanism for providing latent fault diagnostics. It verifies the safety mechanisms available on the device.

The figure below illustrates the Safety Diagnostic Library features on the Hercules MCU devices based on the ARM Cortex® R4 and ARM Cortex® R4F devices. The same concept applies to the ARM Cortex R5 variant diagnostic library.

Criteria for the usage of the SafeTI™ Hercules™ Diagnostic Library API

The API provided by the Diagnostic Library are recommended to be used in a system for periodic tests on the fault diagnostics. It is expected that this is done the diagnostic time interval (time interval set aside for selftest and where nothing else is running in the system.) These API configure the fault diagnostics in special modes to check the function of the diagnostic. The return value of the Selftest APIs indicate if the diagnostic is functioning as expected or if there is a fault in the device. Interrupting the operation of the Selftest API can leave the system in an undefined state.

Please refer to the Diagnostic Library data sheet for timing information related to the diagnostic APIs.

Fault injection API are used to create faults at run time such that the application developer may be able to simulate faults and their handling during development. Similar to Selftest API, Fault injection API configure fault diagnostics in special modes to create the desired fault. It should be possible to insert faults at any time. The above requirements imply that Diagnostic Library API are run as the highest priority task in the application.

Folder structure

Safety Library installer extracts into the folder structure shown below

Include files necessary for using SafeTI™ Hercules™ Diagnostic Library

The sl_api.h should be included(#include "sl_api.h") by the application to use the Diagnostic Library.

Generated on Fri Feb 6 2015 03:20:30 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: Configuration items

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Configuration items

Refer to configuration items for SafeTI™ Hercules™ Diagnostic library for a list of configurable settings

Generated on Fri Feb 6 2015 03:20:29 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: Build

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Build

Building the library

The SafeTI™ Hercules™ Diagnostic Library (referred to as Diagnostic Library hereinafter) package includes a Code Composer Studio Eclipse project (in the build_safeTILib folder) which can be built using the Code Composer Studio GUI or through the command line.

Multiple Diagnostic Library project configurations are defined, based on the Hercules MCU device variant and build configuration (debug/release). A particular configuration can be selected in the CCS project under <Right Click Project> -> Build Configurations. Depending on your Hercules MCU, you set a particular configuration active and work with it.

These configurations can be managed under <Right Click Project> -> Build Configurations -> Manage... as shown in the figure below.

Prebuilt release mode libraries for the Hercules MCU devices are available in the libs folder.

You can choose specific behavior of the library by enabling/disabling certain macros and their values in the sl_config.h header file. This provides options for enabling/ disabling - function parameter check; function entry condition check; logging of function results and function profiling. Please see the Configuration items for additional details.

Demo application

Device specific sample applications are bundled with the Diagnostic Library to demonstrate the use of the Diagnostic Library APIs.

This is an example application which does not use any RTOS. This project relies on HALCoGen to provide the system initialization and application framework. The project can be imported using the File -> Import -> Existing CCS Eclipse Project and pointing it to the particular build folder in <Installation Directory>\ <device>_NoOS folder (depending on the device variant). This may then be built and run on the specified target board.

Separate HALCoGen projects have been created under the <Installation Directory>demo_app<device> folder. These projects can be accessed in HALCoGen under File -> Open -> Project and pointing it to the HALCoGen project file (*.hcg) of the corresponding device, available in that particular folder. This opens the HALCoGen project and user can now modify its configuration and update the HALCoGen files (for instance update them to newer versions using a newer version of HALCoGen).

Diagnostic Library Functionality in Demo application

The sys_startup.c file from HALCoGen has been modified to make calls to the Diagnostic Library APIs which do the boot time tests.(the function _c_int00)

The application main() function contains the Diagnostic Library API calls for demonstrating the run-time diagnostics.

  • Running counters - periodicSTPassCount, periodicSTFailCount - are incremented to keep track of passing and failing test counts.
  • After 10 iterations the execution can be paused and the variables periodicSTPassCount, periodicSTFailCount can be checked to see the number of tests passing and the number of tests which are failing.
  • When integrating with an OS, these tests can be run in a separate task which may be invoked periodically.

Note that prior to running the parity/ECC tests on various peripherals, ECC must be enabled and the corresponding memories have to be initialized with the correct parity/ECC values prior to the test.

In the demo application Reg_Read_Compare() API is called at startup to baseline the values of current configuration registers of various device modules. It is again invoked at run time to do a readback and compare (check it the values are intact). Care has to be taken during periodic checking - if you make any configuration change (for any tests or otherwise) in the application code (main) then you might have to rebaseline first and then do the readback and compare.

Generated on Fri Feb 6 2015 03:20:29 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: References

References
  1. Datasheets, TRM, Safety manuals for Hercules devices - http://www.ti.com/Hercules
  2. HALCoGen - http://www.ti.com/tool/halcogen
  3. UniFlash - http://www.ti.com/tool/uniflash
  4. Initialization of Hercules™ ARM Cortex-R4F Microcontrollers - http://www.ti.com/lit/an/spna106c/spna106c.pdf
Generated on Fri Feb 6 2015 03:20:29 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: Safety manual to API mapping

Safety manual to API mapping
Device Partition | Unique Identifier | Safety Feature or Diagnostic | API Name | Remarks | Possible Latent Diagnostics
Power Supply | PWR1 | Voltage monitor (VMON) | Not Applicable | No software control,always enabled in hardware | External Voltage Supervisor
 | PWR2 | External voltage supervisor | Not Applicable | Handled by the safety application | Voltage monitor (VMON)
Power Management Module (PMM) | PMM1 | Lockstep PSCON | SL_SelfTest_PSCON |  | PSCON lockstep self test
 | PMM2 | Privileged mode access and multi-bit keys for control registers | SL_SelfTest_PSCON |  | Software test of register configuration and error response
 | PMM3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
 | PMM4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
Clock | CLK1 | LPOCLKDET | Not Applicable | Handled by the safety application | DCC, ECLK, watchdog
 | CLK2 | PLL slip detector | ESM_Application_Callback |  | DCC, ECLK, watchdog
 | CLK3 | Dual Clock Comparator (DCC) | ESM_Application_Callback |  | DCC Autocoverage, ECLK, watchdog
 | CLK4 | External monitoring via ECLK | Not Applicable | Handled by the safety application | LPOCLKDET, PLL slip detector, DCC, watchdog
 | CLK5A | Internal watchdog - DWD | Not Applicable | Handled by the safety application | External watchdog, software test of watchdog configuration and error response
 | CLK5B | Internal watchdog - DWWD | Not Applicable | Handled by the safety application | External watchdog, software test of watchdog configuration and error response
 | CLK5C | External watchdog | Not Applicable | Handled by the safety application | Internal watchdog, software test of watchdog configuration and error response
 | CLK6 | Periodic software readback of static clock configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
 | CLK7 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
Reset | RST1 | External monitoring of warm reset | Not Applicable | Handled by the safety application | Watchdog
 | RST2 | Software check of last reset | SL_Init_ResetReason |  | CPU lockstep
 | RST3 | Software warm reset generation | SL_SW_Reset |  | CPU lockstep
 | RST4 | Glitch filtering on reset pins | Not Applicable | No software control,always enabled in hardware | Watchdog
 | RST5 | Use of status shadow registers | SL_Init_ResetReason_XInfo |  | CPU lockstep
 | RST6 | External watchdog | Not Applicable | Handled by the safety application | Software test of external watchdog configuration and error response
 | RST7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
 | RST8 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
System Control | SYS1 | Privileged mode access and multi-bit enable keys | Not Available | Not in scope for this release | Software test of register configuration and error response
 | SYS2 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
 | SYS3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Error Signaling Module (ESM) | ESM1 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
 | ESM2A | Boot time software test of error path reporting | Fault Injection APIs may be used |  | CPU lockstep
 | ESM2B | Periodic software test of error path reporting | Fault Injection APIs may be used |  | CPU lockstep
 | ESM3 | Use of status shadow registers | SL_Init_ResetReason_XInfo |  | CPU lockstep
 | ESM4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
Cortex-R4FCentral Processing Unit (CPU) | CPU1 | Lockstep compare | SL_SelfTest_CCMR4F |  | CCM (lockstep) self test, LBIST
 | CPU2A | Boot time execution of LBIST STC | SL_SelfTest_STC |  | LBIST autocoverage
 | CPU2B | Periodic execution of LBIST STC | SL_SelfTest_STC |  | LBIST autocoverage
 | CPU3 | MPU | Not Applicable | Handled by operation system/safety application | CPU lockstep, LBIST
 | CPU4 | Online profiling using PMU | Not Applicable | Handled by the safety application | CPU lockstep, LBIST
 | CPU5A | Internal watchdog - DWD | Not Applicable | Handled by application | External watchdog, software test of watchdog configuration and error response
 | CPU5B | Internal watchdog - DWWD | Not Applicable | Handled by the safety application | External watchdog, software test of watchdog configuration and error response
 | CPU5C | External watchdog | Not Applicable | Handled by the safety application | Internal watchdog, software test of watchdog configuration and error response
 | CPU6 | Illegal operation and instruction trapping | Not Available | Not in scope for this release | CPU lockstep, LBIST
 | CPU7 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
Primary Flash and Level 1 (L1) Interconnect | FLA1 | Flash Data ECC | SL_SelfTest_Flash |  | CPU lockstep, LBIST, ECC autocoverage
 | FLA2 | Hard error cache and livelock | Not Available | Not in scope for this release | CPU lockstep, LBIST
 | FLA3 | Flash wrapper address ECC | SL_SelfTest_Flash |  | Software test of Flash wrapper ECC logic, ECC autocoverage
 | FLA4 | Address parity | SL_SelfTest_Flash |  | CPU lockstep, LBIST
 | FLA5A | Boot time hardware CRC check of Flash memory contents | SL_CRC_Calculate |  | CRC autocoverage
 | FLA5B | Periodic hardware CRC check of Flash memory contents | SL_CRC_Calculate |  | CRC autocoverage
 | FLA6 | Bit multiplexing in Flash array | Not Applicable | CRC will indicate faults in flash | ECC, CRC test
 | FLA7 | Flash sector protection | Not Applicable | External dependency on flash writing APIs | CRC test
 | FLA8 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
 | FLA9 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
Flash Emulated EEPROM (FEE) | FEE1 | FEE Data ECC | SL_SelfTest_FEE |  | Software test of data ECC in EEPROM emulation Flash wrapper, ECC autocoverage
 | FEE2A | Boot time hardware CRC check of FEE memory contents | SL_CRC_Calculate |  | CRC autocoverage
 | FEE2B | Periodic hardware CRC check of FEE memory contents | SL_CRC_Calculate |  | CRC autocoverage
 | FEE3 | Bit multiplexing in FEE array | Not Applicable | CRC will indicate faults in flash | ECC, CRC test
 | FEE4 | FEE sector protection | Not Applicable | External dependency on flash writing APIs | CRC test
 | FEE5 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
 | FEE6 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
SRAM and Level 1 (L1) Interconnect | RAM1 | Data ECC | SL_SelfTest_SRAM |  | CPU lockstep, LBIST, ECC autocoverage, PBIST
 | RAM2 | Hard error cache and livelock | Not Available | Not in scope for this release | CPU lockstep, LBIST
 | RAM3 | Correctable ECC profiling | Not Available | Not in scope for this release | CPU lockstep, LBIST
 | RAM4 | Address and control parity | SL_SelfTest_SRAM |  | CPU lockstep, LBIST, PBIST
 | RAM5 | Redundant address decode | SL_SelfTest_SRAM |  | ECC, PBIST
 | RAM6 | Data and ECC storage in multiple physical banks | Not Applicable | Feature in Hardware | ECC, autocoverage, PBIST
 | RAM7A | Boot time PBIST check of SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | RAM7B | Periodic PBIST check of SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | RAM8 | Bit multiplexing in SRAM array | Not Applicable | CRC will indicate faults in SRAM | ECC
 | RAM9 | Periodic hardware CRC check of SRAM contents | SL_CRC_Calculate |  | CRC autocoverage
 | RAM10 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CRC autocoverage
 | RAM11 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
Level 2 and Level 3 (L2 and L3) Interconnect | INC1 | Error trapping (including peripheral slave error trapping) | SL_SelfTestL2L3Interconnect |  | Software test of basic functionality and error response
 | INC2 | PCR access management | Not Available | Not in scope for this release | Software test of basic functionality and error response
 | INC3A | Internal watchdog - DWD | Not Applicable | Handled by the safety application | External watchdog, software test of watchdog configuration and error response
 | INC3B | Internal watchdog - DWWD | Not Applicable | Handled by the safety application | External watchdog, software test of watchdog configuration and error response
 | INC3C | External watchdog | Not Applicable | Handled by the safety application | Internal watchdog, software test of watchdog configuration and error response
 | INC4 | Information redundancy | Not Applicable |  | CPU lockstep
 | INC5 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
 | INC6A | Boot time software test of basic functionality including error tests | SL_SelfTestL2L3Interconnect |  | CPU lockstep
 | INC6B | Periodic software test of basic functionality including error tests | SL_SelfTestL2L3Interconnect |  | CPU lockstep
 | INC7 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
EFuse Static Configuration | EFU1 | Boot time autoload self-test | SL_SelfTest_EFuse |  | Self-test autocoverage
 | EFU2 | E-fuse ECC | Not Available | Not in scope for this release | Autoload self-test
One Time Programmable (OTP) Flash Static Configuration | OTP1 | Boot time autoload self-test | Not Available | Not in scope for this release | Self-test autocoverage
 | OTP2 | OTP ECC | Not Available | Not in scope for this release | Autoload self-test
Input/Output (I/O) Multiplexing (IOMM) | IOM1 | Locking control registers | Not Applicable | Hardware feature with no error response for faults | Software test of basic functionality and error response
 | IOM2 | Master ID filtering | Not Applicable |  | Software test of basic functionality and error response
 | IOM3 | Error trapping | Not Available | Not in scope for this release | Software test of basic functionality and error response
 | IOM4 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
 | IOM5A | Boot time software test of function using peripherals with analog I/O loopback including error tests | Not Available | Not in scope for this release | CPU lockstep
 | IOM5B | Periodic software test of function using peripherals with analog I/O loopback including error tests | Not Available | Not in scope for this release | CPU lockstep
 | IOM6 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
Vectored Interrupt Module (VIM) | VIM1 | VIM SRAM Data Parity | Not Available | Not in scope for this release | PBIST
 | VIM2A | Boot time PBIST check of VIM SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | VIM2B | Periodic PBIST check of VIM SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | VIM3 | Bit multiplexing in VIM SRAM array | Not Applicable | CRC will indicate faults in VIM SRAM | PBIST, parity
 | VIM4 | Periodic hardware CRC check of VIM SRAM contents | SL_CRC_Calculate |  | PBIST
 | VIM5 | Periodic software test of VIM functionality | Not Available | Not in scope for this release | CPU lockstep
 | VIM6 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
 | VIM7 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application. | CPU lockstep
 | VIM8A | Internal watchdog - DWD | Not Applicable | Handled by the safety application | External watchdog, software test of watchdog configuration and error response
 | VIM8B | Internal watchdog - DWWD | Not Applicable | Handled by the safety application | External watchdog, software test of watchdog configuration and error response
VIM8C | External watchdog | Not Applicable | Handled by the safety application | Internal watchdog, software test of watchdog configuration and error response
Real Time Interrupt (RTI) Operating System Timer | RTI1 | 1oo2 software voting using secondary free running counter | Not Available | Not in scope for this release | CPU lockstep, PMU cycle counter
 | RTI2A | Internal watchdog - DWD | Not Available | Not in scope for this release | External watchdog, software test of watchdog configuration and error response
 | RTI2B | Internal watchdog - DWWD | Not Available | Not in scope for this release | External watchdog, software test of watchdog configuration and error response
 | RTI2C | External watchdog | Not Available | Not in scope for this release | Internal watchdog, software test of watchdog configuration and error response
 | RTI3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Direct Memory Access (DMA) | DMA1 | Memory protection unit for bus master accesses | Not Available | Not in scope for this release | Software test of DMA MPU configuration and error response
 | DMA2 | Non-privileged bus master access | Not Available | Not in scope for this release | Software test of bus master function and error response
 | DMA3 | Information redundancy | Not Available | Not in scope for this release | CPU lockstep
 | DMA4 | DMA SRAM Data Parity | Not Available | Not in scope for this release | PBIST
 | DMA5A | Boot time PBIST check of DMA SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | DMA5B | Periodic PBIST check of DMA SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | DMA6 | Bit multiplexing in DMA SRAM array | Not Applicable | Feature in Hardware | PBIST, parity
 | DMA7 | Periodic hardware CRC check of DMA SRAM contents | SL_CRC_Calculate |  | PBIST
 | DMA8 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
 | DMA9A | Boot time software test of basic functionality including error tests | Not Available | Not in scope for this release | CPU lockstep
 | DMA9B | Periodic software test of basic functionality including error tests | Not Available | Not in scope for this release | CPU lockstep
High-End Timer (N2HET) Including HET Transfer Unit (HTU) | HET1 | Memory protection unit for bus master accesses | Not Available | Not in scope for this release | Software test of HTU MPU configuration and error response
 | HET2 | Information redundancy | Not Available | Not in scope for this release | CPU lockstep
 | HET3 | Use of DCC as program sequence watchdog | Not Available | Not in scope for this release | DCC autocoverage
 | HET4 | Monitoring by second N2HET | Not Available | Not in scope for this release | CPU lockstep
 | HET5A | Boot time software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | HET5B | Periodic software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | HET6 | N2HET/HTU SRAM Data Parity | Not Available | Not in scope for this release | PBIST
 | HET7A | Boot time PBIST check of N2HET/HTU SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | HET7B | Periodic PBIST check of N2HET/HTU SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | HET8 | Bit multiplexing in N2HET/HTU SRAM array | Not Applicable | Feature in Hardware | PBIST, parity
 | HET9 | Periodic hardware CRC check of N2HET/HTU SRAM contents | SL_CRC_Calculate |  | PBIST
 | HET10 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Multi-Buffered Analog to Digital Converter (MibADC) | ADC1 | Boot time input self test | SL_SelfTest_ADC |  | CPU lockstep
 | ADC2A | Boot time converter calibration | SL_adcCalibration |  | CPU lockstep
 | ADC2B | Periodic converter calibration | SL_adcCalibration |  | CPU lockstep
 | ADC3 | Information redundancy techniques | Not Available | Not in scope for this release | CPU lockstep, ADC converter calibration, ADC self-test
 | ADC4 | MibADC SRAM Data Parity | SL_SelfTest_ADC |  | PBIST
 | ADC5A | Boot time PBIST check of MibADC SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | ADC5B | Periodic PBIST check of MibADC SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | ADC6 | Bit multiplexing in MibADC SRAM array | Not Applicable | Feature in Hardware | PBIST, parity
 | ADC7 | Periodic hardware CRC check of MibADC SRAM contents | SL_CRC_Calculate |  | PBIST
 | ADC8 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Multi-Buffered Serial Peripheral Interface (MibSPI) | MSP1A | Boot time software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | MSP1B | Periodic software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | MSP2 | Parity in message | Not Available | Not in scope for this release | CPU lockstep
 | MSP3 | Information redundancy techniques | Not Available | Not in scope for this release | CPU lockstep
 | MSP4 | MibSPI SRAM Data Parity | Not Available | Not in scope for this release | PBIST
 | MSP5A | Boot time PBIST check of MibSPI SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | MSP5B | Periodic PBIST check of MibSPI SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | MSP6 | Bit multiplexing in MibSPI SRAM array | Not Applicable | Feature in Hardware | PBIST, parity
 | MSP7 | Periodic hardware CRC check of MibSPI SRAM contents | SL_CRC_Calculate |  | PBIST
 | MSP8 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Serial Peripheral Interface (SPI) | SPI1A | Boot time software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | SPI1B | Periodic software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | SPI2 | Parity in message | Not Available | Not in scope for this release | CPU lockstep
 | SPI3 | Information redundancy techniques | Not Available | Not in scope for this release | CPU lockstep
 | SPI4 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Inter-Integrated Circuit (I2C) | IIC1A | Boot time software test of function | Not Available | Not in scope for this release | CPU lockstep
 | IIC1B | Periodic software test of function | Not Available | Not in scope for this release | CPU lockstep
 | IIC2 | Information redundancy techniques | Not Available | Not in scope for this release | CPU lockstep
 | IIC3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Serial Communications Interface (SCI) | SCI1A | Boot time software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | SCI1B | Periodic software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | SCI2 | Information redundancy techniques | Not Available | Not in scope for this release | CPU lockstep
 | SCI3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Local Interconnect Network (LIN) | LIN1A | Boot time software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | LIN1B | Periodic software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | LIN2 | Information redundancy techniques including end to end safing | Not Available | Not in scope for this release | CPU lockstep
 | LIN3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Controller Area Network (DCAN) | CAN1A | Boot time software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | CAN1B | Periodic software test of function using I/O loopback | Not Available | Not in scope for this release | CPU lockstep
 | CAN2 | Information redundancy techniques including end to end safing | Not Available | Not in scope for this release | CPU lockstep
 | CAN3 | DCAN SRAM Data Parity | Not Available | Not in scope for this release | PBIST
 | CAN4A | Boot time PBIST check of DCAN SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | CAN4B | Periodic PBIST check of DCAN SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | CAN5 | Bit multiplexing in DCAN SRAM array | Not Applicable | Feature in Hardware | PBIST, parity
 | CAN6 | Periodic hardware CRC check of DCAN SRAM contents | SL_CRC_Calculate |  | PBIST
 | CAN7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
FlexRay Including FlexRay Transfer Unit (FTU) | FRY1 | Memory protection unit for bus master accesses | Not Available | Not in scope for this release | Software test of DMA MPU configuration and error response
 | FRY2 | Non-privileged bus master access | Not Available | Not in scope for this release | Software test of bus master function and error response
 | FRY3A | Boot time software test of function using I/O loopback in PHY | Not Available | Not in scope for this release | CPU lockstep
 | FRY3B | Periodic software test of function using I/O loopback in transceiver | Not Available | Not in scope for this release | CPU lockstep
 | FRY4 | Information redundancy techniques including end to end safing | Not Available | Not in scope for this release | CPU lockstep
 | FRY5 | 1oo2 Voting using Both FlexRay Channels | Not Available | Not in scope for this release | CPU lockstep
 | FRY6 | FlexRay and FTU SRAM Data Parity | Not Available | Not in scope for this release | PBIST
 | FRY7A | Boot time PBIST check of FlexRay and FTU SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | FRY7B | Periodic PBIST check of FlexRay and FTU SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | FRY8 | Bit multiplexing in FlexRay and FTU SRAM array | Not Applicable | Feature in hardware | PBIST, parity
 | FRY9 | Periodic hardware CRC check of FlexRay and FTU SRAM contents | SL_CRC_Calculate |  | PBIST
 | FRY10 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
General Purpose Input/Output (GIO) | GIO1A | Boot time software test of function using I/O checking | Not Available | Not in scope for this release | CPU lockstep
 | GIO1B | Periodic software test of function using I/O checking | Not Available | Not in scope for this release | CPU lockstep
 | GIO2 | Information redundancy techniques | Not Available | Not in scope for this release | CPU lockstep
 | GIO3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Ethernet | ETH1 | Non-privileged bus master access | Not Available | Not in scope for this release | Software test of bus master function and error response
 | ETH2A | Boot time software test of function using I/O loopback in PHY | Not Available | Not in scope for this release | CPU lockstep
 | ETH2B | Periodic software test of function using I/O loopback in PHY | Not Available | Not in scope for this release | CPU lockstep
 | ETH3 | Information redundancy techniques including end to end safing | Not Available | Not in scope for this release | CPU lockstep
 | ETH4A | Boot time PBIST check of Ethernet SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | ETH4B | Periodic PBIST check of Ethernet SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | ETH5 | Bit multiplexing in Ethernet SRAM array | Not Applicable | Feature in hardware | PBIST, parity
 | ETH6 | Periodic hardware CRC check of Ethernet SRAM contents | SL_CRC_Calculate |  | PBIST
 | ETH7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Universal Serial Bus (USB) | USB1 | Non-privileged bus master access | Not Available | Not in scope for this release | Software test of bus master function and error response
 | USB2A | Boot time software test of function using I/O loopback in PHY | Not Available | Not in scope for this release | CPU lockstep
 | USB2B | Periodic software test of function using I/O loopback in PHY | Not Available | Not in scope for this release | CPU lockstep
 | USB3 | Information redundancy techniques | Not Available | Not in scope for this release | CPU lockstep
 | USB4A | Boot time PBIST check of USB SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | USB4B | Periodic PBIST check of USB SRAM | SL_SelfTest_PBIST |  | PBIST autocoverage
 | USB5 | Bit multiplexing in USB SRAM array | Not Available | Not in scope for this release | PBIST, parity
 | USB6 | Periodic hardware CRC check of USB SRAM contents | SL_CRC_Calculate |  | PBIST
 | USB7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
External Memory Interface (EMIF) | EMF1 | Information redundancy techniques | Not Available | Not in scope for this release | CPU lockstep
 | EMF2A | Boot time hardware CRC check of external memory | SL_CRC_Calculate |  | CRC autocoverage
 | EMF2B | Periodic hardware CRC check of external memory | SL_CRC_Calculate |  | CRC autocoverage
 | EMF3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application. | CPU lockstep
Joint Technical Action Group (JTAG) Debug/Trace/ Calibration Access | JTG1 | Hardware disable of JTAG port | Not Applicable | Hardware Configuration | Watchdog detection of inadvertent activation that impacts program flow
 | JTG2 | Lockout of JTAG access using AJSM | Not Applicable | Configured by Application | Watchdog detection of inadvertent activation that impacts program flow
Cortex-R4F Central Processing Unit (CPU) Debug and Trace | DBG1 | Hardware disable of JTAG port | Not Available | Hardware Configuration | Watchdog detection of inadvertent activation that impacts program flow
 | DBG2 | Lockout of JTAG access using AJSM | Not Available | Configured by application | Watchdog detection of inadvertent activation that impacts program flow
 | DBG3 | Use MPUs to block access to memory-mapped debug | Not Available | Configured by application | Watchdog detection of inadvertent activation that impacts program flow
 | DBG4 | Use of CoreSight debug logic key enable scheme | Not Available | Not in scope for this release | Watchdog detection of inadvertent activation that impacts program flow
Data Modification Module (DMM) | DMM1 | Hardware disable of JTAG port | Not Applicable | Hardware Configuration | Detection of inadvertent activation that impacts program flow
 | DMM2 | Lockout of JTAG access using AJSM | Not Applicable | Configured by Application | Watchdog detection of inadvertent activation that impacts program flow
 | DMM3 | Use MPUs to block access to memory-mapped debug | Not Applicable | Configured by Application | Watchdog detection of inadvertent activation that impacts program flow
 | DMM4 | Disable DMM pin interface | Not Applicable | Hardware Configuration | Watchdog detection of inadvertent activation that impacts program flow
RAM Trace Port (RTP) | RTP1 | Hardware disable of JTAG port | Not Applicable | Hardware Configuration | Watchdog detection of inadvertent activation that impacts program flow
 | RTP2 | Lockout of JTAG access using AJSM | Not Applicable | Configured by Application | Watchdog detection of inadvertent activation that impacts program flow
 | RTP3 | Use MPUs to block access to memory-mapped debug | Not Applicable | Configured by Application | Watchdog detection of inadvertent activation that impacts program flow
 | RTP4 | Disable RTP pin interface | Not Applicable | Hardware Configuration | Watchdog detection of inadvertent activation that impacts program flow
Parameter Overlay Module (POM) | POM1 | Hardware disable of JTAG port | Not Applicable | Hardware Configuration | Watchdog detection of inadvertent activation that impacts program flow
 | POM2 | Lockout of JTAG access using AJSM | Not Applicable | Configured by Application | Watchdog detection of inadvertent activation that impacts program flow
 | POM3 | Use MPUs to block access to memory-mapped debug | Not Applicable | Configured by Application | Watchdog detection of inadvertent activation that impacts program flow
 | POM4 | Use of CoreSight debug logic key enable scheme | Not Applicable | Configured by Application | Watchdog detection of inadvertent activation that impacts program flow

Support functions

API | Brief Description
SL_Init_R4Registers | Intializes the Cortex R4 core registers
SL_Init_StackPointers | Intializes stack pointers for all the modes
SL_Init_Memory | Initializes memory for Processor
SL_Init_ECCFlash | Initializes ECC for flash
SL_Init_ECCTCMRAM | Intializes ECC for RAM
SL_SelfTest_Status_PBIST | Provides information on PBIST check done
SL_SelfTest_WaitCompletion_PBIST | Checks whether the PBIS is active or not
SL_SelfTest_PBIST_StopExec | Stops PBIST execution
SL_SelfTest_Status_PSCON | Provides status of PSCON test done
SL_SelfTest_Status_STC | Provides status of the STC selftest done
SL_SelfTest_Status_EFuse | Provides status of the EFUSE selftest done
SL_ESM_Init | Initializes ESM

Debug support functions

API | Brief Description
SL_Init_Profiling | This function initializes the pmu module for counting execution ticks
SL_Start_Profiling | This function starts profiling of an API for particular testtype
SL_Stop_Profiling | This function stops profiling of an API for particular testtype
SL_Record_Errorcreationtick | This API is used for recording the timestamp at which the error has been created
SL_Start_Profiling_PBIST | This function starts profiling of an PBIST API for valid ramgrop and algoinfo
SL_Stop_Profiling_PBIST | This function stops profiling of an PBIST API for valid ramgrop and algoinfo
SL_Log_Result | Funcion logs the result of the execution
SL_Log_Error | This function logs the errors that were captured by the SafeTI™ Hercules™ Diagnostic library API in the log buffer


SafeTI™ Diagnostic Library: Safety manual to API mapping: TMS570LC43x/RM57Lx devices

Safety manual to API mapping: TMS570LC43x/RM57Lx devices
Device Partition | Unique Identifier | Safety Feature or Diagnostic | API Mapping | Comments
Power Supply | PWR1 | Voltage monitor (VMON) | Not Applicable | Feature in hardware
 | PWR2 | External voltage supervisor | Not Applicable | Handled by the safety application
Power Management Module (PMM) | PMM1 | Lockstep PSCON | Not Applicable | Feature in hardware
 | PMM2 | Privileged mode access and multi-bit keys for control registers | Not Applicable | Feature in hardware
 | PMM3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | PMM4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
 | PMM5 | PSCON lockstep comparator self-test | Not yet available | To be made available in a subsequent release
 | PMM6 | Power domain off safe mode compare | SL_SelfTest_CCMR5F |
Clock | CLK1 | LPOCLKDET | Not Applicable | Handled by the safety application
 | CLK2 | PLL slip detector | Not Applicable | Handled by the safety application
 | CLK3 | Dual Clock Comparator (DCC) | Not Applicable | Handled by the safety application
 | CLK4 | External monitoring via ECLK | Not Applicable | Handled by the safety application
 | CLK5A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | CLK5B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | CLK5C | External watchdog | Not Applicable | Handled by safety application
 | CLK6 | Periodic software readback of static clock configuration registers | Not Applicable | Static configuration is defined by the application
 | CLK7 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
Reset | RST1 | External monitoring of warm reset | Not Applicable | Handled by the safety application
 | RST2 | Software check of last reset | SL_Init_ResetReason |
 | RST3 | Software warm reset generation | SL_SW_Reset |
 | RST4 | Glitch filtering on reset pins | Not Applicable | Feature in hardware
 | RST5 | Use of status shadow registers | SL_Init_ResetReason_XInfo |
 | RST6 | Handled by the safety application | Not Applicable | Handled by the safety application
 | RST7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | RST8 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
System Control | SYS1 | Privileged mode access and multi-bit enable keys | Not Applicable
 | SYS2 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
 | SYS3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | SYS4 | Multi-bit key based control register error correction for Critical static control register | Not Applicable | Feature in hardware
Error Signaling Module (ESM) | ESM1 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | ESM2A | Boot time software test of error path reporting | Fault injection APIs may be used |
 | ESM2B | Periodic software test of error path reporting | Fault injection APIs may be used |
 | ESM3 | Use of status shadow registers | SL_Init_ResetReason_XInfo |
 | ESM4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
Cortex-R5F Central Processing Unit (CPU) | CPU1 | Lockstep compare | Not Applicable | Feature in hardware
 | CPU2A | Boot time execution of LBIST STC | SL_SelfTest_STC |
 | CPU2B | Periodic execution of LBIST STC | SL_SelfTest_STC |
 | CPU3 | MPU | Not Applicable | Handled by operation system/safety application
 | CPU4 | Online profiling using PMU | Not Applicable | Handled by the safety application
 | CPU5A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | CPU5B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | CPU5C | External watchdog | Not Applicable | Handled by the safety application
 | CPU6 | Illegal operation and instruction trapping | Not available | Not in scope for this release
 | CPU7 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
 | CPU8 | Lockstep comparator (CCM) self-test | SL_SelfTest_CCMR5F |
 | CPU9 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | CPU10 | Information redundancy techniques (multiple execution) | Not Applicable | Information redundancy techniques are defined by application
 | CPU11 | Boot time PBIST check of CPU cache memories | SL_SelfTest_PBIST
 | CPU12 | Periodic PBIST check of CPU cache memories | SL_SelfTest_PBIST
 | CPU13 | ECC on cache memories | Not available | Not in scope for this release
 | CPU14 | Selection of cache scheme |  | Cache scheme selection is owned by the application
Primary Flash | FLA1 | Flash Data ECC | SL_SelfTest_Flash |
 | FLA2 | Hard error cache and livelock | Not available | Not in scope for this release
 | FLA3 | Flash wrapper address ECC | Not Applicable | Feature in hardware
 | FLA4 | Transaction address and control parity | Not Applicable | Feature in hardware
 | FLA5A | Boot time hardware CRC check of Flash memory contents | SL_CRC_Calculate |
 | FLA5B | Periodic hardware CRC check of Flash memory contents | SL_CRC_Calculate |
 | FLA6 | Bit multiplexing in Flash array | Not Applicable | Feature in hardware
 | FLA7 | Flash sector protection | Not Applicable | Feature in hardware
 | FLA8 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | FLA9 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
Flash Emulated EEPROM(FEE) | FEE1 | FEE Data ECC | SL_SelfTest_Flash
 | FEE2 | Hard error cache and livelock | Not available | Not in scope for this release
 | FEE3 | FEE wrapper address ECC | Not Applicable | Feature in hardware
 | FEE4 | Transaction address and control parity | Not Applicable | Feature in hardware
 | FEE5A | Boot time hardware CRC check of FEE memory contents | SL_CRC_Calculate
 | FEE5B | Periodic hardware CRC check of FEE memory contents | SL_CRC_Calculate
 | FEE6 | Bit multiplexing in FEE array | Not Applicable | Feature in hardware
 | FEE7 | FEE sector protection | Not Applicable | Feature in hardware
 | FEE8 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | FEE9 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
SRAM | RAM1 | Data ECC | SL_SelfTest_SRAM
 | RAM2 | Hard error cache and livelock | Not available | Not in scope for this release
 | RAM3 | Correctable ECC profiling | Not Applicable | ECC profiling feature is provided through usage of EPC module
 | RAM4 | Address and control parity | Not Applicable | Feature in hardware
 | RAM5 | Redundant address decode | Not available | Not in scope for this release
 | RAM6 | Data and ECC storage in multiple physical banks | Not Applicable | Feature in hardware
 | RAM7A | Boot time PBIST check of SRAM | SL_SelfTest_PBIST
 | RAM7B | Periodic PBIST check of SRAM | SL_SelfTest_PBIST
 | RAM8 | Bit multiplexing in SRAM array | Not Applicable | Feature in hardware
 | RAM9 | Periodic hardware CRC check of SRAM contents | Not Applicable</ref SL_CRC_Calculate
 | RAM10 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | RAM11 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
 | RAM12 | Software test of SRAM wrapper redundant address decode and ECC | SL_SelfTest_SRAM
 | RAM13 | "Scrubbing" feature to correct detected single bit errors | Not available | Not in scope for this release
Memory Interconnect | MEM1 | Error trapping | Not available | Not in scope for this release
 | MEM2A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | MEM2B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | MEM2C | External watchdog | Not Applicable | Handled by the safety application
 | MEM3 | Information redundancy | Not Applicable | Information redundancy techniques are defined by application
 | MEM4A | Boot time software test of basic functionality including error tests | Not available | Not in scope for this release
 | MEM4B | Periodic software test of basic functionality including error tests | Not available | Not in scope for this release
 | MEM5 | Transaction ECC(data) | Not available | Not in scope for this release
 | MEM6 | Transaction parity (address/control) | Not available | Not in scope for this release
 | MEM7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | MEM8 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
 | MEM9 | Interconnect hardware checker | Not available | Not in scope for this release
 | MEM10 | Boot time execution of interconnect self test | Not available | Not in scope for this release
 | MEM11 | Periodic execution of interconnect self test | Not available | Not in scope for this release
Main Peripheral Interconnect | PER1 | Error trapping | Not available | Not in scope for this release
 | PER2A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | PER2B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | PER2C | External watchdog | Not Applicable | Handled by safety application
 | PER3 | Information redundancy | Not Applicable | Information redundancy techniques are defined by application
 | PER4A | Boot time software test of basic functionality | Not available | Not in scope for this release
 | PER4B | Periodic software test of basic functionality | Not available | Not in scope for this release
 | PER5 | NMPU | Not Applicable | Handled by operation system/safety application
Peripheral Interconnect Segment 1 | P1T1 | Error trapping | Not available | Not in scope for this release
 | P1T2A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | P1T2B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | P1T2C | External watchdog | Not Applicable | Handled by the safety application
 | P1T3 | Information redundancy | Not Applicable | Information redundancy techniques are defined by application
 | P1T4A | Boot time software test of basic functionality(Is this protection and master id filtering ) | Not available | Not in scope for this release
 | P1T4B | Periodic software test of basic functionality | Not available | Not in scope for this release
 | P1T5 | Bus master filtering (slave memory protection) | Not Applicable | Software configuration of bus master filtering is done by application.
 | P1T6 | PCR access management | Not Applicable | Software configuration of PCR Access Management is done by application.
 | P1T7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | P1T8 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
Peripheral Interconnect Segment 2 | P2T1 | Error trapping | Not available | Not in scope for this release
 | P2T2A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | P2T2B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | P2T2C | External watchdog | Not Applicable | Handled by the safety application
 | P2T3 | Information redundancy | Not Applicable | Information redundancy techniques are defined by application
 | P2T4A | Boot time software test of basic functionality | Not available | Not in scope for this release
 | P2T4B | Periodic software test of basic functionality | Not available | Not in scope for this release
 | P2T5 | Bus master filtering (slave memory protection) | Not Applicable | Software configuration of bus master filtering is
 | P2T6 | PCR access management | Not Applicable | Software configuration of PCR Access Management is
 | P2T7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | P2T8 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
Peripheral Interconnect Segment 3 | P3T1 | Error trapping | Not available | Not in scope for this release
 | P3T2A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | P3T2B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | P3T2C | External watchdog | Not Applicable | Handled by the safety application
 | P3T3 | Information redundancy | Not Applicable | Information redundancy techniques are defined by application
 | P3T4A | Boot time software test of basic functionality | Not available | Not in scope for this release
 | P3T4B | Periodic software test of basic functionality | Not available | Not in scope for this release
 | P3T5 | Bus master filtering (slave memory protection) | Not Applicable | Software configuration of bus master filtering is
 | P3T6 | PCR access management | Not Applicable | Software configuration of PCR Access Management is
 | P3T7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | P3T8 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
EFuse Static Configuration | EFU1 | Boot time autoload self-test | SL_SelfTest_EFuse
 | EFU2 | E-fuse ECC | SL_SelfTest_EFuse
 | EFU3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | EFU4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
One Time Programmable (OTP) Flash Static Configuration | OTP1 | Boot time autoload self-test (clarification as it is meant for Fault avoidance) | Not available | Not in scope for this release
 | OTP2 | OTP ECC | Not available | Not in scope for this release
 | OTP3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | OTP4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
Input/Output (I/O) Multiplexing (IOMM) | IOM1 | Locking control registers | Not Applicable | Hardware feature with no error response for faults
 | IOM2 | Master ID filtering | Not available | Not in scope for this release
 | IOM3 | Error trapping | Not available | Not in scope for this release
 | IOM4 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | IOM5A | Boot time software test of function using peripherals with analog I/O loopback including error tests | Not available | Not in scope for this release
 | IOM5B | Periodic software test of function using peripherals with analog I/O loopback including error tests | Not available | Not in scope for this release
 | IOM6 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
Vectored Interrupt Module (VIM) | VIM1 | VIM SRAM Data ECC | Not available | Not in scope for this release
 | VIM2A | Boot time PBIST check of VIM SRAM | SL_SelfTest_PBIST
 | VIM2B | Periodic PBIST check of VIM SRAM | SL_SelfTest_PBIST
 | VIM3 | Bit multiplexing in VIM SRAM array | Not Applicable | Feature in hardware
 | VIM4 | Periodic hardware CRC check of VIM SRAM contents | SL_CRC_Calculate
 | VIM5A | Boot time software test of VIM functionality including error tests | Not Applicable | Defined by safety application
 | VIM5B | Periodic software test of VIM functionality including error tests | Not Applicable | Defined by safety application
 | VIM6 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | VIM7 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
 | VIM8A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | VIM8B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | VIM8C | External watchdog | Not Applicable | Handled by the safety application
 | VIM9 | Hardware 1oo2 comparison of VIM | Not Applicable | Feature in hardware
Real Time Interrupt (RTI) Operating System Timer | RTI1 | 1oo2 software voting using secondary free running counter | Not Applicable | OS configures the RTI OS timer
 | RTI2A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | RTI2B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | RTI2C | External watchdog | Not Applicable | Handled by the safety application
 | RTI3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | RTI4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
Direct Memory Access (DMA) | DMA1 | Memory protection unit for bus master accesses | Not Applicable | Handled by operation system/safety application
 | DMA2 | Non-privileged bus master access | Not available | Not in scope for this release
 | DMA3 | Information redundancy | Not Applicable | Information redundancy techniques are defined by application
 | DMA4 | DMA SRAM Data ECC | SL_SelfTest_DMA
 | DMA5A | Boot time PBIST check of DMA SRAM | SL_SelfTest_PBIST
 | DMA5B | Periodic PBIST check of DMA SRAM | SL_SelfTest_PBIST
 | DMA6 | Bit multiplexing in DMA SRAM array | Not Applicable | Feature in hardware
 | DMA7 | Periodic hardware CRC check of DMA SRAM contents | SL_CRC_Calculate
 | DMA8 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | DMA9A | Boot time software test of basic functionality including error tests | Not Applicable | Defined by safety application
 | DMA9B | Periodic software test of basic functionality including error tests | Not Applicable | Defined by safety application
 | DMA10 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application</td
 | DMA11 | Detection of soft error on critical registers | Not available | Not in scope for this release
 | DMA12 | NMPU | Not Applicable | Handled by operation system/safety application
High-End Timer (N2HET) Including HET Transfer Unit (HTU) | HET1 | Memory protection unit for bus master accesses | Not Applicable | Handled by operation system/safety application
 | HET2 | Information redundancy | Not Applicable | Information redundancy techniques are defined by application
 | HET3 | Use of DCC as program sequence watchdog | Not Applicable | Configured by safety application
 | HET4 | Monitoring by second N2HET | Not Applicable | Configured by safety application
 | HET5A | Boot time software test of function using I/O loopback | Not available | Not in scope for this release
 | HET5B | Periodic software test of function using I/O loopback | Not available | Not in scope for this release
 | HET6 | N2HET/HTU SRAM Data Parity | Not available | Not in scope for this release
 | HET7A | Boot time PBIST check of N2HET/HTU SRAM | SL_SelfTest_PBIST
 | HET7B | Periodic PBIST check of N2HET/HTU SRAM | SL_SelfTest_PBIST
 | HET8 | Bit multiplexing in N2HET/HTU SRAM array | Not Applicable | Feature in hardware
 | HET9 | Periodic hardware CRC check of N2HET/HTU SRAM contents | SL_CRC_Calculate
 | HET10 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | HET11 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
 | HET12A | Boot time Hardware self test | Not available | Not in scope for this release
 | HET12B | Run time Hardware self test | Not available | Not in scope for this release
Multi-Buffered Analog to Digital Converter (MibADC) | ADC1 | Boot time input self test | Not available | Not in scope for this release
 | ADC2A | Boot time converter calibration | Not available | Not in scope for this release
 | ADC2B | Periodic converter calibration | Not available | Not in scope for this release
 | ADC3 | Information redundancy techniques | Not Applicable | Information redundancy techniques are defined by application
 | ADC4 | MibADC SRAM Data Parity | Not available | Not in scope for this release
 | ADC5A | Boot time PBIST check of MibADC SRAM | SL_SelfTest_PBIST
 | ADC5B | Periodic PBIST check of MibADC SRAM | SL_SelfTest_PBIST
 | ADC6 | Bit multiplexing in MibADC SRAM array | Not Applicable | Feature in hardware
 | ADC7 | Periodic hardware CRC check of MibADC SRAM contents | SL_CRC_Calculate
 | ADC8 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | ADC9 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
Enhanced Pulse Width Modulators (ePWM) | PWM1A | Boot time software test of function | Not Applicable | Defined by the application
 | PWM1B | Periodic software test of function | Not Applicable | Defined by the application
 | PWM2 | Information redundancy techniques | Not Applicable | Information redundancy techniques are defined by application
 | PWM3 | Monitoring by eCAP or N2HET | Not Applicable | Configuration in application
 | PWM4 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | PWM5 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
Enhanced Capture (eCAP) | CAP1A | Boot time software test of function | Not Applicable | Defined by the application
 | CAP1B | Periodic software test of function | Not Applicable | Defined by the application
 | CAP2 | Information redundancy techniques | Not Applicable | Information redundancy techniques are defined by application
 | CAP3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | CAP4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
Enhance Quadrature Encoder Pulse (eQEP) | QEP1A | Boot time software test of function | Not Applicable | Defined by the application
 | QEP1B | Periodic software test of function | Not Applicable | Defined by the application
 | QEP2 | Information redundancy techniques | Not Applicable | Information redundancy techniques are defined by application
 | QEP3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | QEP4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application.
Multi-Buffered Serial Peripheral Interface (MibSPI) | MSP1A | Boot time software test of function using I/O loopback | Not available | Not in scope for this release
 | MSP1B | Periodic software test of function using I/O loopback | Not available | Not in scope for this release
 | MSP2 | Parity in message | Not Applicable | Configuration defined in application
 | MSP3 | Information redundancy techniques | Not Applicable | Information redundancy techniques are defined by application
 | MSP4 | MibSPI SRAM Data ECC | SL_SelfTest_MibSPI
 | MSP5A | Boot time PBIST check of MibSPI SRAM | SL_SelfTest_PBIST
 | MSP5B | Periodic PBIST check of MibSPI SRAM | SL_SelfTest_PBIST
 | MSP6 | Bit multiplexing in MibSPI SRAM array | Not Applicable | Feature in hardware
 | MSP7 | Periodic hardware CRC check of MibSPI SRAM contents | SL_CRC_Calculate
 | MSP8 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | MSP9 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
Inter-Integrated Circuit (I2C) | IIC1A | Boot time software test of function | Not Applicable | Defined by the application
 | IIC1B | Periodic software test of function | Not Applicable | Defined by the application
 | IIC2 | Information redundancy techniques | Not Applicable | Information redundancy techniques are defined by application
 | IIC3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application.
 | IIC4 | Software readback of written configuration | Not Applicable | Static configuration is defined by the application.
Serial Communications Interface (SCI) | SCI1A | Boot time software test of function using I/O loopback | Not available | Not in scope for this release
 | SCI1B | Periodic software test of function using I/O loopback | Not available | Not in scope for this release
 | SCI2 | Information redundancy techniques | Not Applicable | Information redundancy techniques are defined by application
 | SCI3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | SCI4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
Local Interconnect Network (LIN) | LIN1A | Boot time software test of function using I/O loopback | Not available | Not in scope for this release
 | LIN1B | Periodic software test of function using I/O loopback | Not available | Not in scope for this release
 | LIN2 | Information redundancy techniques including end to end safing | Not Applicable | Information redundancy techniques are defined by application
 | LIN3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | LIN4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
Controller Area Network (DCAN) | CAN1A | Boot time software test of function using I/O loopback | Not available | Not in scope for this release
 | CAN1B | Periodic software test of function using I/O loopback | Not available | Not in scope for this release
 | CAN2 | Information redundancy techniques including end to end safing | Not Applicable | Information redundancy techniques are defined by application
 | CAN3 | DCAN SRAM Data ECC | SL_SelfTest_CAN
 | CAN4A | Boot time PBIST check of DCAN SRAM | SL_SelfTest_PBIST
 | CAN4B | Periodic PBIST check of DCAN SRAM | SL_SelfTest_PBIST
 | CAN5 | Bit multiplexing in DCAN SRAM array | Not Applicable | Feature in hardware
 | CAN6 | Periodic hardware CRC check of DCAN SRAM contents | SL_CRC_Calculate
 | CAN7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | CAN8 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
FlexRay Including FlexRay Transfer Unit (FTU) | FRY1 | Memory protection unit for bus master accesses | Not Applicable | Handled by operation system/safety application
 | FRY2 | Non-privileged bus master access | Not available | Not in scope for this release
 | FRY3A | Boot time software test of function using I/O loopback in PHY | Not available | Not in scope for this release
 | FRY3B | Periodic software test of function using I/O loopback in transceiver | Not available | Not in scope for this release
 | FRY4 | Information redundancy techniques including end to end safing | Not Applicable | Information redundancy techniques are defined by application
 | FRY5 | 1oo2 Voting using Both FlexRay Channels | Not Applicable | Defined by application
 | FRY6 | FlexRay and FTU SRAM Data ECC | Not available | Not in scope for this release
 | FRY7A | Boot time PBIST check of FlexRay and FTU SRAM | SL_SelfTest_PBIST
 | FRY7B | Periodic PBIST check of FlexRay and FTU SRAM | SL_SelfTest_PBIST
 | FRY8 | Bit multiplexing in FlexRay and FTU SRAM array | Not Applicable | Feature in hardware
 | FRY9 | Periodic hardware CRC check of FlexRay and FTU SRAM contents | SL_CRC_Calculate
 | FRY10 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | FRY11 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
General Purpose Input/Output (GIO) | GIO1A | Boot time software test of function using I/O checking | Not available | Not in scope for this release
 | GIO1B | Periodic software test of function using I/O checking | Not available | Not in scope for this release
 | GIO2 | Information redundancy techniques | Not Applicable | Information redundancy techniques are defined by application
 | GIO3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | GIO4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
Ethernet | ETH1 | Non-privileged bus master access | Not Applicable | Handled by operation system/safety application
 | ETH2A | Boot time software test of function using I/O loopback in PHY | Not available | Not in scope for this release
 | ETH2B | Periodic software test of function using I/O loopback in PHY | Not available | Not in scope for this release
 | ETH3 | Information redundancy techniques including end to end safing | Not Applicable | Information redundancy techniques are defined by application
 | ETH4A | Boot time PBIST check of Ethernet SRAM | SL_SelfTest_PBIST
 | ETH4B | Periodic PBIST check of Ethernet SRAM | SL_SelfTest_PBIST
 | ETH5 | Bit multiplexing in Ethernet SRAM array | Not Applicable | Feature in hardware
 | ETH6 | Periodic hardware CRC check of Ethernet SRAM contents | SL_CRC_Calculate
 | ETH7 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | ETH8 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
 | ETH9 | NMPU | Not Applicable | Handled by operation system/safety application
External Memory Interface (EMIF) | EMF1 | Information redundancy techniques | Not Applicable | Information redundancy techniques are defined by
 | EMF2A | Boot time hardware CRC check of external memory | SL_CRC_Calculate
 | EMF2B | Periodic hardware CRC check of external memory | SL_CRC_Calculate
 | EMF3 | Periodic software readback of static configuration registers | Not Applicable | Static configuration is defined by the application
 | EMF4 | Software readback of written configuration | Not Applicable | Written configuration is defined by the application
Joint Technical Action Group (JTAG) Debug/Trace/ Calibration Access | JTG1 | Hardware disable of JTAG port | Not Applicable | Hardware configuration
 | JTG2 | Lockout of JTAG access using AJSM | Not Applicable | Configured by application
 | JTG3A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | JTG3B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | JTG3C | External watchdog | Not Applicable | Handled by the safety application
Cortex-R5F Central Processing Unit (CPU) Debug and Trace | DBG1 | Hardware disable of JTAG port | Not Applicable | Hardware configuration
 | DBG2 | Lockout of JTAG access using AJSM | Not Applicable | Configured by application
 | DBG3 | Use MPUs to block access to memory-mapped debug | Not Applicable | Configured by application
 | DBG4 | Use of CoreSight debug logic key enable scheme | Not Applicable | Configured by application
 | DBG5A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | DBG5B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | DBG5C | External watchdog | Not Applicable | Handled by the safety application
Data Modification Module (DMM) | DMM1 | Hardware disable of JTAG port | Not Applicable | Hardware configuration
 | DMM2 | Lockout of JTAG access using AJSM | Not Applicable | Configured by application
 | DMM3 | Use MPUs to block access to memory-mapped debug | Not Applicable | Configured by application
 | DMM4 | Disable DMM pin interface | Not Applicable | Hardware configuration
 | DMM5A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | DMM5B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | DMM5C | External watchdog | Not Applicable | Handled by the safety application
RAM Trace Port (RTP) | RTP1 | Hardware disable of JTAG port | Not Applicable | Hardware configuration
 | RTP2 | Lockout of JTAG access using AJSM | Not Applicable | Watchdog configuration is in application
 | RTP3 | Use MPUs to block access to memory-mapped debug | Not Applicable | Configured by application
 | RTP4 | Disable RTP pin interface | Not Applicable | Hardware configuration
 | RTP5A | Internal watchdog - DWD | Not Applicable | Watchdog configuration is in application
 | RTP5B | Internal watchdog - DWWD | Not Applicable | Watchdog configuration is in application
 | RTP5C | External watchdog | Not Applicable | Handled by the safety application
Parameter Overlay Module (POM) | POM1 | Hardware disable of JTAG port | Not Applicable | Hardware configuration
 | POM2 | Lockout of JTAG access using AJSM | Not Applicable | Configured by application
 | POM3 | Use MPUs to block access to memory-mapped debug | Not Applicable | Configured by application


SafeTI™ Diagnostic Library: Modules

Modules
Here is a list of all modules:
[detail level 12]
Types & Module register definition files
▼ configuration items for SafeTI™ Hercules™ Diagnostic library
Stack Size for various ARM modes
delay value for nerror clearing
SRAM Range defines
macros for loggin infomration
Log buffer counts
macros for enabling profiling
Error codes used in log functions
Function IDs for error/result log buffers
structure for storing the profiling information for selftest and pbist.
Macros for F021Flash ECC Configuration
Macros for ESM Channel assignments
SRAM Range defines
Macros for PBIST RAM groups
Macros for PBIST Algorithms


SafeTI™ Diagnostic Library: Types & Module register definition files

Types & Module register definition files


SafeTI™ Diagnostic Library: configuration items for SafeTI™ Hercules™ Diagnostic library

Modules
configuration items for SafeTI™ Hercules™ Diagnostic library

Modules

Stack Size for various ARM modes
delay value for nerror clearing
SRAM Range defines
macros for loggin infomration
Log buffer counts
macros for enabling profiling

Detailed Description

configuration items for the SafeTI™ Hercules™ Diagnostic library


SafeTI™ Diagnostic Library: Stack Size for various ARM modes

Macros
Stack Size for various ARM modes
configuration items for SafeTI&trade; Hercules&trade; Diagnostic library

Macros

#define | STACK_SIZE_MODE_SVC 1024u
#define | STACK_SIZE_MODE_FIQ 1024u
#define | STACK_SIZE_MODE_IRQ 1024u
#define | STACK_SIZE_MODE_ABT 1024u
#define | STACK_SIZE_MODE_UND 1024u
#define | STACK_SIZE_MODE_SYS 1024u

Detailed Description

Following macros define the size of stacks for the ARM modes

Macro Definition Documentation

#define STACK_SIZE_MODE_ABT 1024u

Stack size for ABT mode

#define STACK_SIZE_MODE_FIQ 1024u

Stack size for FIQ mode

#define STACK_SIZE_MODE_IRQ 1024u

Stack size for IRQ mode

#define STACK_SIZE_MODE_SVC 1024u

Stack size for SVC mode

#define STACK_SIZE_MODE_SYS 1024u

Stack size for SYS mode

#define STACK_SIZE_MODE_UND 1024u

Stack size for UND mode


SafeTI™ Diagnostic Library: delay value for nerror clearing

Macros
delay value for nerror clearing
configuration items for SafeTI&trade; Hercules&trade; Diagnostic library

Macros

#define NERROR_HOLD_DELAY (uint32)10u

Detailed Description

Delay counter used before clearing nERROR. Delay is implemented using a while loop & is not calibrated. This function is used by Self test APIs that activate nERROR

Macro Definition Documentation

#define NERROR_HOLD_DELAY (uint32)10u

Delay counter used before clearing nERROR. Delay is implemented using a while loop & is not calibrated. This function is used by Self test APIs that activate nERROR


SafeTI™ Diagnostic Library: SRAM Range defines

Macros
SRAM Range defines
configuration items for SafeTI&trade; Hercules&trade; Diagnostic library

Macros

#define | SRAM_START (uint32)0x08000000u
#define | SRAM_END (uint32)0x0807FFFFu
#define | SRAM_END (uint32)0x0803FFFFu

Detailed Description

Following macros are used to define the range of TCM RAM

Macro Definition Documentation

#define SRAM_END (uint32)0x0807FFFFu

End address of SRAM

End address of TCM SRAM

#define SRAM_END (uint32)0x0803FFFFu

End address of SRAM

End address of TCM SRAM

#define SRAM_START (uint32)0x08000000u

Start address of TCM SRAM


SafeTI™ Diagnostic Library: macros for loggin infomration

Macros
macros for loggin infomration
configuration items for SafeTI&trade; Hercules&trade; Diagnostic library

Macros

#define | FUNCTION_PARAM_CHECK_ENABLED 1u
#define | FUNC_ENTRY_COND_CHECK_ENABLED 1u
#define | FUNC_RESULT_LOG_ENABLED 0u

Detailed Description

!!! BEFORE ENABLING THESE MACROS !!! If the functions are called in non-privilege mode, the buffers must be suitably placed (& MPU regions updated) so that the buffers are Read & Writable from non-priv tasks

Following macros are used for enabling or disabling logging and entry and param check in api's

Macro Definition Documentation

#define FUNC_ENTRY_COND_CHECK_ENABLED 1u

When defined enables the entry codition check at function entry

#define FUNC_RESULT_LOG_ENABLED 0u

When enabled logs the function results to a pre-determined buffer

#define FUNCTION_PARAM_CHECK_ENABLED 1u

When defined enables the parameter check at function entry


SafeTI™ Diagnostic Library: Log buffer counts

Macros
Log buffer counts
configuration items for SafeTI&trade; Hercules&trade; Diagnostic library

Macros

#define | LOG_RESULT_BUFFER_COUNT 0u
#define | LOG_ERROR_BUFFER_COUNT 32u

Detailed Description

Following macros defines the size of the log buffers for error & result buffers

Macro Definition Documentation

#define LOG_ERROR_BUFFER_COUNT 32u

Size of the error buffer

#define LOG_RESULT_BUFFER_COUNT 0u

Logging results is disabled


SafeTI™ Diagnostic Library: macros for enabling profiling

Macros
macros for enabling profiling
configuration items for SafeTI&trade; Hercules&trade; Diagnostic library

Macros

#define FUNCTION_PROFILING_ENABLED 0u

Detailed Description

!!! BEFORE ENABLING THESE MACROS !!! If the functions are called in non-privilege mode, the buffers must be suitably placed (& MPU regions updated) so that the buffers are Read & Writable from non-priv tasks

Following macros are used for enabling or disabling profiling in the code

Macro Definition Documentation

#define FUNCTION_PROFILING_ENABLED 0u

When defined enables the profiling of the functions


SafeTI™ Diagnostic Library: Error codes used in log functions

Macros
Error codes used in log functions

Macros

#define | ERR_TYPE_ENTRY_CON 0x00000001u
#define | ERR_TYPE_PARAM 0x00000002u

Detailed Description

Following macros are used to indicate errors in function entry point

Macro Definition Documentation

#define ERR_TYPE_ENTRY_CON 0x00000001u

Indicates error due to invalid entry condition

#define ERR_TYPE_PARAM 0x00000002u

Indicates error due to invalid parameter


SafeTI™ Diagnostic Library: Function IDs for error/result log buffers

Enumerations
Function IDs for error/result log buffers

Enumerations

enum _sl_log_func_id {
FUNC_ID_ST_SRAM =0xA, FUNC_ID_ST_FLASH, FUNC_ID_ST_ADC, FUNC_ID_ST_PBIST,
FUNC_ID_ST_PBIST_STATUS, FUNC_ID_ST_CCMR4F, FUNC_ID_ST_CCMR4F_STATUS, FUNC_ID_ST_CCMR5F,
FUNC_ID_ST_CCMR5F_STATUS, FUNC_ID_ST_PSCON, FUNC_ID_ST_STC, FUNC_ID_ST_EFUSE,
FUNC_ID_ST_L2L3INTERCONNECT, FUNC_ID_ST_DMA, FUNC_ID_ST_CAN, FUNC_ID_ST_SPI
}

Detailed Description

Following macros are to be used by the error & result log functions to indicate the function ID

Enumeration Type Documentation

enum _sl_log_func_id
Enumerator
FUNC_ID_ST_SRAM | SRAM SelfTest API
FUNC_ID_ST_FLASH | Flash selftest API
FUNC_ID_ST_ADC | ADC SelfTest API
FUNC_ID_ST_PBIST | PBIST SelfTest API
FUNC_ID_ST_PBIST_STATUS | PBIST Status function
FUNC_ID_ST_CCMR4F | CCM SelfTest API
FUNC_ID_ST_CCMR4F_STATUS | CCM Selft test status query API
FUNC_ID_ST_CCMR5F | CCM SelfTest API
FUNC_ID_ST_CCMR5F_STATUS | CCM Selft test status query API
FUNC_ID_ST_PSCON | PSCON selftest API
FUNC_ID_ST_STC | STC selftest API
FUNC_ID_ST_EFUSE | EFuse SelfTest API
FUNC_ID_ST_L2L3INTERCONNECT | L2L3 interconnect SelfTest API
FUNC_ID_ST_DMA | DMA selftest API
FUNC_ID_ST_CAN | CAN selftest API
FUNC_ID_ST_SPI | MibSPI SelfTest API


SafeTI™ Diagnostic Library: structure for storing the profiling information for selftest and pbist.

Data Structures
structure for storing the profiling information for selftest and pbist.

Data Structures

struct | _SL_Profile_Struct
structure for storing the profiling information of each testtype. More...
struct | _SL_Profile_Pbist_Struct
structure for storing the profiling information of PBIST tests on various ramgroups fir different algorithms. More...

Detailed Description

Following strucutures are used in the profiling of pbist and selftest/fault injection API.


SafeTI™ Diagnostic Library: _SL_Profile_Struct Struct Reference

  • Data Structures
  • Data Structure Index
_SL_Profile_Struct Struct Reference
structure for storing the profiling information for selftest and pbist.

structure for storing the profiling information of each testtype. More...

#include <sl_log.h>

Detailed Description

structure for storing the profiling information of each testtype.

The documentation for this struct was generated from the following file:
  • safety_library/include/sl_log.h


SafeTI™ Diagnostic Library: _SL_Profile_Pbist_Struct Struct Reference

  • Data Structures
  • Data Structure Index
_SL_Profile_Pbist_Struct Struct Reference
structure for storing the profiling information for selftest and pbist.

structure for storing the profiling information of PBIST tests on various ramgroups fir different algorithms. More...

#include <sl_log.h>

Detailed Description

structure for storing the profiling information of PBIST tests on various ramgroups fir different algorithms.

The documentation for this struct was generated from the following file:
  • safety_library/include/sl_log.h


SafeTI™ Diagnostic Library: Macros for F021Flash ECC Configuration

Macros
Macros for F021Flash ECC Configuration

Macros

#define | FLASHECC_E0FEN (uint32)(1U << 10)
#define | FLASHECC_EZFEN (uint32)(1U << 9)
#define | FLASHECC_EPEN (uint32)(1U << 8)
#define | FLASHECC_EOCV (uint32)(1U << 5)
#define | FLASHECC_EZCV (uint32)(1U << 4)
#define | FLASHECC_DEFAULT (uint32)(F021F_FEDACCTRL1_E0FEN | F021F_FEDACCTRL1_EZFEN)

Detailed Description

Following macros are to be used for the ctrlFlags parameter of SL_Init_ECCFlash API

Macro Definition Documentation

#define FLASHECC_DEFAULT (uint32)(F021F_FEDACCTRL1_E0FEN | F021F_FEDACCTRL1_EZFEN)

Default flag combination

#define FLASHECC_E0FEN (uint32)(1U << 10)

Enable Error on Fail event

#define FLASHECC_EOCV (uint32)(1U << 5)

Enable One Condition valid

#define FLASHECC_EPEN (uint32)(1U << 8)

Enable Error profiling

#define FLASHECC_EZCV (uint32)(1U << 4)

Enable Zero Condition Valid

#define FLASHECC_EZFEN (uint32)(1U << 9)

Enable Error on Zero Fail event


SafeTI™ Diagnostic Library: Macros for ESM Channel assignments

Macros
Macros for ESM Channel assignments

Macros

#define | ESM_G3ERR_EFUSE_AUTOLOAD_ERR (uint32)(1u)
#define | ESM_G3ERR_B0TCM_ECC_UNCORR (uint32)(3u)
#define | ESM_G3ERR_B1TCM_ECC_UNCORR (uint32)(5u)
#define | ESM_G3ERR_FMC_UNCORR (uint32)(7u)
#define | ESM_G2ERR_CCMR4_COMP (uint32)(2u)
#define | ESM_G2ERR_B0TCM_UNCORR (uint32)(6u)
#define | ESM_G2ERR_B1TCM_UNCORR (uint32)(8u)
#define | ESM_G2ERR_B0TCM_ADDPAR (uint32)(10u)
#define | ESM_G2ERR_B1TCM_ADDPAR (uint32)(12u)
#define | ESM_G2ERR_FMC_UNCORR (uint32)(4u)
#define | ESM_G2ERR_FLASH_LIVLCK (uint32)(16u)
#define | ESM_G2ERR_RTI_WWD_NMI (uint32)(24u)
#define | ESM_G1ERR_FMC_CORR (uint32)(6u)
#define | ESM_G1ERR_PLL1_SLIP (uint32)(10u)
#define | ESM_G1ERR_CLOCKMON_INTR (uint32)(11u)
#define | ESM_G1ERR_VIMRAM_PARITY (uint32)(15u)
#define | ESM_G1ERR_B0TCM_CORRERR (uint32)(26u)
#define | ESM_G1ERR_B1TCM_CORRERR (uint32)(28u)
#define | ESM_G1ERR_DCC1_ERR (uint32)(30u)
#define | ESM_G1ERR_CCMR4_SELFTEST (uint32)(31u)
#define | ESM_G1ERR_EEPROM_CORRERR (uint32)(35u)
#define | ESM_G1ERR_EEPROM_UNCORRERR (uint32)(36u)
#define | ESM_G1ERR_PSCON_COMPARE_ERR (uint32)(38u)
#define | ESM_G1ERR_PSCON_SELTEST_ERR (uint32)(39u)
#define | ESM_G1ERR_PLL2_SLIP (uint32)(42u)
#define | ESM_G1ERR_DCC2_ERR (uint32)(62u)
#define | ESM_G1ERR_EFUSE_ERR_OTHER (uint32)(40u)
#define | ESM_G1ERR_EFUSE_SELTEST_ERR (uint32)(41u)
#define | ESM_G2ERR_CCMR5_CPUCOMP_ERR (uint32)(2u)
#define | ESM_G2ERR_CCMR5_VIMCOMP_ERR (uint32)(25u)
#define | ESM_G2ERR_CCMR5_INMCOMP_ERR (uint32)(26u)
#define | ESM_G2ERR_CCMR5_PDCOMP_ERR (uint32)(28u)
#define | ESM_G2ERR_CR5_BUSERR (uint32)(3u)
#define | ESM_G2ERR_L2RAMW_UNCORR_B (uint32)(7u)
#define | ESM_G1ERR_L2RAMW_CORRERR (uint32)(26u)
#define | ESM_G2ERR_EPC_UNCORR (uint32)(21u)
#define | ESM_G1ERR_EPC_SERR (uint32)(4u)
#define | ESM_G1ERR_CCMR5_SELFTEST (uint32)(31u)
#define | ESM_G1ERR_CCMR5_OPERATING_STATUS (uint32)(92u)
#define | ESM_G1ERR_DMA_ECC_SBERR (uint32)(82u)
#define | ESM_G1ERR_DMA_ECC_UNCORR (uint32)(3u)
#define | ESM_G1ERR_CAN1_ECC_SBERR (uint32)(73u)
#define | ESM_G1ERR_CAN1_ECC_UNCORR (uint32)(21u)
#define | ESM_G1ERR_CAN2_ECC_SBERR (uint32)(74u)
#define | ESM_G1ERR_CAN2_ECC_UNCORR (uint32)(23u)
#define | ESM_G1ERR_CAN3_ECC_SBERR (uint32)(75u)
#define | ESM_G1ERR_CAN3_ECC_UNCORR (uint32)(22u)
#define | ESM_G1ERR_CAN4_ECC_SBERR (uint32)(76u)
#define | ESM_G1ERR_CAN4_ECC_UNCORR (uint32)(51u)
#define | ESM_G1ERR_SPI1_ECC_SBERR (uint32)(77u)
#define | ESM_G1ERR_SPI2_ECC_SBERR (uint32)(78u)
#define | ESM_G1ERR_SPI3_ECC_SBERR (uint32)(79u)
#define | ESM_G1ERR_SPI4_ECC_SBERR (uint32)(80u)
#define | ESM_G1ERR_SPI5_ECC_SBERR (uint32)(81u)
#define | ESM_G1ERR_SPI1_ECC_UNCORR (uint32)(17u)
#define | ESM_G1ERR_SPI2_ECC_UNCORR (uint32)(49u)
#define | ESM_G1ERR_SPI3_ECC_UNCORR (uint32)(18u)
#define | ESM_G1ERR_SPI4_ECC_UNCORR (uint32)(50u)
#define | ESM_G1ERR_SPI5_ECC_UNCORR (uint32)(24u)

Detailed Description

Following macros are used by the ESM Handler as a parameter (channel) to the application callback. Refer to ESM_Application_Callback definition for details

Naming Convention: ESM_G<number>ERR_<module>_<error type>

Macro Definition Documentation

#define ESM_G1ERR_B0TCM_CORRERR (uint32)(26u)

ESM Group 1 - RAM Even bank (B0TCM) correctable error

#define ESM_G1ERR_B1TCM_CORRERR (uint32)(28u)

ESM Group 1 - RAM Odd bank (B1TCM) correctable error

#define ESM_G1ERR_CAN1_ECC_SBERR (uint32)(73u)

ESM Group 1 - DCAN1

  • ECC single bit error
#define ESM_G1ERR_CAN1_ECC_UNCORR (uint32)(21u)

ESM Group 1 - DCAN1

  • ECC uncorrectable error
#define ESM_G1ERR_CAN2_ECC_SBERR (uint32)(74u)

ESM Group 1 - DCAN2

  • ECC single bit error
#define ESM_G1ERR_CAN2_ECC_UNCORR (uint32)(23u)

ESM Group 1 - DCAN2

  • ECC uncorrectable error
#define ESM_G1ERR_CAN3_ECC_SBERR (uint32)(75u)

ESM Group 1 - DCAN3

  • ECC single bit error
#define ESM_G1ERR_CAN3_ECC_UNCORR (uint32)(22u)

ESM Group 1 - DCAN3

  • ECC uncorrectable error
#define ESM_G1ERR_CAN4_ECC_SBERR (uint32)(76u)

ESM Group 1 - DCAN4

  • ECC single bit error
#define ESM_G1ERR_CAN4_ECC_UNCORR (uint32)(51u)

ESM Group 1 - DCAN4

  • ECC uncorrectable error
#define ESM_G1ERR_CCMR4_SELFTEST (uint32)(31u)

ESM Group 1 - CCMR4 Selftest error

#define ESM_G1ERR_CCMR5_OPERATING_STATUS (uint32)(92u)

ESM Group 1 - CCMR5 Selftests running

#define ESM_G1ERR_CCMR5_SELFTEST (uint32)(31u)

ESM Group 1 - CCMR5 Selftest error

#define ESM_G1ERR_CLOCKMON_INTR (uint32)(11u)

ESM Group 1 - Clock monitor interrupt

#define ESM_G1ERR_DCC1_ERR (uint32)(30u)

ESM Group 1 - DCC1 error

#define ESM_G1ERR_DCC2_ERR (uint32)(62u)

ESM Group 1 - DCC2 error

#define ESM_G1ERR_DMA_ECC_SBERR (uint32)(82u)

ESM Group 1 - DMA - ECC single bit error bit

#define ESM_G1ERR_DMA_ECC_UNCORR (uint32)(3u)

ESM Group 1 - DMA - ECC uncorrectable error

#define ESM_G1ERR_EEPROM_CORRERR (uint32)(35u)

ESM Group 1 - Flash EEPROM Correctable error

#define ESM_G1ERR_EEPROM_UNCORRERR (uint32)(36u)

ESM Group 1 - Flash EEPROM Uncorrectable error

#define ESM_G1ERR_EFUSE_ERR_OTHER (uint32)(40u)

ESM Group 1 - Power Domain Controller - Self-Test Error

#define ESM_G1ERR_EFUSE_SELTEST_ERR (uint32)(41u)

ESM Group 1 - Power Domain Controller - Self-Test Error

#define ESM_G1ERR_EPC_SERR (uint32)(4u)

ESM Group 1 - EPC - ECC single bit error

#define ESM_G1ERR_FMC_CORR (uint32)(6u)

ESM Group 1 - F021 Flash Correctable error (Bus 1 & 2)

#define ESM_G1ERR_L2RAMW_CORRERR (uint32)(26u)

ESM Group 1 - L2RAM correctable error

#define ESM_G1ERR_PLL1_SLIP (uint32)(10u)

ESM Group 1 - PLL1 Slip error

#define ESM_G1ERR_PLL2_SLIP (uint32)(42u)

ESM Group 1 - PLL2 Slip error

#define ESM_G1ERR_PSCON_COMPARE_ERR (uint32)(38u)

ESM Group 1 - Power Domain Controller - Compare Error

#define ESM_G1ERR_PSCON_SELTEST_ERR (uint32)(39u)

ESM Group 1 - Power Domain Controller - Self-Test Error

#define ESM_G1ERR_SPI1_ECC_SBERR (uint32)(77u)

ESM Group 1 - MIBSPI1 - ECC single bit error

#define ESM_G1ERR_SPI1_ECC_UNCORR (uint32)(17u)

ESM Group 1 - MIBSPI1 - ECC uncorrectable error

#define ESM_G1ERR_SPI2_ECC_SBERR (uint32)(78u)

ESM Group 1 - MIBSPI2 - ECC single bit error

#define ESM_G1ERR_SPI2_ECC_UNCORR (uint32)(49u)

ESM Group 1 - MIBSPI2 - ECC uncorrectable error

#define ESM_G1ERR_SPI3_ECC_SBERR (uint32)(79u)

ESM Group 1 - MIBSPI3 - ECC single bit error

#define ESM_G1ERR_SPI3_ECC_UNCORR (uint32)(18u)

ESM Group 1 - MIBSPI3 - ECC uncorrectable error

#define ESM_G1ERR_SPI4_ECC_SBERR (uint32)(80u)

ESM Group 1 - MIBSPI4 - ECC single bit error

#define ESM_G1ERR_SPI4_ECC_UNCORR (uint32)(50u)

ESM Group 1 - MIBSPI4 - ECC uncorrectable error

#define ESM_G1ERR_SPI5_ECC_SBERR (uint32)(81u)

ESM Group 1 - MIBSPI5 - ECC single bit error

#define ESM_G1ERR_SPI5_ECC_UNCORR (uint32)(24u)

ESM Group 1 - MIBSPI5 - ECC uncorrectable error

#define ESM_G1ERR_VIMRAM_PARITY (uint32)(15u)

ESM Group 1 - VIM RAM Parity error

#define ESM_G2ERR_B0TCM_ADDPAR (uint32)(10u)

ESM Group 2 - TCM RAM Even Bank (B0TCM)

  • Address bus parity error
#define ESM_G2ERR_B0TCM_UNCORR (uint32)(6u)

ESM Group 2 - TCM RAM Even Bank (B0TCM)

  • Uncorrectable error
#define ESM_G2ERR_B1TCM_ADDPAR (uint32)(12u)

ESM Group 2 - TCM RAM Odd Bank (B1TCM)

  • Address bus parity error
#define ESM_G2ERR_B1TCM_UNCORR (uint32)(8u)

ESM Group 2 - TCM RAM Odd Bank (B1TCM)

  • Uncorrectable error
#define ESM_G2ERR_CCMR4_COMP (uint32)(2u)

ESM Group 2 - CCMR4 Compare error

#define ESM_G2ERR_CCMR5_CPUCOMP_ERR (uint32)(2u)

ESM Group 2 - CCMR5 Compare error

#define ESM_G2ERR_CCMR5_INMCOMP_ERR (uint32)(26u)

ESM Group 2 - CCMR5 Compare error

#define ESM_G2ERR_CCMR5_PDCOMP_ERR (uint32)(28u)

ESM Group 2 - CCMR5 Compare error

#define ESM_G2ERR_CCMR5_VIMCOMP_ERR (uint32)(25u)

ESM Group 2 - CCMR5 Compare error

#define ESM_G2ERR_CR5_BUSERR (uint32)(3u)

ESM Group 2 - R5 Bus error

#define ESM_G2ERR_EPC_UNCORR (uint32)(21u)

ESM Group 2 - EPC - ECC uncorrectable error

#define ESM_G2ERR_FLASH_LIVLCK (uint32)(16u)

ESM Group 2 - Flash (ATCM - ECC Live lock detect)

#define ESM_G2ERR_FMC_UNCORR (uint32)(4u)

ESM Group 2 - F021Flash Uncorrectable error (address parity on bus1 accesses)

#define ESM_G2ERR_L2RAMW_UNCORR_B (uint32)(7u)

ESM Group 2 - L2RAM Uncorrectable error (Type B)

#define ESM_G2ERR_RTI_WWD_NMI (uint32)(24u)

ESM Group 2 - RTI Windowed WatchDog NMI

#define ESM_G3ERR_B0TCM_ECC_UNCORR (uint32)(3u)

ESM Group 3 - RAM Even Bank (B0TCM) Uncorrectable ECC error

#define ESM_G3ERR_B1TCM_ECC_UNCORR (uint32)(5u)

ESM Group 3 - RAM Odd bank (B1TCM) Uncorrectable ECC error

#define ESM_G3ERR_EFUSE_AUTOLOAD_ERR (uint32)(1u)

ESM Group 3 - eFuse Auto Load error

#define ESM_G3ERR_FMC_UNCORR (uint32)(7u)

ESM Group 3 - Flash Uncorrectable error (bus1 & bus2)


SafeTI™ Diagnostic Library: SRAM Range defines

Macros
SRAM Range defines

Macros

#define | TESTTYPE_MIN SRAM_ECC_ERROR_FORCING_1BIT
#define | TESTTYPE_MAX L3INTERCONNECT_FAULT_INJECT
#define | TESTTYPE_MAX MIBSPI_ECC_TEST_MODE_2BIT

Detailed Description

Following macros are used to define the range of TCM RAM

Macro Definition Documentation

#define TESTTYPE_MAX L3INTERCONNECT_FAULT_INJECT

ending testtype

#define TESTTYPE_MAX MIBSPI_ECC_TEST_MODE_2BIT

ending testtype

#define TESTTYPE_MIN SRAM_ECC_ERROR_FORCING_1BIT

starting testtype


SafeTI™ Diagnostic Library: Macros for PBIST RAM groups

Macros
Macros for PBIST RAM groups

Macros

#define | PBIST_RAMGROUP_01_PBIST_ROM (uint32)0x00000001u
#define | PBIST_RAMGROUP_01_PBIST_ROM (uint64)0x0000000001u
#define | PBIST_RAMGROUP_02_STC_ROM (uint32)0x00000002u
#define | PBIST_RAMGROUP_03_DCAN1 (uint32)0x00000004u
#define | PBIST_RAMGROUP_04_DCAN2 (uint32)0x00000008u
#define | PBIST_RAMGROUP_05_DCAN3 (uint32)0x00000010u
#define | PBIST_RAMGROUP_06_ESRAM1 (uint32)0x00000020u
#define | PBIST_RAMGROUP_07_MIBSPI1 (uint32)0x00000040u
#define | PBIST_RAMGROUP_08_MIBSPI3 (uint32)0x00000080u
#define | PBIST_RAMGROUP_09_MIBSPI5 (uint32)0x00000100u
#define | PBIST_RAMGROUP_10_VIM (uint32)0x00000200u
#define | PBIST_RAMGROUP_11_MIBADC1 (uint32)0x00000400u
#define | PBIST_RAMGROUP_12_DMA (uint32)0x00000800u
#define | PBIST_RAMGROUP_13_N2HET1 (uint32)0x00001000u
#define | PBIST_RAMGROUP_14_HETTU1 (uint32)0x00002000u
#define | PBIST_RAMGROUP_15_RTP (uint32)0x00004000u
#define | PBIST_RAMGROUP_16_FRAY (uint32)0x00008000u
#define | PBIST_RAMGROUP_17_FRAY (uint32)0x00010000u
#define | PBIST_RAMGROUP_18_MIBADC2 (uint32)0x00020000u
#define | PBIST_RAMGROUP_19_N2HET2 (uint32)0x00040000u
#define | PBIST_RAMGROUP_20_HETTU2 (uint32)0x00080000u
#define | PBIST_RAMGROUP_21_ESRAM5 (uint32)0x00100000u
#define | PBIST_RAMGROUP_22_ESRAM6 (uint32)0x00200000u
#define | PBIST_RAMGROUP_23_ETHERNET1 (uint32)0x00400000u
#define | PBIST_RAMGROUP_24_ETHERNET2 (uint32)0x00800000u
#define | PBIST_RAMGROUP_25_ETHERNET3 (uint32)0x01000000u
#define | PBIST_RAMGROUP_26_USB1 (uint32)0x02000000u
#define | PBIST_RAMGROUP_27_USB2 (uint32)0x04000000u
#define | PBIST_RAMGROUP_28_ESRAM8 (uint32)0x08000000u
#define | PBIST_RAMGROUP_29_RSVD (uint32)0x10000000u

Detailed Description

Enumerations for selecting the RAM Groups parameters for SL_SelfTest_PBIST API Naming Convention: PBIST_RAMGROUP_<RAM Group Select#>_<Peripheral Abbreviation>

Note : For details on RAM Group, Algorithm Mapping and supported types refer to device TRM

Macro Definition Documentation

#define PBIST_RAMGROUP_01_PBIST_ROM (uint32)0x00000001u

PBIST ROM

#define PBIST_RAMGROUP_01_PBIST_ROM (uint64)0x0000000001u

PBIST ROM

#define PBIST_RAMGROUP_02_STC_ROM (uint32)0x00000002u

STC ROM

#define PBIST_RAMGROUP_03_DCAN1 (uint32)0x00000004u

DCAN1 2 Port RAM

#define PBIST_RAMGROUP_04_DCAN2 (uint32)0x00000008u

DCAN2 2 Port RAM

#define PBIST_RAMGROUP_05_DCAN3 (uint32)0x00000010u

DCA3 2 Port RAM

#define PBIST_RAMGROUP_06_ESRAM1 (uint32)0x00000020u

ESRAM1 Single Port RAM

#define PBIST_RAMGROUP_07_MIBSPI1 (uint32)0x00000040u

MIBSPI1 2 Port RAM

#define PBIST_RAMGROUP_08_MIBSPI3 (uint32)0x00000080u

MIBSPI3 2 Port RAM

#define PBIST_RAMGROUP_09_MIBSPI5 (uint32)0x00000100u

MIBSPI5 2 Port RAM

#define PBIST_RAMGROUP_10_VIM (uint32)0x00000200u

VIM 2 Port RAM

#define PBIST_RAMGROUP_11_MIBADC1 (uint32)0x00000400u

MIBADC1 Port RAM

#define PBIST_RAMGROUP_12_DMA (uint32)0x00000800u

DMA Port RAM

#define PBIST_RAMGROUP_13_N2HET1 (uint32)0x00001000u

N2HET1 2 Port RAM

#define PBIST_RAMGROUP_14_HETTU1 (uint32)0x00002000u

HETTU1 2 Port RAM

#define PBIST_RAMGROUP_15_RTP (uint32)0x00004000u

RTP 2 Port RAM

#define PBIST_RAMGROUP_16_FRAY (uint32)0x00008000u

FlexRay 2 Port RAM

#define PBIST_RAMGROUP_17_FRAY (uint32)0x00010000u

FlexRay 1 Port RAM

#define PBIST_RAMGROUP_18_MIBADC2 (uint32)0x00020000u

MIBAD2 2 Port RAM

#define PBIST_RAMGROUP_19_N2HET2 (uint32)0x00040000u

N2HET2 2 Port RAM

#define PBIST_RAMGROUP_20_HETTU2 (uint32)0x00080000u

HETTU2 2 Port RAM

#define PBIST_RAMGROUP_21_ESRAM5 (uint32)0x00100000u

ESRAM5 Single Port RAM

#define PBIST_RAMGROUP_22_ESRAM6 (uint32)0x00200000u

ESRAM6 Single Port RAM

#define PBIST_RAMGROUP_23_ETHERNET1 (uint32)0x00400000u

Ethernet 2 Port RAM

#define PBIST_RAMGROUP_24_ETHERNET2 (uint32)0x00800000u

Ethernet 2 Port RAM

#define PBIST_RAMGROUP_25_ETHERNET3 (uint32)0x01000000u

Ethernet 1 Port RAM

#define PBIST_RAMGROUP_26_USB1 (uint32)0x02000000u

USB 2 Port RAM

#define PBIST_RAMGROUP_27_USB2 (uint32)0x04000000u

USB 1 Port RAM

#define PBIST_RAMGROUP_28_ESRAM8 (uint32)0x08000000u

ESRAM8 Single Port RAM

#define PBIST_RAMGROUP_29_RSVD (uint32)0x10000000u

— Reserved


SafeTI™ Diagnostic Library: Macros for PBIST Algorithms

Macros
Macros for PBIST Algorithms

Macros

#define | PBISTALGO_TRIPLE_READ_SLOW_READ (uint32)0x00000001u
#define | PBISTALGO_TRIPLE_READ_SLOW_READ (uint32)0x00000001u
#define | PBISTALGO_TRIPLE_READ_FAST_READ (uint32)0x00000002u
#define | PBISTALGO_TRIPLE_READ_FAST_READ (uint32)0x00000002u
#define | PBISTALGO_MARCH13N_RED_2PORT (uint32)0x00000004u
#define | PBISTALGO_MARCH13N_RED_1PORT (uint32)0x00000008u
#define | PBISTALGO_DOWN1A_RED_2PORT (uint32)0x00000010u
#define | PBISTALGO_DOWN1A_RED_1PORT (uint32)0x00000020u
#define | PBISTALGO_MAPCOLUMN_2PORT (uint32)0x00000040u
#define | PBISTALGO_MAPCOLUMN_1PORT (uint32)0x00000080u
#define | PBISTALGO_PRECHARGE_2PORT (uint32)0x00000100u
#define | PBISTALGO_PRECHARGE_2PORT (uint32)0x00020000u
#define | PBISTALGO_PRECHARGE_1PORT (uint32)0x00000200u
#define | PBISTALGO_PRECHARGE_1PORT (uint32)0x00010000u
#define | PBISTALGO_DTXN2_2PORT (uint32)0x00000400u
#define | PBISTALGO_DTXN2_2PORT (uint32)0x00200000u
#define | PBISTALGO_DTXN2_1PORT (uint32)0x00000800u
#define | PBISTALGO_DTXN2_1PORT (uint32)0x00100000u
#define | PBISTALGO_PMOS_OPEN_2PORT (uint32)0x00001000u
#define | PBISTALGO_PMOS_OPEN_1PORT (uint32)0x00002000u
#define | PBISTALGO_PMOS_OP_SLICE1_2PORT (uint32)0x00004000u
#define | PBISTALGO_PMOS_OP_SLICE1_2PORT (uint32)0x00800000u
#define | PBISTALGO_PMOS_OP_SLICE2_2PORT (uint32)0x00008000u
#define | PBISTALGO_PMOS_OP_SLICE2_2PORT (uint32)0x01000000u
#define | PBISTALGO_FLIP10_2PORT (uint32)0x00010000u
#define | PBISTALGO_FLIP10_2PORT (uint32)0x00080000u
#define | PBISTALGO_FLIP10_1PORT (uint32)0x00020000u
#define | PBISTALGO_FLIP10_1PORT (uint32)0x00040000u
#define | PBISTALGO_IDDQ_2PORT (uint32)0x00040000u
#define | PBISTALGO_IDDQ_1PORT (uint32)0x00080000u
#define | PBISTALGO_RETENTION_2PORT (uint32)0x00100000u
#define | PBISTALGO_RETENTION_1PORT (uint32)0x00200000u
#define | PBISTALGO_IDDQ2_2PORT (uint32)0x00400000u
#define | PBISTALGO_IDDQ2_1PORT (uint32)0x00800000u
#define | PBISTALGO_RETENTION2_2PORT (uint32)0x01000000u
#define | PBISTALGO_RETENTION2_1PORT (uint32)0x02000000u
#define | PBISTALGO_IDDQROWSTRIPE_2PORT (uint32)0x04000000u
#define | PBISTALGO_IDDQROWSTRIPE_1PORT (uint32)0x08000000u
#define | PBISTALGO_IDDQROWSTRIPE2_2PORT (uint32)0x10000000u
#define | PBISTALGO_IDDQROWSTRIPE2_1PORT (uint32)0x20000000u
#define | PBISTALGO_MARCH13N_2PORT (uint32)0x00000004u
#define | PBISTALGO_MARCH13N_1PORT (uint32)0x00000008u
#define | PBISTALGO_MAP_COLUMN_1PORT (uint32)0x00004000u
#define | PBISTALGO_MAP_COLUMN_2PORT (uint32)0x00008000u
#define | PBISTALGO_PMOS_OP_SLICE1_1PORT (uint32)0x00400000u

Detailed Description

Enumerations for selecting the PBIST algorith for SL_SelfTest_PBIST API Naming Convention: PBISTALGO_<Algo name>_<1/2>PORT

For details on Algorithms, Algorithm Mapping and supported types refer to device TRM

Macro Definition Documentation

#define PBISTALGO_DOWN1A_RED_1PORT (uint32)0x00000020u

Down1a Algor forces the switching fo all data bits & most addr bits on consecutive read cycles

#define PBISTALGO_DOWN1A_RED_2PORT (uint32)0x00000010u

Down1a Algor forces the switching fo all data bits & most addr bits on consecutive read cycles

#define PBISTALGO_DTXN2_1PORT (uint32)0x00000800u

Global column decode logic algo for 1 Port memories

#define PBISTALGO_DTXN2_1PORT (uint32)0x00100000u

Global column decode logic algo for 1 Port memories

#define PBISTALGO_DTXN2_2PORT (uint32)0x00000400u

Global column decode logic algo for 2 Port memories

#define PBISTALGO_DTXN2_2PORT (uint32)0x00200000u

Global column decode logic algo for 2 Port memories

#define PBISTALGO_FLIP10_1PORT (uint32)0x00020000u

flip10 algo for 1 port memories

#define PBISTALGO_FLIP10_1PORT (uint32)0x00040000u

flip10 algo for 1 port memories

#define PBISTALGO_FLIP10_2PORT (uint32)0x00010000u

flip10 algo for 2 port memories

#define PBISTALGO_FLIP10_2PORT (uint32)0x00080000u

flip10 algo for 2 port memories

#define PBISTALGO_IDDQ2_1PORT (uint32)0x00800000u

iddq2 algo for 1 port memories

#define PBISTALGO_IDDQ2_2PORT (uint32)0x00400000u

iddq2 algo for 2 port memories

#define PBISTALGO_IDDQ_1PORT (uint32)0x00080000u

iddq algo for 1 port memories

#define PBISTALGO_IDDQ_2PORT (uint32)0x00040000u

iddq algo for 2 port memories

#define PBISTALGO_IDDQROWSTRIPE2_1PORT (uint32)0x20000000u

iddqwstripe2 algo for 1 port memories

#define PBISTALGO_IDDQROWSTRIPE2_2PORT (uint32)0x10000000u

iddqwstripe2 algo for 2 port memories

#define PBISTALGO_IDDQROWSTRIPE_1PORT (uint32)0x08000000u

iddqwstripe algo for 1 port memories

#define PBISTALGO_IDDQROWSTRIPE_2PORT (uint32)0x04000000u

iddqwstripe algo for 2 port memories

#define PBISTALGO_MAP_COLUMN_1PORT (uint32)0x00004000u

Map Column algo (to identify bit line senstivities) for 1 Port memory

#define PBISTALGO_MAP_COLUMN_2PORT (uint32)0x00008000u

Map Column algo (to identify bit line senstivities) for 2 Port memory

#define PBISTALGO_MAPCOLUMN_1PORT (uint32)0x00000080u

Map Column algo (to identify bit line senstivities) for 1 Port memory

#define PBISTALGO_MAPCOLUMN_2PORT (uint32)0x00000040u

Map Column algo (to identify bit line senstivities) for 2 Port memory

#define PBISTALGO_MARCH13N_1PORT (uint32)0x00000008u

March13 N Algo for 1 Port mem — BASELINE TEST ALGO with HIGHEST OVERALL COVERAGE

#define PBISTALGO_MARCH13N_2PORT (uint32)0x00000004u

March13 N Algo for 2 Port mem — BASELINE TEST ALGO with HIGHEST OVERALL COVERAGE

#define PBISTALGO_MARCH13N_RED_1PORT (uint32)0x00000008u

March13 N Algo for 1 Port mem — BASELINE TEST ALGO with HIGHEST OVERALL COVERAGE

#define PBISTALGO_MARCH13N_RED_2PORT (uint32)0x00000004u

March13 N Algo for 2 Port mem — BASELINE TEST ALGO with HIGHEST OVERALL COVERAGE

#define PBISTALGO_PMOS_OP_SLICE1_1PORT (uint32)0x00400000u

pmos open slice1 for 1port memories

#define PBISTALGO_PMOS_OP_SLICE1_2PORT (uint32)0x00004000u

pmos open slice1 for 2port memories

#define PBISTALGO_PMOS_OP_SLICE1_2PORT (uint32)0x00800000u

pmos open slice1 for 2port memories

#define PBISTALGO_PMOS_OP_SLICE2_2PORT (uint32)0x00008000u

pmos open slice2 for 2port memories

#define PBISTALGO_PMOS_OP_SLICE2_2PORT (uint32)0x01000000u

pmos open slice2 for 2port memories

#define PBISTALGO_PMOS_OPEN_1PORT (uint32)0x00002000u

pmos oper algo for 1 port memories

#define PBISTALGO_PMOS_OPEN_2PORT (uint32)0x00001000u

pmos oper algo for 2 port memories

#define PBISTALGO_PRECHARGE_1PORT (uint32)0x00000200u

Pre-Charge algo to exercise pre-charge capability for 1 port memory

#define PBISTALGO_PRECHARGE_1PORT (uint32)0x00010000u

Pre-Charge algo to exercise pre-charge capability for 1 port memory

#define PBISTALGO_PRECHARGE_2PORT (uint32)0x00000100u

Pre-Charge algo to exercise pre-charge capability for 2 port memory

#define PBISTALGO_PRECHARGE_2PORT (uint32)0x00020000u

Pre-Charge algo to exercise pre-charge capability for 2 port memory

#define PBISTALGO_RETENTION2_1PORT (uint32)0x02000000u

retention2 algo for 1 port memories

#define PBISTALGO_RETENTION2_2PORT (uint32)0x01000000u

retention2 algo for 2 port memories

#define PBISTALGO_RETENTION_1PORT (uint32)0x00200000u

retention algo for 1 port memories

#define PBISTALGO_RETENTION_2PORT (uint32)0x00100000u

retention algo for 2 port memories

#define PBISTALGO_TRIPLE_READ_FAST_READ (uint32)0x00000002u

TRIPLE_READ_SLOW_READ for PBIST and STC ROM

#define PBISTALGO_TRIPLE_READ_FAST_READ (uint32)0x00000002u

TRIPLE_READ_SLOW_READ for PBIST and STC ROM

#define PBISTALGO_TRIPLE_READ_SLOW_READ (uint32)0x00000001u

TRIPLE_READ_SLOW_READ for PBIST and STC ROM

#define PBISTALGO_TRIPLE_READ_SLOW_READ (uint32)0x00000001u

TRIPLE_READ_SLOW_READ for PBIST and STC ROM


SafeTI™ Diagnostic Library: Data Structures

  • Data Structures
  • Data Structure Index
Data Structures
Here are the data structures with brief descriptions:
C _SL_Profile_Pbist_Struct | Structure for storing the profiling information of PBIST tests on various ramgroups fir different algorithms
C _SL_Profile_Struct | Structure for storing the profiling information of each testtype
C SL_adcData | ADC Conversion data structure
C SL_EFuse_FailInfo | EFuse Self-test failure information
C SL_PBIST_ExecStatus | Structure used to return the execution status of PBIST. This is used as a parmeter for the SL_SelfTest_PBIST_ExecStatus API
C SL_PSCON_FailInfo | PSCON failure information. Used in with SL_SelfTest_PSCON_FailInfo API
C SL_ResetReason_XInfo | Provides extended information of the previous reset (using shadow registers)
C SL_STC_Config | STC Configuration information to be used with SL_SelfTest_STC API
C SL_STC_FailInfo | STC failure information. Used in conjunction with SL_SelfTest_STC_Status API


SafeTI™ Diagnostic Library: SL_adcData Struct Reference

  • Data Structures
  • Data Structure Index
SL_adcData Struct Reference

ADC Conversion data structure. More...

#include <sl_priv.h>

Detailed Description

ADC Conversion data structure.

This type is used to pass adc conversion data.

The documentation for this struct was generated from the following file:
  • safety_library/source/sl_priv.h


SafeTI™ Diagnostic Library: SL_EFuse_FailInfo Struct Reference

  • Data Structures
  • Data Structure Index
SL_EFuse_FailInfo Struct Reference

EFuse Self-test failure information. More...

#include <sl_types.h>

Detailed Description

EFuse Self-test failure information.

The documentation for this struct was generated from the following file:
  • safety_library/include/sl_types.h


SafeTI™ Diagnostic Library: SL_PBIST_ExecStatus Struct Reference

  • Data Structures
  • Data Structure Index
SL_PBIST_ExecStatus Struct Reference

Structure used to return the execution status of PBIST. This is used as a parmeter for the SL_SelfTest_PBIST_ExecStatus API. More...

#include <sl_types.h>

Detailed Description

Structure used to return the execution status of PBIST. This is used as a parmeter for the SL_SelfTest_PBIST_ExecStatus API.

The documentation for this struct was generated from the following file:
  • safety_library/include/sl_types.h


SafeTI™ Diagnostic Library: SL_PSCON_FailInfo Struct Reference

  • Data Structures
  • Data Structure Index
SL_PSCON_FailInfo Struct Reference

PSCON failure information. Used in with SL_SelfTest_PSCON_FailInfo API. More...

#include <sl_types.h>

Detailed Description

PSCON failure information. Used in with SL_SelfTest_PSCON_FailInfo API.

The documentation for this struct was generated from the following file:
  • safety_library/include/sl_types.h


SafeTI™ Diagnostic Library: SL_ResetReason_XInfo Struct Reference

  • Data Structures
  • Data Structure Index
SL_ResetReason_XInfo Struct Reference

Provides extended information of the previous reset (using shadow registers) More...

#include <sl_types.h>

Detailed Description

Provides extended information of the previous reset (using shadow registers)

The documentation for this struct was generated from the following file:
  • safety_library/include/sl_types.h


SafeTI™ Diagnostic Library: SL_STC_Config Struct Reference

  • Data Structures
  • Data Structure Index
SL_STC_Config Struct Reference

STC Configuration information to be used with SL_SelfTest_STC API. More...

#include <sl_types.h>

Detailed Description

STC Configuration information to be used with SL_SelfTest_STC API.

The documentation for this struct was generated from the following file:
  • safety_library/include/sl_types.h


SafeTI™ Diagnostic Library: SL_STC_FailInfo Struct Reference

  • Data Structures
  • Data Structure Index
SL_STC_FailInfo Struct Reference

STC failure information. Used in conjunction with SL_SelfTest_STC_Status API. More...

#include <sl_types.h>

Detailed Description

STC failure information. Used in conjunction with SL_SelfTest_STC_Status API.

The documentation for this struct was generated from the following file:
  • safety_library/include/sl_types.h


SafeTI™ Diagnostic Library: Data Structure Index

  • Data Structures
  • Data Structure Index
Data Structure Index
S | _
S
SL_EFuse_FailInfo SL_ResetReason_XInfo
_
_SL_Profile_Struct
SL_PBIST_ExecStatus SL_STC_Config
SL_adcData SL_PSCON_FailInfo SL_STC_FailInfo _SL_Profile_Pbist_Struct
S | _


SafeTI™ Diagnostic Library: File List

  • File List
  • Globals
File List
Here is a list of all documented files with brief descriptions:
[detail level 123]
▼ safety_library |
▼ include |
sl_api.h | Main API files for Hercules SafeTI™ Hercules™ Diagnostic Library
sl_config.h | SafeTI™ Hercules™ Diagnostic Library configuration items
sl_log.h | API's for logging(errors,results) and profiling of functions
sl_types.h | File contains the types used by the SafeTI™ Hercules™ Diagnostic Library APIs
▼ source |
sl_esm.c | File contains esm handling and interrupt handlers for esm errors
sl_priv.h | Private header file for SafeTI™ Hercules™ Diagnostic Library
sl_selftest.c | File contains the Self Test APIs
sl_sys_pmu.h |


SafeTI™ Diagnostic Library: safety_library Directory Reference

  • safety_library
safety_library Directory Reference

Directories

directory | include
directory | source


SafeTI™ Diagnostic Library: safety_library/include Directory Reference

  • safety_library
  • include
include Directory Reference

Files

file | sl_api.h [code]
Main API files for Hercules SafeTI™ Hercules™ Diagnostic Library.
file | sl_config.h [code]
SafeTI™ Hercules™ Diagnostic Library configuration items.
file | sl_log.h [code]
API's for logging(errors,results) and profiling of functions.
file | sl_types.h [code]
File contains the types used by the SafeTI™ Hercules™ Diagnostic Library APIs.


SafeTI™ Diagnostic Library: safety_library/include/sl_api.h File Reference

  • File List
  • Globals
  • safety_library
  • include
sl_api.h File Reference

Main API files for Hercules SafeTI™ Hercules™ Diagnostic Library. More...

Detailed Description

Main API files for Hercules SafeTI™ Hercules™ Diagnostic Library.

Version
2.2.0

The function prototypes of the of the API's which are exposed by the
SafeTI™ Hercules™ Diagnostic Library are declared here.The file also includes the depandancies
of the SafeTI™ Hercules™ Diagnostic Library API's This single file can be included by
application which needs to make use of the SafeTI™ Hercules™ Diagnostic Library in their
application.

Function Documentation

uint32 _SL_Get_DataFault_Status ( void )

NOTE: Below functions are for future enhancements. Do not use these APIs until it's officially supported

boolean SL_adcCalibration | ( | sl_adcBASE_t * | adc,
 |  | uint32 * | offset_error
 | ) |  |

Computes offset error using Calibration mode Below is the flowchart for the SL_adcCalibration.

Parameters
[in] adc Pointer to ADC module:
  • sl_adcREG1: ADC1 module pointer
  • sl_adcREG2: ADC2 module pointer offset Pointer to uint32
Returns
TRUE if success FALSE if failure offset variable is updated with the computed offset error

Example Usage:

//Disable Interrupts
adc->GxINTENA[sl_adcGROUP1] = 0u;
//disable any self tst and Calib mode first
adc->CALCR = 0u;
//Enable 12-BIT ADC
(adc->OPMODECR) |= ADC_12BIT_RESOLUTION;
//Disable all channels for conversion
//Event select
adc->GxSEL[sl_adcGROUP1] = 0u;
//Calibrate the ADC so as to fill appropriate value in CALR register
SL_adcCalibration(adc, offset);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
  • Backup Mode before Calibration
  • Enable 12-BIT ADC
  • Restore Mode after Calibration
Note
The function adcInit has to be called before using this function.
void SL_Clear_nERROR ( void )

Function clears the nERROR (de-activates) signal.

Note: Application must use the SL_ESM_nERROR_Active to wait for the signal to go in-active.
Note: The nERROR pin can remain active even after the function call and the duration for which it can be
active depends on the LTCRP register Low-Time Counter Preload register (LTCRP).

Parameters
[in] | None
[out] | None
Returns
TRUE if function executed successfully else FALSE.
Entry Mode:
Any privilege mode
Exit Mode:
Same as at entry
See also:
SL_ESM_nERROR_Active
uint64 SL_CRC_Calculate | ( | uint64 * | startAddr,
 |  | uint32 | count64
 | ) |  |

This function calculates the CRC of specified memory (& length) using the hardware CRC implementing the ISO CRC-64 standard polynomial.

Description:
This API can be used to test the integrity of memory contents by calculating a CRC for
the memory and comparing this value to a previously generated golden CRC.
Parameters
[in] | startAddr | - Starting address of the memory (aligned to 64bit address boundary).
[in] | count64 | - Length of the memory (for calculating CRC) in multiple of 64bits.
Returns
Calculated CRC value

Example Usage:

//Calculate the CRC for VIM RAM
vimCRC = SL_CRC_Calculate(((uint64 *)0xFFF82000), 256);
Entry Mode:
Any Privilege Mode
Exit Mode:
Same as entry
void SL_ESM_Init ( ESM_Application_Callback appCallback )

Initializes the ESM module handing in the SafeTI™ Hercules™ Diagnostic Library.

Description:
Once initialized all ESM notifications are decoded & 'appCallback' is called with the
parameters indicating the ESM failure information. For details on the failure information,
provided by this API, refer to documentation on ESM_Application_Callback.
Parameters
[in] | appCallback | - Application callback to be called for ESM notifications.
[out] | None
Returns
None

Example Usage:

void ESM_Callback(uint32 channel, uint32 param1, uint32 param2, uint32 param3);
void ESM_Callback(uint32 channel, uint32 param1, uint32 param2, uint32 param3)
{
Code for handling the ESM errors
}
SL_ESM_Init(ESM_Callback);
Entry Mode:
Any Privilege Mode
Exit Mode:
Same as at entry
See also:
ESM_Application_Callback
boolean SL_ESM_nERROR_Active ( void )

Function returns the status of the nERRORpin.

Parameters
[in] | None
[out] | None
Returns
TRUE if nERROR pin is active (low) else FALSE.
Entry Mode:
Any privilege mode
Exit Mode:
Same as at entry
boolean SL_Init_ECCFlash | ( | uint16 | secThreshold,
 |  | uint16 | ctrlFlags
 | ) |  |

Enables detection of Flash ECC errors on Cortex-R4F.

Implementation:
The on-chip Flash memory (ATCM) supports SECDED diagnositcs. This function enables this
mechanism by exporting error detection events from the CPU to the Flash wrapper and then
from the Flash wrapper to the ESM. This functionality is not enabled by default and must
be configured by the software. The R4F PMU is first set to export events to external monitor
and then the Flash wrapper is confiugred to export the correctable and uncorrectable events
to the ESM.
Parameters
[in] secThreshold - Single Error Correction Threshold(updates the fields for EE_CTRL2/FEDACCTRL2 register in flash module)
[in] ctrlFlags - Error Detection and Correction flags (updates the fields for EE_CTRL1/FEDACCTRL1 register in flash module)
Note : please refer the section for F021 Flash Module Controller of the TRM for more information
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

boolean retVal;
retVal = SL_Init_ECCFlash(10, FLASHECC_DEFAULT);
Entry Mode:
Any Privilege Mode
Exit Mode:
No change
See also:
SL_Init_ECCTCMRAM, Macros for F021Flash ECC Configuration
boolean SL_Init_ECCTCMRAM | ( | uint16 | threshold,
 |  | boolean | enableErrIntGen
 | ) |  |

Enables/Disables detection of ECC errors on TCM SRAM on Cortex-R4F.

Description:
The on-chip TCM SRAM is supported by SECDED ECC diagnostics. In this SECDED scheme, an 8-bit
code word is used to store the ECC data as calculated over the 64-bit data bus. This function
eports error detection events from the CPU to the SRAM wrapper, and then from the SRAM wrapper
to the ESM.
Parameters
[in] | threshold | - Number of single-bit error corrections by the SECDED logic inside the Cortex-R4F CPU before generating a single-bit error interrupt.
[in] | enableErrIntGen | - When TRUE enables the generation of the single-bit error interrupt when the count reaches the programmed threshold. If the interrupt is not enabled, the single-bit error counter continues to count by resetting back to zero without generating any error interrupt.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

boolean retVal;
//Set the threshold to 1 & generarte ESM interrupt on each error
retVal = SL_Init_ECCTCMRAM(10, TRUE);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_Init_ECCFlash

First configure and then enable the ECC Checks

boolean SL_Init_Memory ( SL_AutoInitRamId ramSet )

Hardware intialization of memories.

Description:
This function auto-initializes memories using the hardware initialization on Hercules devices.
Hercules devices support auto-initialization on most memories on the system bus and on the
peripheral bus. The memory used for the FlexRay message objects is not directly CPU addressable,
hence there is no memory auto-initialization support for this memory.

The system module on the Hercules microcontroller allows all on-chip SRAMs to be initialized in hardware.
This is especially essential since all the on-chip memories support some form of error detection. The CPU
data RAM supports ECC while the peripheral memories support parity error detection. The auto initialization
mechanism also initializes the ECC or parity memories, as required.
For possible values of the ramSet please refer to _SL_AutoInitRamId.
Parameters
[in] | ramSet | Specifies the memories to be auto-initialized.
[out] | None
Returns
TRUE if function executed successfully else FALSE

Example Usage:

boolean retVal;
retVal = SL_Init_Memory((RAMTYPE_RAM | RAMTYPE_VIM));
Entry Mode:
Any Privilege Mode
Exit Mode:
Same as at entry
See also:
_SL_AutoInitRamId
Refer to the document "Initialization of Hercules� ARM Cortex -R4F Microcontrollers"
for more information(refer to section 2.27)

Note:The ECC or parity should be enabled on the RAMs before hardware auto-initialization starts if parity or ECC is being used.

void SL_Init_R4Registers ( void )

Initializes Cortex-R4F CPU's internal registers.

Description:
Hercules series of MCU include dual Cortex-R4F CPUs in lock-step. At power up registers are not
guaranteed to be in same state for both the CPUs. The CPU pushes the internal registers on to the stack on
a function call, which could lead to the detection of a core compare error. Therefore, the CPU internal
core registers need to be initialized to a predefined state before any function call is made. This function
is recommended to be executed right after a reset.
Parameters
[in] | None
[out] | None
Returns
None

Example Usage:

SL_Init_R4Registers();
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_Init_StackPointers

Note: This function does not initialize Stack Pointers.SL_Init_StackPointers must be called to initialize the stack pointers.

void SL_Init_R5Registers ( void )

Initializes Cortex-R5F CPU's internal registers.

Description:
Hercules series of MCU include dual Cortex-R5F CPUs in lock-step. At power up registers are not
guaranteed to be in same state for both the CPUs. The CPU pushes the internal registers on to the stack on
a function call, which could lead to the detection of a core compare error. Therefore, the CPU internal
core registers need to be initialized to a predefined state before any function call is made. This function
is recommended to be executed right after a reset.
Parameters
[in] | None
[out] | None
Returns
None

Example Usage:

SL_Init_R5Registers();
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_Init_StackPointers

**Note: This function does not initialize Stack Pointers. SL_Init_StackPointers must be called to initialize the stack pointers.**

SL_ResetReason SL_Init_ResetReason ( void )

Provides source of last reset.

Description:
The Hercules microcontroller can be reset by either of the conditions described below. This function returns
reset condition indicated in the System Exception Status Register (SYSESR).
  • Driving nPORRST pin low : Cold reset, or power-on reset. This reset signal is typically driven by an
    external voltage externally supervisor.
  • Voltage Monitor reset : The microcontroller has an embedded voltage monitor that generates a power-on
    reset when the core voltage gets out of a valid range, or when the I/O voltage
    falls below a threshold.
  • Warm reset : This reset input is typically used in a system with multiple ICs and which
    requires that the microcontroller also gets reset whenever the other IC detects
    a fault condition.
  • Oscillator failure : This reset is generated by the system module when the clock monitor detects an
    oscillator fail condition.
  • Software reset : This reset is generated by the application software
  • CPU reset : This reset is generated by the CPU self-test controller (LBIST) or by changing
    the memory protection (MMU/MPU) configuration in the CPURSTCR register.
  • Debug reset : The ICEPICK logic implemented on the microcontroller allows a system reset to
    be generated via the debug logic.
  • Watchdog reset : This reset is generated by the digital windowed watchdog (DWWD) module on the
    microcontroller. The DWWD can generate a reset whenever the watchdog service
    window is violated.
Parameters
[in] | None
[out] | None
Returns
SL_ResetReason - Reset reason

Example Usage:

SL_ResetReason rstReason;
rstReason = SL_Init_ResetReason();
Entry Mode:
Can be called in any operating mode of CPU
Exit Mode:
No change in the operating mode
See also:
Type:_SL_ResetReason
boolean SL_Init_ResetReason_XInfo ( SL_ResetReason_XInfo * rrXInfo )

Function is used to return extended information on the reset reason.

Note: Refer to section on Reset Behavior in the TRM.

Parameters
[in] | rrXInfo | - structure which holds the additional information on the reset reason.
[out] | None
Returns
None
Entry Mode:
Can be called in any operating mode of CPU.
Exit Mode:
No change in the operating mode.

Note: This function clears the ESM Group2 Shadow register (ESMSSR2).

See also:
_SL_ResetReason_XInfo
void SL_Init_StackPointers ( void )

Initializes CPU's stack pointer for SVC, FIQ, IRQ, ABT, UND & SYS modes.

Description:
This function initializes the stack pointers for the privilege modes of the CPU. Following
variables are used as stack pointers and hence must be defined by the application. StackModeSVC,
StackModeFIQ, StackModeIRQ, StackModeABT, StackModeUND, StackModeSYS. Function uses the
macros Stack Size for various ARM modes from sl_config.h file.
Parameters
[in] | None
[out] | None
Returns
None

Example Usage:

SL_Init_StackPointers();
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_Init_R4Registers

**Note: Application can define the macro EXTERNAL_SP_INIT to disable the use of this API and use its own implementation to initialize the stack pointers. This provision is provided because the diagnostic library expects the application to define global variables pointing to the Stack pointer locations, and if not using this API, need to be removed.

boolean SL_SelfTest_ADC | ( | SL_SelfTestType | testType,
 |  | boolean | mode,
 |  | SL_ADC_Config * | config,
 |  | SL_ADC_Pinstatus * | pinstatus
 | ) |  |

It does the selftest on the required adc pin and provides the information on status of the Pin.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Below is the flowchart for the ADC self test

Parameters
[in] | testType | - None there are no Different types of test types for the ADC self test.
[in] | mode | - None Only Synchronous mode is supported.
[in] | config | - Pointer to structure that contains ADC base address and the Channel number.
[out] | pinstatus | - pointer to SL_ADC_Pinstatus it is output parameter and stores the state of the adc pin tested.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

//use the channel 7 and adc1
adcConfig.adc_channel = 7;
adcConfig.adcbase = sl_adcREG1;
//pin is not connected to any analog input
if( TRUE == SL_SefTest_ADC(0, 0, &adcConfig, &adc_pinstatus)) {
if (ADC_PIN_GOOD == adc_pinstatus) {
//testcase pass
} else {
//testcase fail
}
} else {
//testcase fail
}
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
_SL_ADC_Config, _SL_ADC_Pinstatus
  • Backup Mode before Calibration
  • Enable 12-BIT ADC
  • Restore Mode after Calibration
boolean SL_SelfTest_CAN | ( | SL_SelfTestType | testType,
 |  | SL_DCAN_Instance | instance
 | ) |  |

Perform a test of the SECDED ECC in CAN
.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] | testType | Indicates the type of fault injection to perform.
[in] | instance | Indicates the CAN port instance to be tested.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

SL_SelfTest_CAN(CAN_ECC_TEST_MODE_1BIT, SL_DCAN1);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
boolean SL_SelfTest_CCMR4F | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_CCMR4F_FailInfo * | config
 | ) |  |

Executes self-tests on Core Compare Module (CCM).

Description:
The Hercules product family includes a lockstep processor diagnostic. This feature includes the
addition of a diagnostic Cortex-R4F CPU that is combined into a 1oo1D (single channel with diagnostic
channel) configuration with the application CPU. The core compare module (CCM) compares the CPU
outputs and flags all mis-compares to the ESM.
The CCM logic provides self test and error forcing capability via software triggered hardware.
The self test ensures that the CCM compare logic is working properly. The error forcing capability
allows you to test the system level response to a lockstep miscompare.

Please refer to _SL_SelfTest_Type for the values to be used for testType

Parameters
[in] | testType | - Indicates the type of self test to run. For details refer to SL_SelTestType. documentation
[in] | bMode | - TRUE for synchronous mode & FALSE for async mode Parameter is valid only for CCMR4F_SELF_TEST selftest type.
[in] | config | - Structure used for returning the test results. For details refer to SL_CCMR4F_FailInfo documentation.**Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.**
Returns
TRUE if the test was executed else FALSE

Example Usage:

SL_CCMR4F_FailInfo failInfoCCMR4F;
retVal = SL_SelfTest_CCMR4F(CCMR4F_SELF_TEST, TRUE, &failInfoCCMR4F);
if (failInfoCCMR4F.stResult == ST_FAIL) {
// Self test failed.. for details of failure info read failInfoCCMR4F.failInfo
}
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_SelfTest_Status_CCMR4F
Profiling Information of Tests:
TestType | Profiling Time in us
CCMR4F_SELF_TEST | 10.405
CCMR4F_ERROR_FORCING_TEST | 7.556
CCMR4F_SELF_TEST_ERROR_FORCING | 5.04
boolean SL_SelfTest_CCMR5F | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_CCMR5F_FailInfo * | config
 | ) |  |

Executes self-tests on Core Compare Module (CCM).

Description:
The Hercules product family includes a lockstep processor diagnostic. This feature includes the
addition of a diagnostic Cortex-R5F CPU that is combined into a 1oo1D (single channel with diagnostic
channel) configuration with the application CPU. The core compare module (CCM) compares the CPU
outputs and flags all mis-compares to the ESM.
The CCM logic provides self test and error forcing capability via software triggered hardware.
The self test ensures that the CCM compare logic is working properly. The error forcing capability
allows you to test the system level response to a lockstep miscompare.

Please refer to _SL_SelfTest_Type for the values to be used for testType

Parameters
[in] | testType | - Indicates the type of self test to run. For details refer to SL_SelTestType. documentation
[in] | bMode | - TRUE for synchronous mode & FALSE for async mode Parameter is valid only for CCMR5F_SELF_TEST selftest type.
[in] | config | - Structure used for returning the test results. For details refer to SL_CCMR5F_FailInfo documentation.**Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.**
Returns
TRUE if the test was executed else FALSE

Example Usage:

SL_CCMR5F_FailInfo failInfoCCMR5F;
retVal = SL_SelfTest_CCMR5F(CCMR5F_SELF_TEST, TRUE, &failInfoCCMR5F);
if (failInfoCCMR5F.stResult == ST_FAIL) {
// Self test failed.. for details of failure info read failInfoCCMR5F.failInfo
}
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_SelfTest_Status_CCMR5F
Profiling Information of Tests:
TestType | Profiling Time in us
CCMR4F_SELF_TEST | 10.405
CCMR4F_ERROR_FORCING_TEST | 7.556
CCMR4F_SELF_TEST_ERROR_FORCING | 5.04
boolean SL_SelfTest_DMA ( SL_SelfTestType testType )

Perform a test of the SECDED ECC in DMA
.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] testType Indicates the type of fault injection to perform.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

SL_SelfTest_DMA(DMA_ECC_TEST_MODE_1BIT);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
boolean SL_SelfTest_EFuse | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_EFuse_Config * | config
 | ) |  |

This function executes self tests on the eFuse structures.

Description:
The Hercules platform devices support a manufacturing time configuration of certain functionality via a
one time programmable EFuse structures. The EFuses are read automatically after POR by an autoload function.
This function executes the diagnostic tests on detect incorrect configuration values.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] | testType | - Must be one of EFUSE_SELF_TEST_ECC or EFUSE_SELF_TEST_STUCK_AT_ZERO
[in] | bMode | - When TRUE function will wait for the test to complete (synchronous). Function will be async when FALSE & the use can must use SL_SelfTest_Status_EFuse to retrieve the result.
[in] | config | - Configuration parameters for the self tests. Refer to SL_EFuse_Config structure documentation for details of each configuration parameter.
Returns
TRUE if the tests were executed else FALSE. (Does not indicate the test result).

Example Usage:

// Run EFuse self tests
stConfigEFuse.numPatterns = 600u;
stConfigEFuse.seedSignature = 0x5362F97Fu;
stConfigEFuse.failInfo.stResult= ST_FAIL;
stConfigEFuse.failInfo.failInfo= EFUSE_ERROR_NONE;
retVal = SL_SelfTest_EFuse(EFUSE_SELF_TEST_STUCK_AT_ZERO, TRUE, &stConfigEFuse);
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_SelfTest_Status_EFuse
Profiling Information of Tests:
TestType | Profiling Time in us
EFUSE_SELF_TEST_ECC | 6.438
EFUSE_SELF_TEST_STUCK_AT_ZERO | 5.402
boolean SL_SelfTest_FEE | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_SelfTest_Result * | fee_stResult
 | ) |  |

Executes diagnostic tests on F021 Flash.

Description:
F021 Flash wrapper provides to verify various logic. The flash wrapper provides multiple diagnostic modes.
This function executes the selected diagnostic mode.

Please refer to _SL_SelfTest_Type for the values to be used for testType.
Note : Refer to Safety Manual for TMS570LS31x/21x and RM48x Hercules ARM Safety Critical Microcontrollers (section on Primary Embedded Flash and RM48x/TMS570LS31x 16/32-Bit RISC Flash Microcontroller TRM (section F021 Flash Module Controller)

Parameters
[in] | testType | - Specifies the test type to execute
[in] | bMode | - NOT USED
[in] fee_stResult - Pointer to structure that is used to return the test status & results
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection modes.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

boolean retVal;
//Execute 1Bit test
SL_SelfTest_Result flash_stResult;
retVal = SL_SelfTest_FEE(FLASH_ECC_SYN_REPORT_MODE, TRUE, &flash_stResult);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
Type:_SL_SelfTest_Type
boolean SL_SelfTest_Flash | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_SelfTest_Result * | flash_stResult
 | ) |  |

Executes diagnostic tests on F021 Flash.

Description:
F021 Flash wrapper provides to verify various logic. The flash wrapper provides multiple diagnostic modes.
Thisfunction executes the selected diagnostic mode.

Please refer to _SL_SelfTest_Type for the values to be used for testType

Note : Refer to Safety Manual for TMS570LS31x/21x and RM48x Hercules ARM Safety Critical Microcontrollers (section on Primary Embedded Flash and RM48x/TMS570LS31x 16/32-Bit RISC Flash Microcontroller TRM (section F021 Flash Module Controller)
Note: For FLASH_ECC_TEST_MODE_2BIT_FAULT_INJECT the fault is injected in the subsequent read of the corrupted flash area by the application. The application must take care to restore the flash diagnostic control registers . Note: FLASH_HARD_ERROR_LIVELOCK is not supported in this release.

Parameters
[in] | testType | - Specifies the test type to execute
[in] | bMode | - NOT USED
[in] flash_stResult - Pointer to structure that is used to return the test status & results
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.
Returns
TRUE if function executed successfully else FALSE

Example Usage:

boolean retVal;
//Execute 1Bit test
SL_SelfTest_Result flash_stResult;
retVal = SL_SelfTest_Flash(FLASHECC_ECC_TEST_MODE_1BIT, TRUE, &flash_stResult);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
Type:_SL_SelfTest_Type
Profiling Information of Tests:
TestType | Profiling Time in us
FLASH_ECC_ADDR_TAG_REG_MODE | 8.437
FLASH_ECC_TEST_MODE_1BIT | 7.3605
FLASH_ECC_TEST_MODE_2BIT | 13.3885
boolean SL_SelfTest_MibSPI | ( | SL_SelfTestType | testType,
 |  | SL_MIBSPI_Instance | instance
 | ) |  |

Perform a test of the SECDED ECC in MibSPI
.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] | testType | Indicates the type of fault injection to perform.
[in] | instance | Indicates the MibSPI port instance to be tested.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI1);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
boolean SL_SelfTest_PBIST | ( | register SL_SelfTestType | testType,
 |  | register uint32 | ramGroup,
 |  | register uint32 | algoInfo
 | ) |  |

Executes PBIST tests on RAM groups with different algorithms.

Description:
Hercules microcontrollers support run-time-programmable memory BIST engine for varying levels of
coverage across many embedded memory instance. This function executes the selected PBIST Algorithms
on the selected RAM Groups.This API just initiates the PBIST for the provide ramgroups and algorithms
The API SL_SelfTest_Status_PBIST should be used to get the status of the PBIST execution which
which has completed.

Please refer to

  • _SL_SelfTest_Type for the values to be used for testType.
  • Macros for PBIST Algorithms for the PBIST Algorithm types(possible values for algoInfo).
  • Macros for PBIST RAM groups for the PBIST Algorithm types(possible values for ramGroup).
Parameters
[in] | testType | - Specifies the test type to execute.
[in] | ramGroup | - List of RAM Groups to be used for testing. ** NOTE: This parameter is of type uint64 for RM57Lx and TMS570LC43x devices **
[in] | algoInfo | - List of algorithms to be used for testing.

Note: Refer to Device TRM for supported combinations of RAM Group & Algorithms.
Note: The PBIST on RAM memories is destructive and corrupts the memories.
Note: PBIST Algorithm should not be used on SRAM when code/data resides in SRAM.The application.
needs to appropriately branch to non volatile location without the use of the data variables during this test.

Returns
TRUE if function executed successfully else FALSE

Example Usage:

boolean retVal;
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
(PBIST_RAMGROUP_07_MIBSPI1 |
PBIST_RAMGROUP_08_MIBSPI3 |
PBIST_RAMGROUP_09_MIBSPI5 |
PBIST_RAMGROUP_10_VIM |
PBIST_RAMGROUP_11_MIBADC1 |
PBIST_RAMGROUP_18_MIBADC2),
PBISTALGO_MARCH13N_RED_2PORT);
while (TRUE != SL_SelfTest_PBIST_ExecStatus(&pbistStatus));
retVal = SL_SelfTest_PBIST_StopExec();
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
_SL_SelfTest_Type, Macros for PBIST RAM groups,Macros for PBIST Algorithms,SL_SelfTest_Status_PBIST & SL_SelfTest_PBIST_StopExec
Profiling Information of Tests:
RAMGROUP | ALGORITHM | Profiling Time in us
PBIST_RAMGROUP_01_PBIST_ROM | PBISTALGO_TRIPLE_READ_SLOW_READ | 261.2105
PBIST_RAMGROUP_01_PBIST_ROM | PBISTALGO_TRIPLE_READ_FAST_READ | 97.295
PBIST_RAMGROUP_02_STC_ROM | PBISTALGO_TRIPLE_READ_SLOW_READ | 211.308
PBIST_RAMGROUP_02_STC_ROM | PBISTALGO_TRIPLE_READ_FAST_READ | 80.765
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_MARCH13N_RED_2PORT | 332.0085
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_DOWN1A_RED_2PORT | 85.404
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_MAPCOLUMN_2PORT | 110.2615
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_PRECHARGE_2PORT | 78.144
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_DTXN2_2PORT | 115.3145
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_PMOS_OPEN_2PORT | 268.895
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 269.143
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_FLIP10_2PORT | 78.932
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_IDDQ_2PORT | 28.445
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_RETENTION_2PORT | 28.655
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_IDDQ2_2PORT | 28.415
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_RETENTION2_2PORT | 28.655
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_IDDQROWSTRIPE_2PORT | 28.895
PBIST_RAMGROUP_03_DCAN1 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 28.895
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_MARCH13N_RED_2PORT | 331.7705
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_DOWN1A_RED_2PORT | 85.535
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_MAPCOLUMN_2PORT | 102.253
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_PRECHARGE_2PORT | 78.125
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_DTXN2_2PORT | 115.295
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_PMOS_OPEN_2PORT | 268.895
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 269.07
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_FLIP10_2PORT | 70.925
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_IDDQ_2PORT | 28.415
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_RETENTION_2PORT | 28.655
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_IDDQ2_2PORT | 28.415
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_RETENTION2_2PORT | 28.655
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_IDDQROWSTRIPE_2PORT | 28.895
PBIST_RAMGROUP_04_DCAN2 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 28.895
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_MARCH13N_RED_2PORT | 331.7745
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_DOWN1A_RED_2PORT | 85.418
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_MAPCOLUMN_2PORT | 102.365
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_PRECHARGE_2PORT | 78.095
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_DTXN2_2PORT | 115.295
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_PMOS_OPEN_2PORT | 268.895
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 269.018
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_FLIP10_2PORT | 70.925
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_IDDQ_2PORT | 28.415
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_RETENTION_2PORT | 28.655
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_IDDQ2_2PORT | 28.415
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_RETENTION2_2PORT | 28.655
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_IDDQROWSTRIPE_2PORT | 28.895
PBIST_RAMGROUP_05_DCAN3 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 28.895
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_MARCH13N_RED_2PORT | 395.552
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_DOWN1A_RED_2PORT | 93.005
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_MAPCOLUMN_2PORT | 115.775
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_PRECHARGE_2PORT | 83.615
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_DTXN2_2PORT | 174.335
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_PMOS_OPEN_2PORT | 379.178
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 379.325
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_FLIP10_2PORT | 82.415
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_IDDQ_2PORT | 26.015
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_RETENTION_2PORT | 13.945
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_IDDQ2_2PORT | 26.015
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_RETENTION2_2PORT | 14.185
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_IDDQROWSTRIPE_2PORT | 27.305
PBIST_RAMGROUP_07_MIBSPI1 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 26.554
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_MARCH13N_RED_2PORT | 395.408
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_DOWN1A_RED_2PORT | 92.975
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_MAPCOLUMN_2PORT | 115.775
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_PRECHARGE_2PORT | 83.615
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_DTXN2_2PORT | 174.464
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_PMOS_OPEN_2PORT | 379.325
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 379.382
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_FLIP10_2PORT | 82.445
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_IDDQ_2PORT | 26.015
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_RETENTION_2PORT | 13.945
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_IDDQ2_2PORT | 26.015
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_RETENTION2_2PORT | 14.185
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_IDDQROWSTRIPE_2PORT | 26.495
PBIST_RAMGROUP_08_MIBSPI3 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 26.495
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_MARCH13N_RED_2PORT | 395.506
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_DOWN1A_RED_2PORT | 93.005
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_MAPCOLUMN_2PORT | 115.775
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_PRECHARGE_2PORT | 83.615
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_DTXN2_2PORT | 174.335
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_PMOS_OPEN_2PORT | 379.195
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 379.325
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_FLIP10_2PORT | 82.415
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_IDDQ_2PORT | 26.015
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_RETENTION_2PORT | 14.185
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_IDDQ2_2PORT | 26.015
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_RETENTION2_2PORT | 14.185
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_IDDQROWSTRIPE_2PORT | 27.302
PBIST_RAMGROUP_09_MIBSPI5 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 26.6135
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_MARCH13N_RED_2PORT | 75.248
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_DOWN1A_RED_2PORT | 27.695
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_MAPCOLUMN_2PORT | 30.815
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_PRECHARGE_2PORT | 26.495
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_DTXN2_2PORT | 37.775
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_PMOS_OPEN_2PORT | 58.175
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 58.175
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_FLIP10_2PORT | 23.135
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_IDDQ_2PORT | 15.935
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_RETENTION_2PORT | 16.175
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_IDDQ2_2PORT | 15.935
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_RETENTION2_2PORT | 16.175
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_IDDQROWSTRIPE_2PORT | 16.175
PBIST_RAMGROUP_11_MIBADC1 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 16.175
PBIST_RAMGROUP_12_DMA | PBISTALGO_MARCH13N_RED_2PORT | 163.955
PBIST_RAMGROUP_12_DMA | PBISTALGO_DOWN1A_RED_2PORT | 52.022
PBIST_RAMGROUP_12_DMA | PBISTALGO_MAPCOLUMN_2PORT | 58.382
PBIST_RAMGROUP_12_DMA | PBISTALGO_PRECHARGE_2PORT | 49.235
PBIST_RAMGROUP_12_DMA | PBISTALGO_DTXN2_2PORT | 62.915
PBIST_RAMGROUP_12_DMA | PBISTALGO_PMOS_OPEN_2PORT | 15.895
PBIST_RAMGROUP_12_DMA | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 84.275
PBIST_RAMGROUP_12_DMA | PBISTALGO_FLIP10_2PORT | 39.875
PBIST_RAMGROUP_12_DMA | PBISTALGO_IDDQ_2PORT | 23.795
PBIST_RAMGROUP_12_DMA | PBISTALGO_RETENTION_2PORT | 24.035
PBIST_RAMGROUP_12_DMA | PBISTALGO_IDDQ2_2PORT | 23.795
PBIST_RAMGROUP_12_DMA | PBISTALGO_RETENTION2_2PORT | 24.035
PBIST_RAMGROUP_12_DMA | PBISTALGO_IDDQROWSTRIPE_2PORT | 24.035
PBIST_RAMGROUP_12_DMA | PBISTALGO_IDDQROWSTRIPE2_2PORT | 24.035
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_MARCH13N_RED_2PORT | 452.376
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_DOWN1A_RED_2PORT | 120.365
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_MAPCOLUMN_2PORT | 142.415
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_PRECHARGE_2PORT | 111.215
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_DTXN2_2PORT | 157.066
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_PMOS_OPEN_2PORT | 19.255
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 260.975
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_FLIP10_2PORT | 93.695
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_IDDQ_2PORT | 40.415
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_RETENTION_2PORT | 40.895
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_IDDQ2_2PORT | 40.415
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_RETENTION2_2PORT | 40.895
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_IDDQROWSTRIPE_2PORT | 41.375
PBIST_RAMGROUP_13_N2HET1 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 41.365
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_MARCH13N_RED_2PORT | 144.6005
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_DOWN1A_RED_2PORT | 50.975
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_MAPCOLUMN_2PORT | 56.255
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_PRECHARGE_2PORT | 49.295
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_DTXN2_2PORT | 57.695
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_PMOS_OPEN_2PORT | 80.735
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 80.975
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_FLIP10_2PORT | 36.335
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_IDDQ_2PORT | 25.535
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_RETENTION_2PORT | 25.775
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_IDDQ2_2PORT | 25.535
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_RETENTION2_2PORT | 32.4295
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_IDDQROWSTRIPE_2PORT | 26.0375
PBIST_RAMGROUP_14_HETTU1 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 26.015
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_MARCH13N_RED_2PORT | 75.215
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_DOWN1A_RED_2PORT | 27.695
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_MAPCOLUMN_2PORT | 30.815
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_PRECHARGE_2PORT | 26.495
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_DTXN2_2PORT | 37.775
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_PMOS_OPEN_2PORT | 58.175
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 58.175
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_FLIP10_2PORT | 23.135
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_IDDQ_2PORT | 15.935
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_RETENTION_2PORT | 16.175
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_IDDQ2_2PORT | 15.935
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_RETENTION2_2PORT | 16.175
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_IDDQROWSTRIPE_2PORT | 16.175
PBIST_RAMGROUP_18_MIBADC2 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 16.175
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_MARCH13N_RED_2PORT | 452.329
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_DOWN1A_RED_2PORT | 120.365
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_MAPCOLUMN_2PORT | 142.415
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_PRECHARGE_2PORT | 111.215
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_DTXN2_2PORT | 157.017
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_PMOS_OPEN_2PORT | 19.495
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 260.975
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_FLIP10_2PORT | 93.695
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_IDDQ_2PORT | 40.415
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_RETENTION_2PORT | 40.895
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_IDDQ2_2PORT | 40.415
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_RETENTION2_2PORT | 40.895
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_IDDQROWSTRIPE_2PORT | 41.365
PBIST_RAMGROUP_19_N2HET2 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 49.15
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_MARCH13N_RED_2PORT | 144.605
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_DOWN1A_RED_2PORT | 50.975
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_MAPCOLUMN_2PORT | 56.255
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_PRECHARGE_2PORT | 49.295
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_DTXN2_2PORT | 57.695
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_PMOS_OPEN_2PORT | 80.735
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 80.975
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_FLIP10_2PORT | 36.335
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_IDDQ_2PORT | 25.535
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_RETENTION_2PORT | 25.775
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_IDDQ2_2PORT | 28.457
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_RETENTION2_2PORT | 25.7975
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_IDDQROWSTRIPE_2PORT | 26.015
PBIST_RAMGROUP_20_HETTU2 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 26.015
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_MARCH13N_RED_2PORT | 138.815
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_DOWN1A_RED_2PORT | 43.535
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_MAPCOLUMN_2PORT | 49.535
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_PRECHARGE_2PORT | 41.135
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_DTXN2_2PORT | 53.855
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_PMOS_OPEN_2PORT | 19.705
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 77.375
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_FLIP10_2PORT | 35.135
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_IDDQ_2PORT | 20.495
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_RETENTION_2PORT | 20.495
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_IDDQ2_2PORT | 20.495
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_RETENTION2_2PORT | 20.498
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_IDDQROWSTRIPE_2PORT | 20.519
PBIST_RAMGROUP_23_ETHERNET1 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 20.495
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_MARCH13N_RED_2PORT | 115.295
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_DOWN1A_RED_2PORT | 39.215
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_MAPCOLUMN_2PORT | 44.735
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_PRECHARGE_2PORT | 38.015
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_DTXN2_2PORT | 54.335
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_PMOS_OPEN_2PORT | 77.375
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_PMOS_OPEN_SLICE1_2POR | 77.375
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_FLIP10_2PORT | 30.815
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_IDDQ_2PORT | 20.015
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_RETENTION_2PORT | 20.255
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_IDDQ2_2PORT | 20.015
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_RETENTION2_2PORT | 20.255
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_IDDQROWSTRIPE_2PORT | 20.52
PBIST_RAMGROUP_24_ETHERNET2 | PBISTALGO_IDDQROWSTRIPE2_2PORT | 20.522
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_MAPCOLUMN_1PORT | 348.865
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_PRECHARGE_1PORT | 225.255
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_DTXN2_1PORT | 921.023
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_PMOS_OPEN_1PORT | 2108.999
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_PMOS_OPEN_SLICE2_1POR | 14.6515
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_FLIP10_1PORT | 261.245
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_IDDQ_1PORT | 43.622
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_RETENTION_1PORT | 35.937
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_IDDQ2_1PORT | 35.835
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_RETENTION2_1PORT | 35.835
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_IDDQROWSTRIPE_1PORT | 36.035
PBIST_RAMGROUP_25_ETHERNET3 | PBISTALGO_IDDQROWSTRIPE2_1PORT | 36.035
boolean SL_SelfTest_PBIST_StopExec ( void )

This function stops the PBIST controller from executing further.

Parameters
[out] | None
[in] | None
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

boolean retVal;
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
(PBIST_RAMGROUP_07_MIBSPI1 |
PBIST_RAMGROUP_08_MIBSPI3 |
PBIST_RAMGROUP_09_MIBSPI5 |
PBIST_RAMGROUP_10_VIM |
PBIST_RAMGROUP_11_MIBADC1 |
PBIST_RAMGROUP_18_MIBADC2),
PBISTALGO_MARCH13N_RED_2PORT);
while (TRUE != SL_SelfTest_PBIST_ExecStatus(&pbistStatus));
retVal = SL_SelfTest_PBIST_StopExec();
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_PBIST & SL_SelfTest_PBIST_StopExec
boolean SL_SelfTest_PSCON | ( | SL_SelfTestType | testType,
 |  | boolean | mode,
 |  | SL_PSCON_FailInfo * | param1
 | ) |  |

Provides interface to run PSCON self tests.

Description:
contains the logic to place the PSCON diagnostic compare block in a self-test mode in order
to test the * failsafe feature. Three diagnostic features are supported by this API.
  • Self-Test Mode : The compare error signal output is disabled in self-test mode. The PSCON
    diagnostic compare block generates two types of patterns during self-test mode:
    compare match test followed by compare mismatch test. During the self-test,
    each test pattern is applied on both PSCON signal ports of the PSCON diagnostic
    compare block and then is clocked for one cycle.
  • Error Forcing Mode : This mode is designed specifically to ensure that the error signal output
    from the PSCON compare block is not stuck inactive. In this mode, a test pattern
    is applied to the PSCON related inputs of the compare logic to force an error.
  • Self-test Error Forcing Mode : In this mode, an error is forced so that the self-test error output
    from the PSCON compare block is activated.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] testType - Indicates 1 of 3 tests to be run
[in] mode - When TRUE the function behaves synchronous (waits for test to complete & returns status) When FALSE the test is started and user has to use the SL_SelfTest_PSCON_Status to check the status & results.
Note: Only self-test (#1) can be run in async mode (mode=FALSE). Rest of the tests are always synchronous
[out] param1 - Pointer to structure that is used to return the test status & results.
Note: param1.pdFailure & param1.mdFailure are valid only for self-test mode.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

SL_PSCON_FailInfo failInfoPSCON;
boolean retVal;
retVal = SL_SelfTest_PSCON(PSCON_SELF_TEST, TRUE, &failInfoPSCON);
retVal = SL_SelfTest_PBIST_StopExec();
if ((TRUE == retVal) && (ST_PASS == failInfoPSCON.stResult)) {
//test passed
} else {
//test failed
}
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_PSCON_Status
Profiling Information of Tests:
TestType | Profiling Time in us
PSCON_SELF_TEST | 2.2585
PSCON_ERROR_FORCING | 1.741
PSCON_SELF_TEST_ERROR_FORCING | 1.757
PSCON_PMA_TEST | 0.9365
boolean SL_SelfTest_SRAM | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_SelfTest_Result * | sram_stResult
 | ) |  |

Executes diagnostic tests on TCM RAM SECDED logic.

Description:
The on-chip TCM SRAM is supported by SECDED ECC diagnostics. This function forces 1Bit/2Bit
errors and checks for proper error responses.

Please refer to _SL_SelfTest_Type for the values to be used for testType

Parameters
[in] | testType | - Specifies 1Bit/2But/RAD test
[in] | bMode | - NOT USED
[in] param1 - Pointer to structure that is used to return the test status & results
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection modes.
Returns
TRUE if function executed successfully else FALSE

Example Usage:

boolean retVal;
//Execute 1Bit test
SL_SelfTest_Result sram_stResult;
retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &sram_stResult);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
Type:_SL_SelfTest_Type
Profiling Information of Tests:
TestType | Profiling Time in us
SRAM_ECC_ERROR_FORCING_1BIT | 12.4245
SRAM_ECC_ERROR_FORCING_2BIT | 10.6655
SRAM_PAR_ADDR_CTRL_SELF_TEST | 17.566
SRAM_RADECODE_DIAGNOSTICS | 11.065
boolean SL_SelfTest_Status_CCMR4F ( SL_CCMR4F_FailInfo * failInfoccmr4f )

Returns the self test result for the previous CCRM4F selftest execution(SL_SelfTest_CCMR4F).To be used whenever the API SL_SelfTest_CCMR4F
is called in asynchronous mode i.e. when the parameter bMode of SL_SelfTest_CCMR4F is FALSE.

The CCMR4F selftest API SL_SelfTest_CCMR4F can run in asynchronous and in synchronous mode for the testType
CCMR4F_SELF_TEST.Whenever the API SL_SelfTest_CCMR4F is called in asynchronous mode the results of the previous CCMR4F
selftest can be accessed or got by calling this function.

Parameters
[in] failInfo - Pointer to structure used for returning the test result.
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.
[out] None
Returns
TRUE indicates that the test was complete and failInfo contents are valid. . FALSE indicates that the test is still executing.

Example Usage:

SL_CCMR4F_FailInfo failInfoCCMR4F;
retVal = SL_SelfTest_CCMR4F(CCMR4F_SELF_TEST, FALSE, &failInfoCCMR4F);
while (TRUE == SL_SelfTest_CCMR4F(&faileInfoCCMR4F));
if (failInfoCCMR4F.stResult == ST_FAIL) {
// Self test failed.. for details of failure info read failInfoCCMR4F.failInfo
}
Entry Mode:
Any Privilege Mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_CCMR4F

Note : This API is only valid when SL_SelfTest_CCMR4F is called in async mode(with bMode=FALSE)

boolean SL_SelfTest_Status_CCMR5F | ( | SL_SelfTestType | diagnostic,
 |  | SL_CCMR5F_FailInfo * | failInfoccmr5f
 | ) |  |

Returns the self test result for the previous CCRM4F selftest execution(SL_SelfTest_CCMR5F).To be used whenever the API SL_SelfTest_CCMR5F
is called in asynchronous mode i.e. when the parameter bMode of SL_SelfTest_CCMR5F is FALSE.

The CCMR5F selftest API SL_SelfTest_CCMR5F can run in asynchronous and in synchronous mode for the testType
CCMR5F_CPUCOMP_SELF_TEST.Whenever the API SL_SelfTest_CCMR5F is called in asynchronous mode the results of the previous CCMR5F
selftest can be accessed or got by calling this function.

Parameters
[in] failInfo - Pointer to structure used for returning the test result.
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.
[out] None
Returns
TRUE indicates that the test was complete and failInfo contents are valid. . FALSE indicates that the test is still executing.

Example Usage:

SL_CCMR5F_FailInfo failInfoCCMR5F;
retVal = SL_SelfTest_CCMR5F(CCMR5F_CPUCOMP_SELF_TEST, FALSE,
&failInfoCCMR5F);
while (TRUE == SL_SelfTest_CCMR5F(&faileInfoCCMR5F));
if (failInfoCCMR5F.stResult == ST_FAIL) {
// Self test failed.. for details of failure info read
failInfoCCMR5F.failInfo
}
Entry Mode:
Any Privilege Mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_CCMR5F

Note : This API is only valid when SL_SelfTest_CCMR5F is called in async mode(with bMode=FALSE)

boolean SL_SelfTest_Status_EFuse ( SL_EFuse_FailInfo * failInfoefuse )

Retrieves the status of the previous EFuse self-test execution.

Parameters
[in] | failInfo | - Pointer to structure that will be used to return the execution results. For details on structure member refer to documentation on SL_EFuse_FailInfo documentation.
[out] | None
Returns
TRUE if the self-test was completed. Else FALSE (self-test is still running).

Example Usage:

SL_SelfTest_Status_EFuse(&failInfo);
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_SelfTest_EFuse

ECC Self test has been enabled, check the results accordingly

boolean SL_SelfTest_Status_PBIST ( SL_PBIST_FailInfo * param1 )

Provides status information on the previous PBIST execution.

Description:
This API returns FALSE if the PBIST execution has not yet completed and if the PBIST execution is over the
the API updates the failinfo parameter with the relavant information on the status of the PBIST execution.This can be used
as apolling function after the call of the SL_SelfTest_PBIST API in order to get the status of the PBIST selftest.
Parameters
[out] | param1 | - Pointer to structure that is used to return the test status & results.
[in] | None
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

boolean retVal;
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
(PBIST_RAMGROUP_07_MIBSPI1 |
PBIST_RAMGROUP_08_MIBSPI3 |
PBIST_RAMGROUP_09_MIBSPI5 |
PBIST_RAMGROUP_10_VIM |
PBIST_RAMGROUP_11_MIBADC1 |
PBIST_RAMGROUP_18_MIBADC2),
PBISTALGO_MARCH13N_RED_2PORT);
while (TRUE != SL_SelfTest_Status_PBIST(&pbistStatus));
retVal = SL_SelfTest_PBIST_StopExec();
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_PBIST & SL_SelfTest_PBIST_StopExec
boolean SL_SelfTest_Status_PSCON ( SL_PSCON_FailInfo * param1 )

Returns the status for previous PSCON self-test execution
.

Note: Does not support status checking of error-forcing modes since these are synchronous in nature.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[out] param1 - Pointer to structure that is used to return the test status & results.
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

boolean retVal;
while (TRUE != SL_SelfTest_PBIST_ExecStatus(&pbistStatus));
retVal = SL_SelfTest_PBIST_StopExec();
if (TRUE == pbistStatus.pbistStatus) {
//test passed
} else {
//test failed
}
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_PSCON
boolean SL_SelfTest_Status_STC ( SL_STC_FailInfo * failInfostc )

Returns the status of previously executed CPU self-test via STC.

Parameters
[in] failinfostc - Pointer to SL_STC_FailInfo. For more details on the return values refer to
SL_STC_FailInfo structure documentation.
[out] None
Returns
TRUE - If the self test was completed, else FALSE (a failure occurred during self test).

Example Usage:

// Start if debugger not connected & reset type is not CPU or DEBUGGER
if ((RESET_TYPE_CPU != resetReason) && (RESET_TYPE_DEBUG != resetReason)) {
stcSelfTestConfig.stcClockDiv = 0; // STC Clock divider = 1
stcSelfTestConfig.intervalCount = 1; // One interval only
stcSelfTestConfig.restartInterval0 = TRUE; // Start from interval 0
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF; // Timeout counter
SL_SelfTest_STC(STC_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);
}
// If STC was executed, get STC self-test status
if (RESET_TYPE_CPU == resetReason) {
retVal = SL_SelfTest_Status_STC (&failInfoSTC);
}
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_SelfTest_STC
boolean SL_SelfTest_STC | ( | register SL_SelfTestType | testType,
 |  | register boolean | bMode,
 |  | register SL_STC_Config * | config
 | ) |  |

Executes CPU Logic Built-In Self Test using Self-Test Controller.

Description:
The Hercules family architecture supports the use of a hardware logic BIST (LBIST) engine self-test
controller (STC). This logic is used to provide a very high diagnostic coverage on the lockstep CPUs
at a transistor level. This logic utilizes the same design for test (DFT) structures inserted into
the device for rapid execution of high quality manufacturing tests, but with an internal test engine
rather than external automated test equipment (ATE).
This function triggers the LBIST using the user provided parameters, thus providing runtime diagnostics
with execution of test time slices per safety critical loop as well as comprehensive CPU test during
initialization.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] | testType | - Must be STC_RUN
[in] | bMode | - NOT USED
[in] | config | - Pointer to structure containing the configuration items. Refer to SL_STC_Config for details of configurable items.
Returns
FALSE - If the function failed to execute STC. Function DOES NOT RETURN if STC was started.

Note: At the end of the STC execution a CPU reset is issued by the STC controller. So the application startup must ensure that the STC is not-executed when reset type is RESET_TYPE_CPU & when the debugger is connected.

Example Usage:

// Start if debugger not connected & reset type is not CPU or DEBUGGER
if ((RESET_TYPE_CPU != resetReason) && (RESET_TYPE_DEBUG != resetReason)) {
stcSelfTestConfig.stcClockDiv = 0; // STC Clock divider = 1
stcSelfTestConfig.intervalCount = 1; // One interval only
stcSelfTestConfig.restartInterval0 = TRUE; // Start from interval 0
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF; // Timeout counter
SL_SelfTest_STC(STC_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);
}
// If STC was executed, get STC self-test status
if (RESET_TYPE_CPU == resetReason) {
retVal = SL_SelfTest_Status_STC (&failInfoSTC);
}
Entry Mode:
Any Privilege Mode
Exit Mode:
NA - (CPU Reset is issued at the end of STC execution)
See also:
SL_SelfTest_Status_STC
boolean SL_SelfTest_WaitCompletion_PBIST ( void )

Provides information regarding whether PBIST is active or not.

Parameters
[out] | None
[in] | Pointer | to structure that is used to return the test status & results.
Returns
TRUE if PBIST is running(wait for completion) FALSE if PBIST is not running

Example Usage:

boolean retVal;
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
(PBIST_RAMGROUP_07_MIBSPI1 |
PBIST_RAMGROUP_08_MIBSPI3 |
PBIST_RAMGROUP_09_MIBSPI5 |
PBIST_RAMGROUP_10_VIM |
PBIST_RAMGROUP_11_MIBADC1 |
PBIST_RAMGROUP_18_MIBADC2),
PBISTALGO_MARCH13N_RED_2PORT);
while (TRUE != SL_SelfTest_WaitCompletion_PBIST(&pbistStatus));
retVal = SL_SelfTest_Status_PBIST(pbistfailinfo);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_PBIST
boolean SL_SelfTestL2L3Interconnect ( SL_SelfTestType testType )

It does the Fault injection on L2(Switched central resource) and L3(Peripheral central resource) interconnects.
Below is the flowchart for the SL_SelfTestL2L3Interconnect.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] testType Indicates the type of fault injection to perform.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

//Trigger L2 interconnect error trap
SL_L2L3Interconnect_FI(L2INTERCONNECT_FAULT_INJECT);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
void SL_Set_nERROR ( void )

Function sets the nERROR pin active.

Parameters
[in] | None
[out] | None
Returns
None
Entry Mode:
Any privilege mode
Exit Mode:
Same as at entry
void SL_SW_Reset ( void )

This function generates an internal warm reset(nRST). This is done by writing appropriate
control bits in the SYSECR control register.

Parameters
[in] | None
[out] | None
Returns
None

Example Usage:

SL_SW_Reset();
Entry Mode:
Any Privilege Mode
Exit Mode:
Not Applicable (since the device resets)
See also:
SL_Init_ResetReason & SL_Init_ResetReason_XInfo
#include <sl_types.h>
#include <sl_config.h>
#include <sl_log.h>
#include <reg_bitdefn_ccmr4f.h>
#include <reg_bitdefn_ccmr5f.h>
#include <reg_bitdefn_dcc.h>
#include <reg_bitdefn_efc.h>
#include <reg_bitdefn_esm.h>
#include <reg_bitdefn_f021flash.h>
#include <reg_bitdefn_iomm.h>
#include <reg_bitdefn_pbist.h>
#include <reg_bitdefn_pmm.h>
#include <reg_bitdefn_rti.h>
#include <reg_bitdefn_stc.h>
#include <reg_bitdefn_system.h>
#include <reg_bitdefn_tcmram.h>
#include <reg_bitdefn_l2ramw.h>
#include <reg_bitdefn_dma.h>
#include <reg_bitdefn_can.h>
#include <reg_bitdefn_mibspi.h>
#include <reg_bitdefn_epc.h>
#include <reg_bitdefn_vim.h>
#include <reg_bitdefn_adc.h>

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SafeTI™ Diagnostic Library: safety_library/include/sl_config.h File Reference

  • File List
  • Globals
  • safety_library
  • include
sl_config.h File Reference

SafeTI™ Hercules™ Diagnostic Library configuration items. More...

Detailed Description

SafeTI™ Hercules™ Diagnostic Library configuration items.

Version
2.2.0

The configuration items of the SafeTI™ Hercules™ Diagnostic library
such as enabling of profiling,enabling of the logging,setting of stack
etc needs to be included in this file.

Go to the source code of this file.

Generated on Fri Feb 6 2015 03:20:29 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: safety_library/include/sl_log.h File Reference

  • File List
  • Globals
  • safety_library
  • include
sl_log.h File Reference

API's for logging(errors,results) and profiling of functions. More...

Detailed Description

API's for logging(errors,results) and profiling of functions.

Version
2.2.0

This file provides the prototypes of the API's which are used for
function result and error logging and the API's which can be used for the profiling
of the selftest and fault injection API's.

Function Documentation

void SL_Log_Error | ( | SL_Log_FuncId | fnId,
 |  | uint32 | errType,
 |  | uint32 | errNum
 | ) |  |

This function logs the errors that were captured by the SafeTI™ Hercules™ Diagnostic library API in the log buffer.

This function is used by the SafeTI™ Hercules™ Diagnostic Library APIs to log the errors generated during the function call. Applications can later use this buffer (&codes) to debug or analyze the errors generated in the process of executing the function

Parameters
[in] | fnId | - Function ID
[in] | errorType | - Error type
[in] | errNum | - Function specific error code.
Returns
None
#include <sl_api.h>

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SafeTI™ Diagnostic Library: safety_library/include/sl_types.h File Reference

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  • safety_library
  • include
sl_types.h File Reference

File contains the types used by the SafeTI™ Hercules™ Diagnostic Library APIs. More...

Detailed Description

File contains the types used by the SafeTI™ Hercules™ Diagnostic Library APIs.

Version
2.2.0

The macros,enumerations,structures which are used within the
sl_selftest.c file are to be declared here.This files serves as a type file for
the SafeTI™ Hercules™ Diagnostic library the types specific for the SafeTI™ Hercules™ Diagnostic library API's are
declared here.

Typedef Documentation

ESM_Application_Callback

Definition for ESM Application call back type.

Description:
The esm application call back happens in case of fault injections and actual device faults. There will be no callback in case of failures in the selftests.
The application should use the provided status function to get the status (pass/fail) of the last selftest which was triggered.
Parameters
grpchannel - ESM Channel Number and group indicator to the application.Upper 16 bits indicate the group and lower 16 bits indicate the channel.
group indicate 1- for group1 and 2- for group2.
param - Additional error information. Contents & type depends on channel# and are described below

NOTE: No additional error information is defined for the ESMs in case of the RM57Lx and the TMS570LC43x devices currently. The application must read the appropriate error information from the module signalling the ESM directly.

|-----------------------—|--------------------------------------------------------------------------------------—|

channel (ESM_xxxx) | Description
G3ERR_EFUSE_AUTOLOAD_ERR | Not Applicable
-----------------------— | --------------------------------------------------------------------------------------—
G3ERR_B0TCM_ECC_UNCORR | Not Applicable
-----------------------— | --------------------------------------------------------------------------------------—
G3ERR_B1TCM_ECC_UNCORR | Not Applicable
-----------------------— | --------------------------------------------------------------------------------------—
G3ERR_FMC_UNCORR | Not Applicable
-----------------------— | --------------------------------------------------------------------------------------—
G2ERR_CCMR4_COMP | None
-----------------------— | --------------------------------------------------------------------------------------—
G2ERR_FMC_UNCORR | param1 - In case of Bus Parity Errors [31-0] indicates address location. In case of
 | ECC errors [31-23] 64bit aligned address and [0-2] are 0.
 | param2 & param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G2ERR_B0TCM_UNCORR | param1 - Address which failed the parity check as an offset from the base address of
 | TCM RAM (0x0800_0000 by default)
 | param2 & param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G2ERR_B1TCM_UNCORR | param2 - Address which failed the parity check as an offset from the base address of
 | TCM RAM (0x0800_0000 by default)
 | param1 & param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G2ERR_B0TCM_ADDPAR | param1 -
 | param2 - param[8] - 1: Indicates a Read Address Parity failure
 | param[9] - 1: Indicates a Write Address Parity failure
 | param2[31-10], param2[7-0] & param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G2ERR_B1TCM_ADDPAR | None
-----------------------— | --------------------------------------------------------------------------------------—
G2ERR_FLASH_LIVLCK | None
-----------------------— | --------------------------------------------------------------------------------------—
G2ERR_RTI_WWD_NMI | None
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_FMC_CORR | param1 - 16bit counter contains the number of correctable error occurrences
 | param2 - 32bit CPU address for which a correctable error is detected
 | param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_PLL1_SLIP | param1[0] - 1: Indicates a under cycle slip error
 | param1[1] - 1: Indicates a over cycle slip error
 | param2 & param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_CLOCKMON_INTR | param1, param2, param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_VIMRAM_PARITY | param1 - 32bit address of the first parity error location
 | param2, param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_B0TCM_CORRERR | param1[17-3] - [17-3] of the address for which the Cortex-R4F CPU detects a single-bit
 | error
 | param2 & param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_B1TCM_CORRERR | param1[17-3] - [17-3] of the address for which the Cortex-R4F CPU detects a single-bit
 | error
 | param2 & param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_DCC1_ERR | param1[19-0] - Indicates the current value of Counter0
 | param2[19-0] - Indicates the current value of Counter1
 | param3 - RESERVED
 | param1[19-0] - Indicates the current counter values might not be accurate
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_EEPROM_CORRERR | param1, param2 & param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_EEPROM_UNCORRERR | param1, param2 & param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_PLL2_SLIP | param1, param2 & param3 - RESERVED
-----------------------— | --------------------------------------------------------------------------------------—
G1ERR_DCC2_ERR | param1[19-0] - Indicates the current value of Counter0
 | param2[19-0] - Indicates the current value of Counter1
 | param3 - RESERVED
 | param1[19-0] - Indicates the current counter values might not be accurate
-----------------------— | --------------------------------------------------------------------------------------—

Enumeration Type Documentation

enum _SL_ADC_Pinstatus
Enumerator
ADC_PIN_GOOD | The pinstate of adc is good and is usable
ADC_PIN_SHORTED_TO_ADVREF_HIGH | The pin of the ADC is shorted to ADVREF High
ADC_PIN_SHORTED_TO_ADVREF_LOW | The pin of the ADC is shorted to ADVREF Low
ADC_PIN_OPEN | The pin of the ADC pin is open
ADC_PIN_UNDETERMINED | The pin of the ADC pin state is undetermined
enum _SL_AutoInitRamId
Enumerator
RAMTYPE_RAM | Internal RAM
RAMTYPE_DMA_RAM | DMA RAM
RAMTYPE_VIM | VIM RAM
RAMTYPE_NHET1 | NHET1 RAM
RAMTYPE_HET_TU1 | HTU RAM
RAMTYPE_NHET2 | NHET2 RAM
RAMTYPE_HET_TU2 | HTU2 RAM
RAMTYPE_DCAN1_RAM | DCAN1 RAM
RAMTYPE_DCAN2_RAM | DCAN2 RAM
RAMTYPE_DCAN3_RAM | DCAN3 RAM
RAMTYPE_DCAN4_RAM | DCAN4 RAM
RAMTYPE_MIBSPI1_RAM | MibSPI1 RAM
RAMTYPE_MIBSPI2_RAM | MibSPI2 RAM
RAMTYPE_MIBSPI3_RAM | MibSPI3 RAM
RAMTYPE_MIBSPI4_RAM | MibSPI4 RAM
RAMTYPE_MIBSPI5_RAM | MibSPI5 RAM
RAMTYPE_MIBADC1_RAM | MibADC1 RAM
RAMTYPE_MIBADC2_RAM | MibADC2 RAM
RAMTYPE_FTU_RAM | MibADC2 RAM
enum _SL_EFuse_Error
Enumerator
EFUSE_ERROR_NONE | Last operation completed successfully
EFUSE_ERROR_TIMEOUT | Controller times out because there is no last row sent from the FuseROM
EFUSE_ERROR_AUTOLOAD_1 | Autoload machine did not find enough FuseROM data to fill the scan chain
EFUSE_ERROR_AUTOLOAD_2 | The autoload machine was able to filll the scan chain, but the wrong signature was returned
EFUSE_ERROR_AUTOLOAD_INTRPTD | Autoload machine was not able or not allowed to complete its operation
EFUSE_ERROR_AUTOLOAD_2B_ERR | 2Bit error detected during Autoload
EFUSE_ERROR_PROG_W_PROTECT | The write protect bit of the chip/row address stored in the controller's address register is set to 1
EFUSE_ERROR_PROG_W_D_ITER | The number of times that the controller tried and failed to write r exceeded the maximum number of iterations allowed (16)
EFUSE_ERROR_PROG_CTRL_ITER | The number of times that the controller tried and failed to write the control bits r exceeded the maximum number of iterations allowed (16)
EFUSE_ERROR_UNPROG_BIT_SET | A bit was found to be set by the test unprogrammed FuseROM instruction
EFUSE_ERROR_RED_REP_ROW | Two rows where the repair bit is set point to the same repair row.
enum _SL_ResetReason
Enumerator
RESET_TYPE_UNKNOWN | Reset reason is unknow
RESET_TYPE_POWERON | nPORRST Reset or VMON Reset
RESET_TYPE_OSC_FAILURE | Reset due to Oscillator failure
RESET_TYPE_WATCHDOG | Reset due to Watchdog expirty
RESET_TYPE_DEBUG | Reset due to software(Debug)
RESET_TYPE_ICEPICK | Reset by Ice Pick (JTAG)
RESET_TYPE_CPU | Reset due to CPU SelfTest Completion or toggling of SL_CPU_RESET bit
RESET_TYPE_SWRST | Software Reset
RESET_TYPE_EXTRST | nRST reset or Warm Reset
RESET_TYPE_EXTRST_NERROR | nRST due to nERROR
enum _SL_SelfTest_Type
Enumerator
SRAM_ECC_ERROR_FORCING_1BIT | BTCM SRAM 1-Bit ECC Error forcing tests(to be used with API SL_SelfTest_SRAM) L2 interconnect fault injection to create error trap (to be used with API SL_SelfTestL2L3Interconnect) L3 interconnect fault injection to create error trap(to be used with API SL_SelfTestL2L3Interconnect) L2RAMW SECDED 1-Bit ECC Error forcing tests(to be used with API SL_SelfTest_SRAM)
SRAM_ECC_1BIT_FAULT_INJECTION | BTCM SRAM 1-Bit ECC Fault injection(to be used with API SL_SelfTest_SRAM)
SRAM_ECC_ERROR_FORCING_2BIT | BTCM SRAM 2-Bit ECC Error forcing test(to be used with API SL_SelfTest_SRAM) L2RAMW SECDED 2-Bit ECC Error forcing test(to be used with API SL_SelfTest_SRAM)
SRAM_ECC_2BIT_FAULT_INJECT | BTCM SRAM 2-Bit ECC Error fault inject (to be used with API SL_SelfTest_SRAM)
SRAM_PAR_ADDR_CTRL_SELF_TEST | BTCM SRAM Address & Control Parity self test(to be used with API SL_SelfTest_SRAM)
SRAM_ECC_ERROR_PROFILING | SRAM Single bit Error Profiling test(to be used with API SL_SelfTest_SRAM)
SRAM_ECC_ERROR_PROFILING_FAULT_INJECT | SRAM Single bit Error Profiling fault injection(to be used with API SL_SelfTest_SRAM)
SRAM_RADECODE_DIAGNOSTICS | SRAM Redundant Address Decode self test(to be used with API SL_SelfTest_SRAM)
FEE_ECC_DATA_CORR_MODE | ECC Data correction diagnostic mode.(to be used with API SL_SelfTest_FEE)
FEE_ECC_SYN_REPORT_MODE | ECC Syndrome reporting diagnostic mode(to be used with API SL_SelfTest_FEE)
FEE_ECC_MALFUNCTION_MODE1 | ECC Malfunction test mode 1 (same data mode)(to be used with API SL_SelfTest_FEE)
FEE_ECC_MALFUNCTION_MODE2 | ECC malfunction test mode 2 (inverted data mode)(to be used with API SL_SelfTest_FEE)
FEE_ECC_ADDR_TAG_REG_MODE | Address tag register diagnostic mode(to be used with API SL_SelfTest_FEE)
FEE_ECC_TEST_MODE_1BIT | 1Bit ECC Data correction diagnostic mode(to be used with API SL_SelfTest_FEE)
FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT | Address tag register diagnostic mode(to be used with API SL_SelfTest_FEE)
FEE_ECC_TEST_MODE_2BIT | 2Bit ECC Data correction diagnostic mode.Verifies whether the 2 bit ecc error is getting created in FEE properly
FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT | 2Bit ECC Fault inject creates a 2 bit ecc error and leaves the application to handle the scenario
FLASH_ECC_ADDR_TAG_REG_MODE | Address tag register diagnostic mode(to be used with API SL_SelfTest_Flash)
FLASH_ADDRESS_ECC_SELF_TEST | Flash wrapper address ecc self test verifies whether the address ecc is working fine (to be used with API SL_SelfTest_Flash)
FLASH_ADDRESS_ECC_FAULT_INJECT | Flash wrapper address ecc self test fault inject creaters an address ecc error and leaves it for the application to handle it(to be used with API SL_SelfTest_Flash)
FLASH_ADDRESS_PARITY_SELF_TEST | Flash wrapper address parity self test.Verifies whether teh address parity feature is working fine
FLASH_ADDRESS_PARITY_FAULT_INJECT | Flash wrapper address parity self test fault inject creates an address parity error and leaves it for the application to handle it(to be used with API SL_SelfTest_Flash)
FLASH_ECC_TEST_MODE_1BIT | 1Bit ECC Data correction diagnostic mode(to be used with API SL_SelfTest_Flash) Test of the CPU SECDED for 1 bit ECC Error on read from L2FMC (to be used with API SL_SelfTest_Flash)
FLASH_ECC_TEST_MODE_2BIT | 2Bit ECC Data correction diagnostic mode(to be used with API SL_SelfTest_Flash) Test of the CPU SECDED for 2 bit ECC Error on read from L2FMC (to be used with API SL_SelfTest_Flash)
FLASH_ECC_TEST_MODE_2BIT_FAULT_INJECT | 2Bit ECC fault injection mode. No response handled. NOTE: Application must read from 0x20000000 to generate error(to be used with API SL_SelfTest_Flash)
PBIST_EXECUTE | PBIST self test mode .The RAM info register RINFOL and RINFOU are used to select the memories for test(to be used with API SL_SelfTest_PBIST)
PBIST_EXECUTE_OVERRIDE | PBIST test mode with ROM override.The memory information available from ROM will override the RAM selection from RAM info Registers (to be used with API SL_SelfTest_PBIST)
STC_RUN | CCMR4 test using STC(to be used with API SL_SelfTest_STC)
STC_COMPARE_SELFCHECK | STC self check diagnostic(to be used with API SL_SelfTest_STC)
PSCON_SELF_TEST | PSCON self test using Compare match & mismatch tests (to be used with API SL_SelfTest_PSCON)
PSCON_ERROR_FORCING | PSCON Error-Forcing self test mode (to be used with API SL_SelfTest_PSCON)
PSCON_ERROR_FORCING_FAULT_INJECT | PSCON Error-Forcing fault inject(to be used with API SL_SelfTest_PSCON)
PSCON_SELF_TEST_ERROR_FORCING | PSCON Self-Test Error forcing mode (to be used with API SL_SelfTest_PSCON)
PSCON_SELF_TEST_ERROR_FORCING_FAULT_INJECT | PSCON Self-Test Error forcing fault inject(to be used with API SL_SelfTest_PSCON)
PSCON_PMA_TEST | PSCON Privilege Mode access test - MUST BE RUN IN USER MODE (to be used with API SL_SelfTest_PSCON)
EFUSE_SELF_TEST_AUTOLOAD | EFuse Auto load self test (to be used with API SL_SelfTest_EFuse)
EFUSE_SELF_TEST_ECC | EFuse ECC Self test (to be used with API SL_SelfTest_EFuse)
EFUSE_SELF_TEST_STUCK_AT_ZERO | EFuse stuck-at-zero self test (to be used with API SL_SelfTest_EFuse)
CCMR4F_SELF_TEST | CCMR4F Self-test (to be used with API SL_SelfTest_CCMR4F)
CCMR4F_ERROR_FORCING_TEST | CCMR4F Error forcing test(to be used with API SL_SelfTest_CCMR4F)
CCMR4F_ERROR_FORCING_TEST_FAULT_INJECT | CCMR4F Error focing test, but does not clear the nERROR & ESM Interrupt (Callee function must clear these) (to be used with API SL_SelfTest_CCMR4F)
CCMR4F_SELF_TEST_ERROR_FORCING | CCMR4F Self-test error forcing (to be used with API SL_SelfTest_CCMR4F)
SRAM_ECC_ERROR_FORCING_1BIT | BTCM SRAM 1-Bit ECC Error forcing tests(to be used with API SL_SelfTest_SRAM) L2 interconnect fault injection to create error trap (to be used with API SL_SelfTestL2L3Interconnect) L3 interconnect fault injection to create error trap(to be used with API SL_SelfTestL2L3Interconnect) L2RAMW SECDED 1-Bit ECC Error forcing tests(to be used with API SL_SelfTest_SRAM)
SRAM_ECC_ERROR_FORCING_2BIT | BTCM SRAM 2-Bit ECC Error forcing test(to be used with API SL_SelfTest_SRAM) L2RAMW SECDED 2-Bit ECC Error forcing test(to be used with API SL_SelfTest_SRAM)
FLASH_ECC_TEST_MODE_1BIT | 1Bit ECC Data correction diagnostic mode(to be used with API SL_SelfTest_Flash) Test of the CPU SECDED for 1 bit ECC Error on read from L2FMC (to be used with API SL_SelfTest_Flash)
FLASH_ECC_TEST_MODE_2BIT | 2Bit ECC Data correction diagnostic mode(to be used with API SL_SelfTest_Flash) Test of the CPU SECDED for 2 bit ECC Error on read from L2FMC (to be used with API SL_SelfTest_Flash)
PBIST_EXECUTE | PBIST self test mode .The RAM info register RINFOL and RINFOU are used to select the memories for test(to be used with API SL_SelfTest_PBIST)
PBIST_EXECUTE_OVERRIDE | PBIST test mode with ROM override.The memory information available from ROM will override the RAM selection from RAM info Registers (to be used with API SL_SelfTest_PBIST)
EFUSE_SELF_TEST_AUTOLOAD | EFuse Auto load self test (to be used with API SL_SelfTest_EFuse)
EFUSE_SELF_TEST_ECC | EFuse ECC Self test (to be used with API SL_SelfTest_EFuse)
EFUSE_SELF_TEST_STUCK_AT_ZERO | EFuse stuck-at-zero self test (to be used with API SL_SelfTest_EFuse)
CCMR5F_CPUCOMP_SELF_TEST | CCMR5F CPU Comparator Self-test (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_CPUCOMP_ERROR_FORCING_TEST | CCMR5F CPU Compare Error forcing test(to be used with API SL_SelfTest_CCMR5F)
CCMR5F_CPUCOMP_ERROR_FORCING_TEST_FAULT_INJECT | CCMR5F CPU Compare Error Fault injection , but does not clear the nERROR & ESM Interrupt (Callee function must clear these) (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_CPUCOMP_SELF_TEST_ERROR_FORCING | CCMR5F CPU Comparator Self-test error forcing (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_VIMCOMP_SELF_TEST | CCMR5F VIM Comparator Self-test (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_VIMCOMP_ERROR_FORCING_TEST | CCMR5F VIM Compare Error forcing test(to be used with API SL_SelfTest_CCMR5F)
CCMR5F_VIMCOMP_ERROR_FORCING_TEST_FAULT_INJECT | CCMR5F VIM Compare Error focing test, but does not clear the nERROR & ESM Interrupt (Callee function must clear these) (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_VIMCOMP_SELF_TEST_ERROR_FORCING | CCMR5F VIM Comparator Self-test error forcing (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_PDCOMP_SELF_TEST | CCMR5F Power Domain Comparator Self-test (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_PDCOMP_ERROR_FORCING_TEST | CCMR5F Power Domain Compare Error forcing test(to be used with API SL_SelfTest_CCMR5F)
CCMR5F_PDCOMP_ERROR_FORCING_TEST_FAULT_INJECT | CCMR5F Power Domain Compare Error focing test, but does not clear the nERROR & ESM Interrupt (Callee function must clear these) (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_PDCOMP_SELF_TEST_ERROR_FORCING | CCMR5F Power Domain Comparator Self-test error forcing (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_INMCOMP_SELF_TEST | CCMR5F Inactive CPU Monitor Comparator Self-test (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_INMCOMP_ERROR_FORCING_TEST | CCMR5F Inactive CPU Monitor Compare Error forcing test(to be used with API SL_SelfTest_CCMR5F)
CCMR5F_INMCOMP_ERROR_FORCING_TEST_FAULT_INJECT | CCMR5F Inactive CPU Monitor Compare Error focing test, but does not clear the nERROR & ESM Interrupt (Callee function must clear these) (to be used with API SL_SelfTest_CCMR5F)
CCMR5F_INMCOMP_SELF_TEST_ERROR_FORCING | CCMR5F Inactive CPU Monitor Comparator Self-test error forcing (to be used with API SL_SelfTest_CCMR5F)
STC1_RUN | CPU test using STC1(to be used with API SL_SelfTest_STC)
STC1_COMPARE_SELFCHECK | STC1 self check diagnostic(to be used with API SL_SelfTest_STC)
DMA_ECC_TEST_MODE_1BIT | DMA RAM SECDED 1-Bit ECC Error forcing tests(to be used with API SL_SelfTest_DMA)
DMA_ECC_TEST_MODE_2BIT | DMA RAM SECDED 2-Bit ECC Error forcing tests(to be used with API SL_SelfTest_DMA)
DMA_ECC_TEST_MODE_1BIT_FAULT_INJECT | DMA RAM SECDED 1-Bit ECC Error Fault injection(to be used with API SL_SelfTest_DMA)
DMA_ECC_TEST_MODE_2BIT_FAULT_INJECT | DMA RAM SECDED 2-Bit ECC Error Fault injection(to be used with API SL_SelfTest_DMA)
CAN_ECC_TEST_MODE_1BIT | CAN RAM SECDED 1-Bit ECC Error forcing tests(to be used with API SL_SelfTest_CAN)
CAN_ECC_TEST_MODE_2BIT | CAN RAM SECDED 2-Bit ECC Error forcing tests(to be used with API SL_SelfTest_CAN)
CAN_ECC_TEST_MODE_1BIT_FAULT_INJECT | CAN RAM SECDED 1-Bit ECC Error Fault injection (to be used with API SL_SelfTest_CAN)
CAN_ECC_TEST_MODE_2BIT_FAULT_INJECT | CAN RAM SECDED 2-Bit ECC Error Fault injection (to be used with API SL_SelfTest_CAN)
MIBSPI_ECC_TEST_MODE_1BIT | MibSPI RAM SECDED 1-Bit ECC Error forcing tests (to be used with API SL_SelfTest_MibSPI)
MIBSPI_ECC_TEST_MODE_2BIT | MibSPI RAM SECDED 2-Bit ECC Error forcing tests (to be used with API SL_SelfTest_MibSPI)
MIBSPI_ECC_TEST_MODE_1BIT_FAULT_INJECT | MibSPI RAM SECDED 1-Bit ECC Error Fault injection(to be used with API SL_SelfTest_MibSPI)
MIBSPI_ECC_TEST_MODE_2BIT_FAULT_INJECT | MibSPI RAM SECDED 2-Bit ECC Error Fault injection (to be used with API SL_SelfTest_MibSPI)
#include "sl_sys_common.h"
#include "reg_bitdefn_adc.h"

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SafeTI™ Diagnostic Library: safety_library/source Directory Reference

  • safety_library
  • source
source Directory Reference

Files

file | sl_asm.inc
file | sl_asm_IAR.inc
file | sl_asm_KEIL.inc
file | sl_esm.c
File contains esm handling and interrupt handlers for esm errors.
file | sl_init.c
file | sl_log.c
file | sl_misc.c
file | sl_priv.c
file | sl_priv.h [code]
Private header file for SafeTI™ Hercules™ Diagnostic Library.
file | sl_selftest.c
File contains the Self Test APIs.
file | sl_sys_pmu.h [code]


SafeTI™ Diagnostic Library: safety_library/source/sl_esm.c File Reference

  • File List
  • Globals
  • safety_library
  • source
sl_esm.c File Reference

File contains esm handling and interrupt handlers for esm errors. More...

Detailed Description

File contains esm handling and interrupt handlers for esm errors.

Version
2.2.0

This file implements interrupt handlers for the esmHigh and esmLow interrupts
the esm group 2 and group 1 handlers have been implemented which can be further extended
depending on the end application.It provides the Init function which updates the application
callback function and the interrupt handlers for esmHigh and esmLow interrupt.It also provides
API's which provide the information on the nerror pin status

Function Documentation

static void esmGroup1Handler ( uint8 esmChannel )
static

F021 Flash Correctabe error (bus1 & bus2) & non-EEPROM

PLL1 Slip error

Store the callback parameters & reset the status registers

LPOCLK Detect error

VIM Parity Error

B0TCM ECC Correctable error

B1TCM ECC Correctable error

DCC Error

CCMR4 Self-Test Compare error

PLL2 Slip error

DCC Error

void SL_ESM_Init ( ESM_Application_Callback appCallback )

Initializes the ESM module handing in the SafeTI™ Hercules™ Diagnostic Library.

Description:
Once initialized all ESM notifications are decoded & 'appCallback' is called with the
parameters indicating the ESM failure information. For details on the failure information,
provided by this API, refer to documentation on ESM_Application_Callback.
Parameters
[in] | appCallback | - Application callback to be called for ESM notifications.
[out] | None
Returns
None

Example Usage:

void ESM_Callback(uint32 channel, uint32 param1, uint32 param2, uint32 param3);
void ESM_Callback(uint32 channel, uint32 param1, uint32 param2, uint32 param3)
{
Code for handling the ESM errors
}
SL_ESM_Init(ESM_Callback);
Entry Mode:
Any Privilege Mode
Exit Mode:
Same as at entry
See also:
ESM_Application_Callback
boolean SL_ESM_nERROR_Active ( void )

Function returns the status of the nERRORpin.

Parameters
[in] | None
[out] | None
Returns
TRUE if nERROR pin is active (low) else FALSE.
Entry Mode:
Any privilege mode
Exit Mode:
Same as at entry
#include <sl_api.h>
#include <sl_priv.h>
Generated on Fri Feb 6 2015 03:20:29 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: safety_library/source/sl_priv.h File Reference

  • File List
  • Globals
  • safety_library
  • source
sl_priv.h File Reference

Private header file for SafeTI™ Hercules™ Diagnostic Library. More...

Detailed Description

Private header file for SafeTI™ Hercules™ Diagnostic Library.

Version
2.2.0

Contains interfaces/definitions that are private to SafeTI™ Hercules™ Diagnostic library & are not
exposed to application.

Function Documentation

void _SL_SelfTest_SRAM_RAD | ( | sl_tcramBASE_t * | ramBase,
 |  | SL_SelfTest_Result * | rad_stResult
 | ) |  |

Start with the equality test scheme

Get single converted ADC value

Parameters
[in] adc Pointer to ADC module:
  • sl_adcREG1: ADC1 module pointer
  • sl_adcREG2: ADC2 module pointer
  • adcREG3: ADC3 module pointer
[in] group Hardware group of ADC module:
  • adcGROUP0: ADC event group
  • adcGROUP1: ADC group 1
  • adcGROUP2: ADC group 2
[out] data Pointer to store ADC converted data
#include <sl_types.h>
#include <sl_config.h>
#include <sl_api.h>
#include <sl_reg_system.h>

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SafeTI™ Diagnostic Library: safety_library/source/sl_selftest.c File Reference

  • File List
  • Globals
  • safety_library
  • source
sl_selftest.c File Reference

File contains the Self Test APIs. More...

Detailed Description

File contains the Self Test APIs.

Version
2.2.0

The file implements the api's for carrying out selftests and fault injection tests on/n all the peripherals (includes Safety island peripherals also).The utility functions or/n support functions which are used by this file are defined in either sl_misc.c or/n sl_priv.c

Function Documentation

boolean SL_adcCalibration | ( | sl_adcBASE_t * | adc,
 |  | uint32 * | offset_error
 | ) |  |

Computes offset error using Calibration mode Below is the flowchart for the SL_adcCalibration.

Parameters
[in] adc Pointer to ADC module:
  • sl_adcREG1: ADC1 module pointer
  • sl_adcREG2: ADC2 module pointer offset Pointer to uint32
Returns
TRUE if success FALSE if failure offset variable is updated with the computed offset error

Example Usage:

//Disable Interrupts
adc->GxINTENA[sl_adcGROUP1] = 0u;
//disable any self tst and Calib mode first
adc->CALCR = 0u;
//Enable 12-BIT ADC
(adc->OPMODECR) |= ADC_12BIT_RESOLUTION;
//Disable all channels for conversion
//Event select
adc->GxSEL[sl_adcGROUP1] = 0u;
//Calibrate the ADC so as to fill appropriate value in CALR register
SL_adcCalibration(adc, offset);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
  • Backup Mode before Calibration
  • Enable 12-BIT ADC
  • Restore Mode after Calibration
Note
The function adcInit has to be called before using this function.
boolean SL_SelfTest_ADC | ( | SL_SelfTestType | testType,
 |  | boolean | mode,
 |  | SL_ADC_Config * | config,
 |  | SL_ADC_Pinstatus * | pinstatus
 | ) |  |

It does the selftest on the required adc pin and provides the information on status of the Pin.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Below is the flowchart for the ADC self test

Parameters
[in] | testType | - None there are no Different types of test types for the ADC self test.
[in] | mode | - None Only Synchronous mode is supported.
[in] | config | - Pointer to structure that contains ADC base address and the Channel number.
[out] | pinstatus | - pointer to SL_ADC_Pinstatus it is output parameter and stores the state of the adc pin tested.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

//use the channel 7 and adc1
adcConfig.adc_channel = 7;
adcConfig.adcbase = sl_adcREG1;
//pin is not connected to any analog input
if( TRUE == SL_SefTest_ADC(0, 0, &adcConfig, &adc_pinstatus)) {
if (ADC_PIN_GOOD == adc_pinstatus) {
//testcase pass
} else {
//testcase fail
}
} else {
//testcase fail
}
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
_SL_ADC_Config, _SL_ADC_Pinstatus
  • Backup Mode before Calibration
  • Enable 12-BIT ADC
  • Restore Mode after Calibration
boolean SL_SelfTest_CAN | ( | SL_SelfTestType | testType,
 |  | SL_DCAN_Instance | instance
 | ) |  |

Perform a test of the SECDED ECC in CAN
.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] | testType | Indicates the type of fault injection to perform.
[in] | instance | Indicates the CAN port instance to be tested.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

SL_SelfTest_CAN(CAN_ECC_TEST_MODE_1BIT, SL_DCAN1);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
boolean SL_SelfTest_CCMR4F | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_CCMR4F_FailInfo * | config
 | ) |  |

Executes self-tests on Core Compare Module (CCM).

Description:
The Hercules product family includes a lockstep processor diagnostic. This feature includes the
addition of a diagnostic Cortex-R4F CPU that is combined into a 1oo1D (single channel with diagnostic
channel) configuration with the application CPU. The core compare module (CCM) compares the CPU
outputs and flags all mis-compares to the ESM.
The CCM logic provides self test and error forcing capability via software triggered hardware.
The self test ensures that the CCM compare logic is working properly. The error forcing capability
allows you to test the system level response to a lockstep miscompare.

Please refer to _SL_SelfTest_Type for the values to be used for testType

Parameters
[in] | testType | - Indicates the type of self test to run. For details refer to SL_SelTestType. documentation
[in] | bMode | - TRUE for synchronous mode & FALSE for async mode Parameter is valid only for CCMR4F_SELF_TEST selftest type.
[in] | config | - Structure used for returning the test results. For details refer to SL_CCMR4F_FailInfo documentation.**Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.**
Returns
TRUE if the test was executed else FALSE

Example Usage:

SL_CCMR4F_FailInfo failInfoCCMR4F;
retVal = SL_SelfTest_CCMR4F(CCMR4F_SELF_TEST, TRUE, &failInfoCCMR4F);
if (failInfoCCMR4F.stResult == ST_FAIL) {
// Self test failed.. for details of failure info read failInfoCCMR4F.failInfo
}
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_SelfTest_Status_CCMR4F
Profiling Information of Tests:
TestType | Profiling Time in us
CCMR4F_SELF_TEST | 10.405
CCMR4F_ERROR_FORCING_TEST | 7.556
CCMR4F_SELF_TEST_ERROR_FORCING | 5.04
boolean SL_SelfTest_CCMR5F | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_CCMR5F_FailInfo * | config
 | ) |  |

Executes self-tests on Core Compare Module (CCM).

Description:
The Hercules product family includes a lockstep processor diagnostic. This feature includes the
addition of a diagnostic Cortex-R5F CPU that is combined into a 1oo1D (single channel with diagnostic
channel) configuration with the application CPU. The core compare module (CCM) compares the CPU
outputs and flags all mis-compares to the ESM.
The CCM logic provides self test and error forcing capability via software triggered hardware.
The self test ensures that the CCM compare logic is working properly. The error forcing capability
allows you to test the system level response to a lockstep miscompare.

Please refer to _SL_SelfTest_Type for the values to be used for testType

Parameters
[in] | testType | - Indicates the type of self test to run. For details refer to SL_SelTestType. documentation
[in] | bMode | - TRUE for synchronous mode & FALSE for async mode Parameter is valid only for CCMR5F_SELF_TEST selftest type.
[in] | config | - Structure used for returning the test results. For details refer to SL_CCMR5F_FailInfo documentation.**Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.**
Returns
TRUE if the test was executed else FALSE

Example Usage:

SL_CCMR5F_FailInfo failInfoCCMR5F;
retVal = SL_SelfTest_CCMR5F(CCMR5F_SELF_TEST, TRUE, &failInfoCCMR5F);
if (failInfoCCMR5F.stResult == ST_FAIL) {
// Self test failed.. for details of failure info read failInfoCCMR5F.failInfo
}
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_SelfTest_Status_CCMR5F
Profiling Information of Tests:
TestType | Profiling Time in us
CCMR4F_SELF_TEST | 10.405
CCMR4F_ERROR_FORCING_TEST | 7.556
CCMR4F_SELF_TEST_ERROR_FORCING | 5.04
boolean SL_SelfTest_DMA ( SL_SelfTestType testType )

Perform a test of the SECDED ECC in DMA
.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] testType Indicates the type of fault injection to perform.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

SL_SelfTest_DMA(DMA_ECC_TEST_MODE_1BIT);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
boolean SL_SelfTest_EFuse | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_EFuse_Config * | config
 | ) |  |

This function executes self tests on the eFuse structures.

Description:
The Hercules platform devices support a manufacturing time configuration of certain functionality via a
one time programmable EFuse structures. The EFuses are read automatically after POR by an autoload function.
This function executes the diagnostic tests on detect incorrect configuration values.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] | testType | - Must be one of EFUSE_SELF_TEST_ECC or EFUSE_SELF_TEST_STUCK_AT_ZERO
[in] | bMode | - When TRUE function will wait for the test to complete (synchronous). Function will be async when FALSE & the use can must use SL_SelfTest_Status_EFuse to retrieve the result.
[in] | config | - Configuration parameters for the self tests. Refer to SL_EFuse_Config structure documentation for details of each configuration parameter.
Returns
TRUE if the tests were executed else FALSE. (Does not indicate the test result).

Example Usage:

// Run EFuse self tests
stConfigEFuse.numPatterns = 600u;
stConfigEFuse.seedSignature = 0x5362F97Fu;
stConfigEFuse.failInfo.stResult= ST_FAIL;
stConfigEFuse.failInfo.failInfo= EFUSE_ERROR_NONE;
retVal = SL_SelfTest_EFuse(EFUSE_SELF_TEST_STUCK_AT_ZERO, TRUE, &stConfigEFuse);
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_SelfTest_Status_EFuse
Profiling Information of Tests:
TestType | Profiling Time in us
EFUSE_SELF_TEST_ECC | 6.438
EFUSE_SELF_TEST_STUCK_AT_ZERO | 5.402
boolean SL_SelfTest_FEE | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_SelfTest_Result * | fee_stResult
 | ) |  |

Executes diagnostic tests on F021 Flash.

Description:
F021 Flash wrapper provides to verify various logic. The flash wrapper provides multiple diagnostic modes.
This function executes the selected diagnostic mode.

Please refer to _SL_SelfTest_Type for the values to be used for testType.
Note : Refer to Safety Manual for TMS570LS31x/21x and RM48x Hercules ARM Safety Critical Microcontrollers (section on Primary Embedded Flash and RM48x/TMS570LS31x 16/32-Bit RISC Flash Microcontroller TRM (section F021 Flash Module Controller)

Parameters
[in] | testType | - Specifies the test type to execute
[in] | bMode | - NOT USED
[in] fee_stResult - Pointer to structure that is used to return the test status & results
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection modes.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

boolean retVal;
//Execute 1Bit test
SL_SelfTest_Result flash_stResult;
retVal = SL_SelfTest_FEE(FLASH_ECC_SYN_REPORT_MODE, TRUE, &flash_stResult);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
Type:_SL_SelfTest_Type
boolean SL_SelfTest_Flash | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_SelfTest_Result * | flash_stResult
 | ) |  |

Executes diagnostic tests on F021 Flash.

Description:
F021 Flash wrapper provides to verify various logic. The flash wrapper provides multiple diagnostic modes.
Thisfunction executes the selected diagnostic mode.

Please refer to _SL_SelfTest_Type for the values to be used for testType

Note : Refer to Safety Manual for TMS570LS31x/21x and RM48x Hercules ARM Safety Critical Microcontrollers (section on Primary Embedded Flash and RM48x/TMS570LS31x 16/32-Bit RISC Flash Microcontroller TRM (section F021 Flash Module Controller)
Note: For FLASH_ECC_TEST_MODE_2BIT_FAULT_INJECT the fault is injected in the subsequent read of the corrupted flash area by the application. The application must take care to restore the flash diagnostic control registers . Note: FLASH_HARD_ERROR_LIVELOCK is not supported in this release.

Parameters
[in] | testType | - Specifies the test type to execute
[in] | bMode | - NOT USED
[in] flash_stResult - Pointer to structure that is used to return the test status & results
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.
Returns
TRUE if function executed successfully else FALSE

Example Usage:

boolean retVal;
//Execute 1Bit test
SL_SelfTest_Result flash_stResult;
retVal = SL_SelfTest_Flash(FLASHECC_ECC_TEST_MODE_1BIT, TRUE, &flash_stResult);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
Type:_SL_SelfTest_Type
Profiling Information of Tests:
TestType | Profiling Time in us
FLASH_ECC_ADDR_TAG_REG_MODE | 8.437
FLASH_ECC_TEST_MODE_1BIT | 7.3605
FLASH_ECC_TEST_MODE_2BIT | 13.3885
boolean SL_SelfTest_MibSPI | ( | SL_SelfTestType | testType,
 |  | SL_MIBSPI_Instance | instance
 | ) |  |

Perform a test of the SECDED ECC in MibSPI
.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] | testType | Indicates the type of fault injection to perform.
[in] | instance | Indicates the MibSPI port instance to be tested.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI1);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
boolean SL_SelfTest_PBIST_StopExec ( void )

This function stops the PBIST controller from executing further.

Parameters
[out] | None
[in] | None
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

boolean retVal;
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
(PBIST_RAMGROUP_07_MIBSPI1 |
PBIST_RAMGROUP_08_MIBSPI3 |
PBIST_RAMGROUP_09_MIBSPI5 |
PBIST_RAMGROUP_10_VIM |
PBIST_RAMGROUP_11_MIBADC1 |
PBIST_RAMGROUP_18_MIBADC2),
PBISTALGO_MARCH13N_RED_2PORT);
while (TRUE != SL_SelfTest_PBIST_ExecStatus(&pbistStatus));
retVal = SL_SelfTest_PBIST_StopExec();
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_PBIST & SL_SelfTest_PBIST_StopExec
boolean SL_SelfTest_PSCON | ( | SL_SelfTestType | testType,
 |  | boolean | mode,
 |  | SL_PSCON_FailInfo * | param1
 | ) |  |

Provides interface to run PSCON self tests.

Description:
contains the logic to place the PSCON diagnostic compare block in a self-test mode in order
to test the * failsafe feature. Three diagnostic features are supported by this API.
  • Self-Test Mode : The compare error signal output is disabled in self-test mode. The PSCON
    diagnostic compare block generates two types of patterns during self-test mode:
    compare match test followed by compare mismatch test. During the self-test,
    each test pattern is applied on both PSCON signal ports of the PSCON diagnostic
    compare block and then is clocked for one cycle.
  • Error Forcing Mode : This mode is designed specifically to ensure that the error signal output
    from the PSCON compare block is not stuck inactive. In this mode, a test pattern
    is applied to the PSCON related inputs of the compare logic to force an error.
  • Self-test Error Forcing Mode : In this mode, an error is forced so that the self-test error output
    from the PSCON compare block is activated.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] testType - Indicates 1 of 3 tests to be run
[in] mode - When TRUE the function behaves synchronous (waits for test to complete & returns status) When FALSE the test is started and user has to use the SL_SelfTest_PSCON_Status to check the status & results.
Note: Only self-test (#1) can be run in async mode (mode=FALSE). Rest of the tests are always synchronous
[out] param1 - Pointer to structure that is used to return the test status & results.
Note: param1.pdFailure & param1.mdFailure are valid only for self-test mode.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

SL_PSCON_FailInfo failInfoPSCON;
boolean retVal;
retVal = SL_SelfTest_PSCON(PSCON_SELF_TEST, TRUE, &failInfoPSCON);
retVal = SL_SelfTest_PBIST_StopExec();
if ((TRUE == retVal) && (ST_PASS == failInfoPSCON.stResult)) {
//test passed
} else {
//test failed
}
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_PSCON_Status
Profiling Information of Tests:
TestType | Profiling Time in us
PSCON_SELF_TEST | 2.2585
PSCON_ERROR_FORCING | 1.741
PSCON_SELF_TEST_ERROR_FORCING | 1.757
PSCON_PMA_TEST | 0.9365
boolean SL_SelfTest_SRAM | ( | SL_SelfTestType | testType,
 |  | boolean | bMode,
 |  | SL_SelfTest_Result * | sram_stResult
 | ) |  |

Executes diagnostic tests on TCM RAM SECDED logic.

Description:
The on-chip TCM SRAM is supported by SECDED ECC diagnostics. This function forces 1Bit/2Bit
errors and checks for proper error responses.

Please refer to _SL_SelfTest_Type for the values to be used for testType

Parameters
[in] | testType | - Specifies 1Bit/2But/RAD test
[in] | bMode | - NOT USED
[in] param1 - Pointer to structure that is used to return the test status & results
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection modes.
Returns
TRUE if function executed successfully else FALSE

Example Usage:

boolean retVal;
//Execute 1Bit test
SL_SelfTest_Result sram_stResult;
retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &sram_stResult);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
Type:_SL_SelfTest_Type
Profiling Information of Tests:
TestType | Profiling Time in us
SRAM_ECC_ERROR_FORCING_1BIT | 12.4245
SRAM_ECC_ERROR_FORCING_2BIT | 10.6655
SRAM_PAR_ADDR_CTRL_SELF_TEST | 17.566
SRAM_RADECODE_DIAGNOSTICS | 11.065
boolean SL_SelfTest_Status_CCMR4F ( SL_CCMR4F_FailInfo * failInfoccmr4f )

Returns the self test result for the previous CCRM4F selftest execution(SL_SelfTest_CCMR4F).To be used whenever the API SL_SelfTest_CCMR4F
is called in asynchronous mode i.e. when the parameter bMode of SL_SelfTest_CCMR4F is FALSE.

The CCMR4F selftest API SL_SelfTest_CCMR4F can run in asynchronous and in synchronous mode for the testType
CCMR4F_SELF_TEST.Whenever the API SL_SelfTest_CCMR4F is called in asynchronous mode the results of the previous CCMR4F
selftest can be accessed or got by calling this function.

Parameters
[in] failInfo - Pointer to structure used for returning the test result.
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.
[out] None
Returns
TRUE indicates that the test was complete and failInfo contents are valid. . FALSE indicates that the test is still executing.

Example Usage:

SL_CCMR4F_FailInfo failInfoCCMR4F;
retVal = SL_SelfTest_CCMR4F(CCMR4F_SELF_TEST, FALSE, &failInfoCCMR4F);
while (TRUE == SL_SelfTest_CCMR4F(&faileInfoCCMR4F));
if (failInfoCCMR4F.stResult == ST_FAIL) {
// Self test failed.. for details of failure info read failInfoCCMR4F.failInfo
}
Entry Mode:
Any Privilege Mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_CCMR4F

Note : This API is only valid when SL_SelfTest_CCMR4F is called in async mode(with bMode=FALSE)

boolean SL_SelfTest_Status_CCMR5F | ( | SL_SelfTestType | diagnostic,
 |  | SL_CCMR5F_FailInfo * | failInfoccmr5f
 | ) |  |

Returns the self test result for the previous CCRM4F selftest execution(SL_SelfTest_CCMR5F).To be used whenever the API SL_SelfTest_CCMR5F
is called in asynchronous mode i.e. when the parameter bMode of SL_SelfTest_CCMR5F is FALSE.

The CCMR5F selftest API SL_SelfTest_CCMR5F can run in asynchronous and in synchronous mode for the testType
CCMR5F_CPUCOMP_SELF_TEST.Whenever the API SL_SelfTest_CCMR5F is called in asynchronous mode the results of the previous CCMR5F
selftest can be accessed or got by calling this function.

Parameters
[in] failInfo - Pointer to structure used for returning the test result.
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.
[out] None
Returns
TRUE indicates that the test was complete and failInfo contents are valid. . FALSE indicates that the test is still executing.

Example Usage:

SL_CCMR5F_FailInfo failInfoCCMR5F;
retVal = SL_SelfTest_CCMR5F(CCMR5F_CPUCOMP_SELF_TEST, FALSE,
&failInfoCCMR5F);
while (TRUE == SL_SelfTest_CCMR5F(&faileInfoCCMR5F));
if (failInfoCCMR5F.stResult == ST_FAIL) {
// Self test failed.. for details of failure info read
failInfoCCMR5F.failInfo
}
Entry Mode:
Any Privilege Mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_CCMR5F

Note : This API is only valid when SL_SelfTest_CCMR5F is called in async mode(with bMode=FALSE)

boolean SL_SelfTest_Status_EFuse ( SL_EFuse_FailInfo * failInfoefuse )

Retrieves the status of the previous EFuse self-test execution.

Parameters
[in] | failInfo | - Pointer to structure that will be used to return the execution results. For details on structure member refer to documentation on SL_EFuse_FailInfo documentation.
[out] | None
Returns
TRUE if the self-test was completed. Else FALSE (self-test is still running).

Example Usage:

SL_SelfTest_Status_EFuse(&failInfo);
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_SelfTest_EFuse

ECC Self test has been enabled, check the results accordingly

boolean SL_SelfTest_Status_PBIST ( SL_PBIST_FailInfo * param1 )

Provides status information on the previous PBIST execution.

Description:
This API returns FALSE if the PBIST execution has not yet completed and if the PBIST execution is over the
the API updates the failinfo parameter with the relavant information on the status of the PBIST execution.This can be used
as apolling function after the call of the SL_SelfTest_PBIST API in order to get the status of the PBIST selftest.
Parameters
[out] | param1 | - Pointer to structure that is used to return the test status & results.
[in] | None
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

boolean retVal;
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
(PBIST_RAMGROUP_07_MIBSPI1 |
PBIST_RAMGROUP_08_MIBSPI3 |
PBIST_RAMGROUP_09_MIBSPI5 |
PBIST_RAMGROUP_10_VIM |
PBIST_RAMGROUP_11_MIBADC1 |
PBIST_RAMGROUP_18_MIBADC2),
PBISTALGO_MARCH13N_RED_2PORT);
while (TRUE != SL_SelfTest_Status_PBIST(&pbistStatus));
retVal = SL_SelfTest_PBIST_StopExec();
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_PBIST & SL_SelfTest_PBIST_StopExec
boolean SL_SelfTest_Status_PSCON ( SL_PSCON_FailInfo * param1 )

Returns the status for previous PSCON self-test execution
.

Note: Does not support status checking of error-forcing modes since these are synchronous in nature.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[out] param1 - Pointer to structure that is used to return the test status & results.
Note: contents of structure param1 is valid only for self-test.Not valid for Fault Injection mode.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

boolean retVal;
while (TRUE != SL_SelfTest_PBIST_ExecStatus(&pbistStatus));
retVal = SL_SelfTest_PBIST_StopExec();
if (TRUE == pbistStatus.pbistStatus) {
//test passed
} else {
//test failed
}
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_PSCON
boolean SL_SelfTest_Status_STC ( SL_STC_FailInfo * failInfostc )

Returns the status of previously executed CPU self-test via STC.

Parameters
[in] failinfostc - Pointer to SL_STC_FailInfo. For more details on the return values refer to
SL_STC_FailInfo structure documentation.
[out] None
Returns
TRUE - If the self test was completed, else FALSE (a failure occurred during self test).

Example Usage:

// Start if debugger not connected & reset type is not CPU or DEBUGGER
if ((RESET_TYPE_CPU != resetReason) && (RESET_TYPE_DEBUG != resetReason)) {
stcSelfTestConfig.stcClockDiv = 0; // STC Clock divider = 1
stcSelfTestConfig.intervalCount = 1; // One interval only
stcSelfTestConfig.restartInterval0 = TRUE; // Start from interval 0
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF; // Timeout counter
SL_SelfTest_STC(STC_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);
}
// If STC was executed, get STC self-test status
if (RESET_TYPE_CPU == resetReason) {
retVal = SL_SelfTest_Status_STC (&failInfoSTC);
}
Entry Mode:
Any Privilege Mode
Exit Mode:
SVC Mode
See also:
SL_SelfTest_STC
boolean SL_SelfTest_STC | ( | register SL_SelfTestType | testType,
 |  | register boolean | bMode,
 |  | register SL_STC_Config * | config
 | ) |  |

Executes CPU Logic Built-In Self Test using Self-Test Controller.

Description:
The Hercules family architecture supports the use of a hardware logic BIST (LBIST) engine self-test
controller (STC). This logic is used to provide a very high diagnostic coverage on the lockstep CPUs
at a transistor level. This logic utilizes the same design for test (DFT) structures inserted into
the device for rapid execution of high quality manufacturing tests, but with an internal test engine
rather than external automated test equipment (ATE).
This function triggers the LBIST using the user provided parameters, thus providing runtime diagnostics
with execution of test time slices per safety critical loop as well as comprehensive CPU test during
initialization.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] | testType | - Must be STC_RUN
[in] | bMode | - NOT USED
[in] | config | - Pointer to structure containing the configuration items. Refer to SL_STC_Config for details of configurable items.
Returns
FALSE - If the function failed to execute STC. Function DOES NOT RETURN if STC was started.

Note: At the end of the STC execution a CPU reset is issued by the STC controller. So the application startup must ensure that the STC is not-executed when reset type is RESET_TYPE_CPU & when the debugger is connected.

Example Usage:

// Start if debugger not connected & reset type is not CPU or DEBUGGER
if ((RESET_TYPE_CPU != resetReason) && (RESET_TYPE_DEBUG != resetReason)) {
stcSelfTestConfig.stcClockDiv = 0; // STC Clock divider = 1
stcSelfTestConfig.intervalCount = 1; // One interval only
stcSelfTestConfig.restartInterval0 = TRUE; // Start from interval 0
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF; // Timeout counter
SL_SelfTest_STC(STC_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);
}
// If STC was executed, get STC self-test status
if (RESET_TYPE_CPU == resetReason) {
retVal = SL_SelfTest_Status_STC (&failInfoSTC);
}
Entry Mode:
Any Privilege Mode
Exit Mode:
NA - (CPU Reset is issued at the end of STC execution)
See also:
SL_SelfTest_Status_STC
boolean SL_SelfTest_WaitCompletion_PBIST ( void )

Provides information regarding whether PBIST is active or not.

Parameters
[out] | None
[in] | Pointer | to structure that is used to return the test status & results.
Returns
TRUE if PBIST is running(wait for completion) FALSE if PBIST is not running

Example Usage:

boolean retVal;
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
(PBIST_RAMGROUP_07_MIBSPI1 |
PBIST_RAMGROUP_08_MIBSPI3 |
PBIST_RAMGROUP_09_MIBSPI5 |
PBIST_RAMGROUP_10_VIM |
PBIST_RAMGROUP_11_MIBADC1 |
PBIST_RAMGROUP_18_MIBADC2),
PBISTALGO_MARCH13N_RED_2PORT);
while (TRUE != SL_SelfTest_WaitCompletion_PBIST(&pbistStatus));
retVal = SL_SelfTest_Status_PBIST(pbistfailinfo);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
See also:
SL_SelfTest_PBIST
boolean SL_SelfTestL2L3Interconnect ( SL_SelfTestType testType )

It does the Fault injection on L2(Switched central resource) and L3(Peripheral central resource) interconnects.
Below is the flowchart for the SL_SelfTestL2L3Interconnect.

Please refer to _SL_SelfTest_Type for the values to be used for testType.

Parameters
[in] testType Indicates the type of fault injection to perform.
Returns
TRUE if function executed successfully else FALSE.

Example Usage:

//Trigger L2 interconnect error trap
SL_L2L3Interconnect_FI(L2INTERCONNECT_FAULT_INJECT);
Entry Mode:
Any privilege mode
Exit Mode:
Same as entry
#include <sl_api.h>
#include <sl_priv.h>
Generated on Fri Feb 6 2015 03:20:29 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: safety_library/source/sl_sys_pmu.h Source File

  • File List
  • Globals
  • safety_library
  • source
sl_sys_pmu.h
1
12 /* (c) Texas Instruments 2009-2013, All rights reserved. */
13
14 #ifndef _SL_PMU_H_
15 #define _SL_PMU_H_
16
17 #include "sl_sys_common.h"
18
19 /* USER CODE BEGIN (0) */
20 /* USER CODE END */
21
27 #define SL_PMUCOUNTER0 0x00000001U
28
34 #define SL_PMUCOUNTER1 0x00000002U
35
41 #define SL_PMUCOUNTER2 0x00000004U
42
48 #define SL_PMUCYCLE_COUNTER 0x80000000U
49
55 enum sl_pmuEvent
56 {
57 SL_PMU_INST_CACHE_MISS = 0x01U,
58 SL_PMU_DATA_CACHE_MISS = 0x03U,
59 SL_PMU_DATA_CACHE_ACCESS = 0x04U,
60 SL_PMU_DATA_READ_ARCH_EXECUTED = 0x06U,
61 SL_PMU_DATA_WRITE_ARCH_EXECUTED = 0x07U,
62 SL_PMU_INST_ARCH_EXECUTED = 0x08U,
63 SL_PMU_EXCEPTION_TAKEN = 0x09U,
64 SL_PMU_EXCEPTION_RETURN_ARCH_EXECUTED = 0x0AU,
65 SL_PMU_CHANGE_TO_CONTEXT_ID_EXECUTED = 0x0BU,
66 SL_PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED = 0x0CU,
67 SL_PMU_BRANCH_IMM_INST_ARCH_EXECUTED = 0x0DU,
68 SL_PMU_PROC_RETURN_ARCH_EXECUTED = 0x0EU,
69 SL_PMU_UNALIGNED_ACCESS_ARCH_EXECUTED = 0x0FU,
70 SL_PMU_BRANCH_MISSPREDICTED = 0x10U,
71 SL_PMU_CYCLE_COUNT = 0x11U,
72 SL_PMU_PREDICTABLE_BRANCHES = 0x12U,
73 SL_PMU_INST_BUFFER_STALL = 0x40U,
74 SL_PMU_DATA_DEPENDENCY_INST_STALL = 0x41U,
75 SL_PMU_DATA_CACHE_WRITE_BACK = 0x42U,
76 SL_PMU_EXT_MEMORY_REQUEST = 0x43U,
77 SL_PMU_LSU_BUSY_STALL = 0x44U,
78 SL_PMU_FORCED_DRAIN_OFSTORE_BUFFER = 0x45U,
79 SL_PMU_FIQ_DISABLED_CYCLE_COUNT = 0x46U,
80 SL_PMU_IRQ_DISABLED_CYCLE_COUNT = 0x47U,
81 SL_PMU_ETMEXTOUT_0 = 0x48U,
82 SL_PMU_ETMEXTOUT_1 = 0x49U,
83 SL_PMU_INST_CACHE_TAG_ECC_ERROR = 0x4AU,
84 SL_PMU_INST_CACHE_DATA_ECC_ERROR = 0x4BU,
85 SL_PMU_DATA_CACHE_TAG_ECC_ERROR = 0x4CU,
86 SL_PMU_DATA_CACHE_DATA_ECC_ERROR = 0x4DU,
87 SL_PMU_TCM_FATAL_ECC_ERROR_PREFETCH = 0x4EU,
88 SL_PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE = 0x4FU,
89 SL_PMU_STORE_BUFFER_MERGE = 0x50U,
90 SL_PMU_LSU_STALL_STORE_BUFFER_FULL = 0x51U,
91 SL_PMU_LSU_STALL_STORE_QUEUE_FULL = 0x52U,
92 SL_PMU_INTEGER_DIV_EXECUTED = 0x53U,
93 SL_PMU_STALL_INTEGER_DIV = 0x54U,
94 SL_PMU_PLD_INST_LINE_FILL = 0x55U,
95 SL_PMU_PLD_INST_NO_LINE_FILL = 0x56U,
96 SL_PMU_NON_CACHEABLE_ACCESS_AXI_MASTER = 0x57U,
97 SL_PMU_INST_CACHE_ACCESS = 0x58U,
98 SL_PMU_DOUBLE_DATA_CACHE_ISSUE = 0x59U,
99 SL_PMU_DUAL_ISSUE_CASE_A = 0x5AU,
100 SL_PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5BU,
101 SL_PMU_DUAL_ISSUE_OTHER = 0x5CU,
102 SL_PMU_DP_FLOAT_INST_EXCECUTED = 0x5DU,
103 SL_PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5EU,
104 SL_PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR = 0x60U,
105 SL_PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR = 0x61U,
106 SL_PMU_PROCESSOR_LIVE_LOCK = 0x62U,
107 SL_PMU_ATCM_MULTI_BIT_ECC_ERROR = 0x64U,
108 SL_PMU_B0TCM_MULTI_BIT_ECC_ERROR = 0x65U,
109 SL_PMU_B1TCM_MULTI_BIT_ECC_ERROR = 0x66U,
110 SL_PMU_ATCM_SINGLE_BIT_ECC_ERROR = 0x67U,
111 SL_PMU_B0TCM_SINGLE_BIT_ECC_ERROR = 0x68U,
112 SL_PMU_B1TCM_SINGLE_BIT_ECC_ERROR = 0x69U,
113 SL_PMU_TCM_COR_ECC_ERROR_LOAD_STORE = 0x6AU,
114 SL_PMU_TCM_COR_ECC_ERROR_PREFETCH = 0x6BU,
115 SL_PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE = 0x6CU,
116 SL_PMU_TCM_COR_ECC_ERROR_AXI_SLAVE = 0x6DU
117 };
118
122 void _sl_pmuInit_(void);
123
127 void _sl_pmuEnableCountersGlobal_(void);
128
132 void _sl_pmuDisableCountersGlobal_(void);
133
137 void _sl_pmuResetCycleCounter_(void);
138
142 void _sl_pmuResetEventCounters_(void);
143
147 void _sl_pmuResetCounters_(void);
148
153 void _sl_pmuStartCounters_(uint32 counters);
154
159 void _sl_pmuStopCounters_(uint32 counters);
160
166 void _sl_pmuSetCountEvent_(uint32 counter, uint32 event);
167
173 uint32 _sl_pmuGetCycleCount_(void);
174
181 uint32 _sl_pmuGetEventCount_(uint32 counter);
182
188 uint32 _sl_pmuGetOverflow_(void);
189
190
191 #endif /* _SL_PMU_H_ */
Generated on Fri Feb 6 2015 03:20:29 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- _ -

  • _SL_ADC_Pinstatus : sl_types.h
  • _SL_AutoInitRamId : sl_types.h
  • _SL_EFuse_Error : sl_types.h
  • _SL_Get_DataFault_Status() : sl_api.h
  • _sl_log_func_id : sl_log.h
  • _SL_ResetReason : sl_types.h
  • _SL_SelfTest_SRAM_RAD() : sl_priv.h
  • _SL_SelfTest_Type : sl_types.h


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- a -

  • ADC_PIN_GOOD : sl_types.h
  • ADC_PIN_OPEN : sl_types.h
  • ADC_PIN_SHORTED_TO_ADVREF_HIGH : sl_types.h
  • ADC_PIN_SHORTED_TO_ADVREF_LOW : sl_types.h
  • ADC_PIN_UNDETERMINED : sl_types.h


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- c -

  • CAN_ECC_TEST_MODE_1BIT : sl_types.h
  • CAN_ECC_TEST_MODE_1BIT_FAULT_INJECT : sl_types.h
  • CAN_ECC_TEST_MODE_2BIT : sl_types.h
  • CAN_ECC_TEST_MODE_2BIT_FAULT_INJECT : sl_types.h
  • CCMR4F_ERROR_FORCING_TEST : sl_types.h
  • CCMR4F_ERROR_FORCING_TEST_FAULT_INJECT : sl_types.h
  • CCMR4F_SELF_TEST : sl_types.h
  • CCMR4F_SELF_TEST_ERROR_FORCING : sl_types.h
  • CCMR5F_CPUCOMP_ERROR_FORCING_TEST : sl_types.h
  • CCMR5F_CPUCOMP_ERROR_FORCING_TEST_FAULT_INJECT : sl_types.h
  • CCMR5F_CPUCOMP_SELF_TEST : sl_types.h
  • CCMR5F_CPUCOMP_SELF_TEST_ERROR_FORCING : sl_types.h
  • CCMR5F_INMCOMP_ERROR_FORCING_TEST : sl_types.h
  • CCMR5F_INMCOMP_ERROR_FORCING_TEST_FAULT_INJECT : sl_types.h
  • CCMR5F_INMCOMP_SELF_TEST : sl_types.h
  • CCMR5F_INMCOMP_SELF_TEST_ERROR_FORCING : sl_types.h
  • CCMR5F_PDCOMP_ERROR_FORCING_TEST : sl_types.h
  • CCMR5F_PDCOMP_ERROR_FORCING_TEST_FAULT_INJECT : sl_types.h
  • CCMR5F_PDCOMP_SELF_TEST : sl_types.h
  • CCMR5F_PDCOMP_SELF_TEST_ERROR_FORCING : sl_types.h
  • CCMR5F_VIMCOMP_ERROR_FORCING_TEST : sl_types.h
  • CCMR5F_VIMCOMP_ERROR_FORCING_TEST_FAULT_INJECT : sl_types.h
  • CCMR5F_VIMCOMP_SELF_TEST : sl_types.h
  • CCMR5F_VIMCOMP_SELF_TEST_ERROR_FORCING : sl_types.h


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- d -

  • DMA_ECC_TEST_MODE_1BIT : sl_types.h
  • DMA_ECC_TEST_MODE_1BIT_FAULT_INJECT : sl_types.h
  • DMA_ECC_TEST_MODE_2BIT : sl_types.h
  • DMA_ECC_TEST_MODE_2BIT_FAULT_INJECT : sl_types.h


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- e -

  • EFUSE_ERROR_AUTOLOAD_1 : sl_types.h
  • EFUSE_ERROR_AUTOLOAD_2 : sl_types.h
  • EFUSE_ERROR_AUTOLOAD_2B_ERR : sl_types.h
  • EFUSE_ERROR_AUTOLOAD_INTRPTD : sl_types.h
  • EFUSE_ERROR_NONE : sl_types.h
  • EFUSE_ERROR_PROG_CTRL_ITER : sl_types.h
  • EFUSE_ERROR_PROG_W_D_ITER : sl_types.h
  • EFUSE_ERROR_PROG_W_PROTECT : sl_types.h
  • EFUSE_ERROR_RED_REP_ROW : sl_types.h
  • EFUSE_ERROR_TIMEOUT : sl_types.h
  • EFUSE_ERROR_UNPROG_BIT_SET : sl_types.h
  • EFUSE_SELF_TEST_AUTOLOAD : sl_types.h
  • EFUSE_SELF_TEST_ECC : sl_types.h
  • EFUSE_SELF_TEST_STUCK_AT_ZERO : sl_types.h
  • ERR_TYPE_ENTRY_CON : sl_log.h
  • ERR_TYPE_PARAM : sl_log.h
  • ESM_Application_Callback : sl_types.h
  • ESM_G1ERR_B0TCM_CORRERR : sl_types.h
  • ESM_G1ERR_B1TCM_CORRERR : sl_types.h
  • ESM_G1ERR_CAN1_ECC_SBERR : sl_types.h
  • ESM_G1ERR_CAN1_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_CAN2_ECC_SBERR : sl_types.h
  • ESM_G1ERR_CAN2_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_CAN3_ECC_SBERR : sl_types.h
  • ESM_G1ERR_CAN3_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_CAN4_ECC_SBERR : sl_types.h
  • ESM_G1ERR_CAN4_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_CCMR4_SELFTEST : sl_types.h
  • ESM_G1ERR_CCMR5_OPERATING_STATUS : sl_types.h
  • ESM_G1ERR_CCMR5_SELFTEST : sl_types.h
  • ESM_G1ERR_CLOCKMON_INTR : sl_types.h
  • ESM_G1ERR_DCC1_ERR : sl_types.h
  • ESM_G1ERR_DCC2_ERR : sl_types.h
  • ESM_G1ERR_DMA_ECC_SBERR : sl_types.h
  • ESM_G1ERR_DMA_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_EEPROM_CORRERR : sl_types.h
  • ESM_G1ERR_EEPROM_UNCORRERR : sl_types.h
  • ESM_G1ERR_EFUSE_ERR_OTHER : sl_types.h
  • ESM_G1ERR_EFUSE_SELTEST_ERR : sl_types.h
  • ESM_G1ERR_EPC_SERR : sl_types.h
  • ESM_G1ERR_FMC_CORR : sl_types.h
  • ESM_G1ERR_L2RAMW_CORRERR : sl_types.h
  • ESM_G1ERR_PLL1_SLIP : sl_types.h
  • ESM_G1ERR_PLL2_SLIP : sl_types.h
  • ESM_G1ERR_PSCON_COMPARE_ERR : sl_types.h
  • ESM_G1ERR_PSCON_SELTEST_ERR : sl_types.h
  • ESM_G1ERR_SPI1_ECC_SBERR : sl_types.h
  • ESM_G1ERR_SPI1_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_SPI2_ECC_SBERR : sl_types.h
  • ESM_G1ERR_SPI2_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_SPI3_ECC_SBERR : sl_types.h
  • ESM_G1ERR_SPI3_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_SPI4_ECC_SBERR : sl_types.h
  • ESM_G1ERR_SPI4_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_SPI5_ECC_SBERR : sl_types.h
  • ESM_G1ERR_SPI5_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_VIMRAM_PARITY : sl_types.h
  • ESM_G2ERR_B0TCM_ADDPAR : sl_types.h
  • ESM_G2ERR_B0TCM_UNCORR : sl_types.h
  • ESM_G2ERR_B1TCM_ADDPAR : sl_types.h
  • ESM_G2ERR_B1TCM_UNCORR : sl_types.h
  • ESM_G2ERR_CCMR4_COMP : sl_types.h
  • ESM_G2ERR_CCMR5_CPUCOMP_ERR : sl_types.h
  • ESM_G2ERR_CCMR5_INMCOMP_ERR : sl_types.h
  • ESM_G2ERR_CCMR5_PDCOMP_ERR : sl_types.h
  • ESM_G2ERR_CCMR5_VIMCOMP_ERR : sl_types.h
  • ESM_G2ERR_CR5_BUSERR : sl_types.h
  • ESM_G2ERR_EPC_UNCORR : sl_types.h
  • ESM_G2ERR_FLASH_LIVLCK : sl_types.h
  • ESM_G2ERR_FMC_UNCORR : sl_types.h
  • ESM_G2ERR_L2RAMW_UNCORR_B : sl_types.h
  • ESM_G2ERR_RTI_WWD_NMI : sl_types.h
  • ESM_G3ERR_B0TCM_ECC_UNCORR : sl_types.h
  • ESM_G3ERR_B1TCM_ECC_UNCORR : sl_types.h
  • ESM_G3ERR_EFUSE_AUTOLOAD_ERR : sl_types.h
  • ESM_G3ERR_FMC_UNCORR : sl_types.h
  • esmGroup1Handler() : sl_esm.c


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- f -

  • FEE_ECC_ADDR_TAG_REG_MODE : sl_types.h
  • FEE_ECC_DATA_CORR_MODE : sl_types.h
  • FEE_ECC_MALFUNCTION_MODE1 : sl_types.h
  • FEE_ECC_MALFUNCTION_MODE2 : sl_types.h
  • FEE_ECC_SYN_REPORT_MODE : sl_types.h
  • FEE_ECC_TEST_MODE_1BIT : sl_types.h
  • FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT : sl_types.h
  • FEE_ECC_TEST_MODE_2BIT : sl_types.h
  • FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT : sl_types.h
  • FLASH_ADDRESS_ECC_FAULT_INJECT : sl_types.h
  • FLASH_ADDRESS_ECC_SELF_TEST : sl_types.h
  • FLASH_ADDRESS_PARITY_FAULT_INJECT : sl_types.h
  • FLASH_ADDRESS_PARITY_SELF_TEST : sl_types.h
  • FLASH_ECC_ADDR_TAG_REG_MODE : sl_types.h
  • FLASH_ECC_TEST_MODE_1BIT : sl_types.h
  • FLASH_ECC_TEST_MODE_2BIT : sl_types.h
  • FLASH_ECC_TEST_MODE_2BIT_FAULT_INJECT : sl_types.h
  • FLASHECC_DEFAULT : sl_types.h
  • FLASHECC_E0FEN : sl_types.h
  • FLASHECC_EOCV : sl_types.h
  • FLASHECC_EPEN : sl_types.h
  • FLASHECC_EZCV : sl_types.h
  • FLASHECC_EZFEN : sl_types.h
  • FUNC_ENTRY_COND_CHECK_ENABLED : sl_config.h
  • FUNC_ID_ST_ADC : sl_log.h
  • FUNC_ID_ST_CAN : sl_log.h
  • FUNC_ID_ST_CCMR4F : sl_log.h
  • FUNC_ID_ST_CCMR4F_STATUS : sl_log.h
  • FUNC_ID_ST_CCMR5F : sl_log.h
  • FUNC_ID_ST_CCMR5F_STATUS : sl_log.h
  • FUNC_ID_ST_DMA : sl_log.h
  • FUNC_ID_ST_EFUSE : sl_log.h
  • FUNC_ID_ST_FLASH : sl_log.h
  • FUNC_ID_ST_L2L3INTERCONNECT : sl_log.h
  • FUNC_ID_ST_PBIST : sl_log.h
  • FUNC_ID_ST_PBIST_STATUS : sl_log.h
  • FUNC_ID_ST_PSCON : sl_log.h
  • FUNC_ID_ST_SPI : sl_log.h
  • FUNC_ID_ST_SRAM : sl_log.h
  • FUNC_ID_ST_STC : sl_log.h
  • FUNC_RESULT_LOG_ENABLED : sl_config.h
  • FUNCTION_PARAM_CHECK_ENABLED : sl_config.h
  • FUNCTION_PROFILING_ENABLED : sl_config.h


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- l -

  • LOG_ERROR_BUFFER_COUNT : sl_config.h
  • LOG_RESULT_BUFFER_COUNT : sl_config.h


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- m -

  • MIBSPI_ECC_TEST_MODE_1BIT : sl_types.h
  • MIBSPI_ECC_TEST_MODE_1BIT_FAULT_INJECT : sl_types.h
  • MIBSPI_ECC_TEST_MODE_2BIT : sl_types.h
  • MIBSPI_ECC_TEST_MODE_2BIT_FAULT_INJECT : sl_types.h


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- n -

  • NERROR_HOLD_DELAY : sl_config.h


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- p -

  • PBIST_EXECUTE : sl_types.h
  • PBIST_EXECUTE_OVERRIDE : sl_types.h
  • PBIST_RAMGROUP_01_PBIST_ROM : sl_types.h
  • PBIST_RAMGROUP_02_STC_ROM : sl_types.h
  • PBIST_RAMGROUP_03_DCAN1 : sl_types.h
  • PBIST_RAMGROUP_04_DCAN2 : sl_types.h
  • PBIST_RAMGROUP_05_DCAN3 : sl_types.h
  • PBIST_RAMGROUP_06_ESRAM1 : sl_types.h
  • PBIST_RAMGROUP_07_MIBSPI1 : sl_types.h
  • PBIST_RAMGROUP_08_MIBSPI3 : sl_types.h
  • PBIST_RAMGROUP_09_MIBSPI5 : sl_types.h
  • PBIST_RAMGROUP_10_VIM : sl_types.h
  • PBIST_RAMGROUP_11_MIBADC1 : sl_types.h
  • PBIST_RAMGROUP_12_DMA : sl_types.h
  • PBIST_RAMGROUP_13_N2HET1 : sl_types.h
  • PBIST_RAMGROUP_14_HETTU1 : sl_types.h
  • PBIST_RAMGROUP_15_RTP : sl_types.h
  • PBIST_RAMGROUP_16_FRAY : sl_types.h
  • PBIST_RAMGROUP_17_FRAY : sl_types.h
  • PBIST_RAMGROUP_18_MIBADC2 : sl_types.h
  • PBIST_RAMGROUP_19_N2HET2 : sl_types.h
  • PBIST_RAMGROUP_20_HETTU2 : sl_types.h
  • PBIST_RAMGROUP_21_ESRAM5 : sl_types.h
  • PBIST_RAMGROUP_22_ESRAM6 : sl_types.h
  • PBIST_RAMGROUP_23_ETHERNET1 : sl_types.h
  • PBIST_RAMGROUP_24_ETHERNET2 : sl_types.h
  • PBIST_RAMGROUP_25_ETHERNET3 : sl_types.h
  • PBIST_RAMGROUP_26_USB1 : sl_types.h
  • PBIST_RAMGROUP_27_USB2 : sl_types.h
  • PBIST_RAMGROUP_28_ESRAM8 : sl_types.h
  • PBIST_RAMGROUP_29_RSVD : sl_types.h
  • PBISTALGO_DOWN1A_RED_1PORT : sl_types.h
  • PBISTALGO_DOWN1A_RED_2PORT : sl_types.h
  • PBISTALGO_DTXN2_1PORT : sl_types.h
  • PBISTALGO_DTXN2_2PORT : sl_types.h
  • PBISTALGO_FLIP10_1PORT : sl_types.h
  • PBISTALGO_FLIP10_2PORT : sl_types.h
  • PBISTALGO_IDDQ2_1PORT : sl_types.h
  • PBISTALGO_IDDQ2_2PORT : sl_types.h
  • PBISTALGO_IDDQ_1PORT : sl_types.h
  • PBISTALGO_IDDQ_2PORT : sl_types.h
  • PBISTALGO_IDDQROWSTRIPE2_1PORT : sl_types.h
  • PBISTALGO_IDDQROWSTRIPE2_2PORT : sl_types.h
  • PBISTALGO_IDDQROWSTRIPE_1PORT : sl_types.h
  • PBISTALGO_IDDQROWSTRIPE_2PORT : sl_types.h
  • PBISTALGO_MAP_COLUMN_1PORT : sl_types.h
  • PBISTALGO_MAP_COLUMN_2PORT : sl_types.h
  • PBISTALGO_MAPCOLUMN_1PORT : sl_types.h
  • PBISTALGO_MAPCOLUMN_2PORT : sl_types.h
  • PBISTALGO_MARCH13N_1PORT : sl_types.h
  • PBISTALGO_MARCH13N_2PORT : sl_types.h
  • PBISTALGO_MARCH13N_RED_1PORT : sl_types.h
  • PBISTALGO_MARCH13N_RED_2PORT : sl_types.h
  • PBISTALGO_PMOS_OP_SLICE1_1PORT : sl_types.h
  • PBISTALGO_PMOS_OP_SLICE1_2PORT : sl_types.h
  • PBISTALGO_PMOS_OP_SLICE2_2PORT : sl_types.h
  • PBISTALGO_PMOS_OPEN_1PORT : sl_types.h
  • PBISTALGO_PMOS_OPEN_2PORT : sl_types.h
  • PBISTALGO_PRECHARGE_1PORT : sl_types.h
  • PBISTALGO_PRECHARGE_2PORT : sl_types.h
  • PBISTALGO_RETENTION2_1PORT : sl_types.h
  • PBISTALGO_RETENTION2_2PORT : sl_types.h
  • PBISTALGO_RETENTION_1PORT : sl_types.h
  • PBISTALGO_RETENTION_2PORT : sl_types.h
  • PBISTALGO_TRIPLE_READ_FAST_READ : sl_types.h
  • PBISTALGO_TRIPLE_READ_SLOW_READ : sl_types.h
  • PSCON_ERROR_FORCING : sl_types.h
  • PSCON_ERROR_FORCING_FAULT_INJECT : sl_types.h
  • PSCON_PMA_TEST : sl_types.h
  • PSCON_SELF_TEST : sl_types.h
  • PSCON_SELF_TEST_ERROR_FORCING : sl_types.h
  • PSCON_SELF_TEST_ERROR_FORCING_FAULT_INJECT : sl_types.h


SafeTI™ Diagnostic Library: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- r -

  • RAMTYPE_DCAN1_RAM : sl_types.h
  • RAMTYPE_DCAN2_RAM : sl_types.h
  • RAMTYPE_DCAN3_RAM : sl_types.h
  • RAMTYPE_DCAN4_RAM : sl_types.h
  • RAMTYPE_DMA_RAM : sl_types.h
  • RAMTYPE_FTU_RAM : sl_types.h
  • RAMTYPE_HET_TU1 : sl_types.h
  • RAMTYPE_HET_TU2 : sl_types.h
  • RAMTYPE_MIBADC1_RAM : sl_types.h
  • RAMTYPE_MIBADC2_RAM : sl_types.h
  • RAMTYPE_MIBSPI1_RAM : sl_types.h
  • RAMTYPE_MIBSPI2_RAM : sl_types.h
  • RAMTYPE_MIBSPI3_RAM : sl_types.h
  • RAMTYPE_MIBSPI4_RAM : sl_types.h
  • RAMTYPE_MIBSPI5_RAM : sl_types.h
  • RAMTYPE_NHET1 : sl_types.h
  • RAMTYPE_NHET2 : sl_types.h
  • RAMTYPE_RAM : sl_types.h
  • RAMTYPE_VIM : sl_types.h
  • RESET_TYPE_CPU : sl_types.h
  • RESET_TYPE_DEBUG : sl_types.h
  • RESET_TYPE_EXTRST : sl_types.h
  • RESET_TYPE_EXTRST_NERROR : sl_types.h
  • RESET_TYPE_ICEPICK : sl_types.h
  • RESET_TYPE_OSC_FAILURE : sl_types.h
  • RESET_TYPE_POWERON : sl_types.h
  • RESET_TYPE_SWRST : sl_types.h
  • RESET_TYPE_UNKNOWN : sl_types.h
  • RESET_TYPE_WATCHDOG : sl_types.h


SafeTI™ Diagnostic Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • c
  • d
  • e
  • f
  • l
  • m
  • n
  • p
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- s -

  • SL_adcCalibration() : sl_selftest.c , sl_api.h
  • SL_Clear_nERROR() : sl_api.h
  • SL_CRC_Calculate() : sl_api.h
  • SL_ESM_Init() : sl_esm.c , sl_api.h
  • SL_ESM_nERROR_Active() : sl_api.h , sl_esm.c
  • SL_Init_ECCFlash() : sl_api.h
  • SL_Init_ECCTCMRAM() : sl_api.h
  • SL_Init_Memory() : sl_api.h
  • SL_Init_R4Registers() : sl_api.h
  • SL_Init_R5Registers() : sl_api.h
  • SL_Init_ResetReason() : sl_api.h
  • SL_Init_ResetReason_XInfo() : sl_api.h
  • SL_Init_StackPointers() : sl_api.h
  • SL_Log_Error() : sl_log.h
  • SL_SelfTest_ADC() : sl_selftest.c , sl_api.h
  • SL_SelfTest_CAN() : sl_selftest.c , sl_api.h
  • SL_SelfTest_CCMR4F() : sl_selftest.c , sl_api.h
  • SL_SelfTest_CCMR5F() : sl_selftest.c , sl_api.h
  • SL_SelfTest_DMA() : sl_selftest.c , sl_api.h
  • SL_SelfTest_EFuse() : sl_selftest.c , sl_api.h
  • SL_SelfTest_FEE() : sl_selftest.c , sl_api.h
  • SL_SelfTest_Flash() : sl_selftest.c , sl_api.h
  • SL_SelfTest_MibSPI() : sl_selftest.c , sl_api.h
  • SL_SelfTest_PBIST() : sl_api.h
  • SL_SelfTest_PBIST_StopExec() : sl_selftest.c , sl_api.h
  • SL_SelfTest_PSCON() : sl_selftest.c , sl_api.h
  • SL_SelfTest_SRAM() : sl_selftest.c , sl_api.h
  • SL_SelfTest_Status_CCMR4F() : sl_selftest.c , sl_api.h
  • SL_SelfTest_Status_CCMR5F() : sl_selftest.c , sl_api.h
  • SL_SelfTest_Status_EFuse() : sl_selftest.c , sl_api.h
  • SL_SelfTest_Status_PBIST() : sl_selftest.c , sl_api.h
  • SL_SelfTest_Status_PSCON() : sl_selftest.c , sl_api.h
  • SL_SelfTest_Status_STC() : sl_selftest.c , sl_api.h
  • SL_SelfTest_STC() : sl_selftest.c , sl_api.h
  • SL_SelfTest_WaitCompletion_PBIST() : sl_selftest.c , sl_api.h
  • SL_SelfTestL2L3Interconnect() : sl_selftest.c , sl_api.h
  • SL_Set_nERROR() : sl_api.h
  • SL_SW_Reset() : sl_api.h
  • SRAM_ECC_1BIT_FAULT_INJECTION : sl_types.h
  • SRAM_ECC_2BIT_FAULT_INJECT : sl_types.h
  • SRAM_ECC_ERROR_FORCING_1BIT : sl_types.h
  • SRAM_ECC_ERROR_FORCING_2BIT : sl_types.h
  • SRAM_ECC_ERROR_PROFILING : sl_types.h
  • SRAM_ECC_ERROR_PROFILING_FAULT_INJECT : sl_types.h
  • SRAM_END : sl_config.h
  • SRAM_PAR_ADDR_CTRL_SELF_TEST : sl_types.h
  • SRAM_RADECODE_DIAGNOSTICS : sl_types.h
  • SRAM_START : sl_config.h
  • STACK_SIZE_MODE_ABT : sl_config.h
  • STACK_SIZE_MODE_FIQ : sl_config.h
  • STACK_SIZE_MODE_IRQ : sl_config.h
  • STACK_SIZE_MODE_SVC : sl_config.h
  • STACK_SIZE_MODE_SYS : sl_config.h
  • STACK_SIZE_MODE_UND : sl_config.h
  • STC1_COMPARE_SELFCHECK : sl_types.h
  • STC1_RUN : sl_types.h
  • STC_COMPARE_SELFCHECK : sl_types.h
  • STC_RUN : sl_types.h


SafeTI™ Diagnostic Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • c
  • d
  • e
  • f
  • l
  • m
  • n
  • p
  • r
  • s
  • t
Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- t -

  • TESTTYPE_MAX : sl_types.h
  • TESTTYPE_MIN : sl_types.h


SafeTI™ Diagnostic Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • e
  • s

- _ -

  • _SL_Get_DataFault_Status() : sl_api.h
  • _SL_SelfTest_SRAM_RAD() : sl_priv.h

- e -

  • esmGroup1Handler() : sl_esm.c

- s -

  • SL_adcCalibration() : sl_selftest.c , sl_api.h
  • SL_Clear_nERROR() : sl_api.h
  • SL_CRC_Calculate() : sl_api.h
  • SL_ESM_Init() : sl_esm.c , sl_api.h
  • SL_ESM_nERROR_Active() : sl_api.h , sl_esm.c
  • SL_Init_ECCFlash() : sl_api.h
  • SL_Init_ECCTCMRAM() : sl_api.h
  • SL_Init_Memory() : sl_api.h
  • SL_Init_R4Registers() : sl_api.h
  • SL_Init_R5Registers() : sl_api.h
  • SL_Init_ResetReason() : sl_api.h
  • SL_Init_ResetReason_XInfo() : sl_api.h
  • SL_Init_StackPointers() : sl_api.h
  • SL_Log_Error() : sl_log.h
  • SL_SelfTest_ADC() : sl_selftest.c , sl_api.h
  • SL_SelfTest_CAN() : sl_selftest.c , sl_api.h
  • SL_SelfTest_CCMR4F() : sl_selftest.c , sl_api.h
  • SL_SelfTest_CCMR5F() : sl_selftest.c , sl_api.h
  • SL_SelfTest_DMA() : sl_selftest.c , sl_api.h
  • SL_SelfTest_EFuse() : sl_selftest.c , sl_api.h
  • SL_SelfTest_FEE() : sl_selftest.c , sl_api.h
  • SL_SelfTest_Flash() : sl_selftest.c , sl_api.h
  • SL_SelfTest_MibSPI() : sl_selftest.c , sl_api.h
  • SL_SelfTest_PBIST() : sl_api.h
  • SL_SelfTest_PBIST_StopExec() : sl_selftest.c , sl_api.h
  • SL_SelfTest_PSCON() : sl_api.h , sl_selftest.c
  • SL_SelfTest_SRAM() : sl_selftest.c , sl_api.h
  • SL_SelfTest_Status_CCMR4F() : sl_selftest.c , sl_api.h
  • SL_SelfTest_Status_CCMR5F() : sl_api.h , sl_selftest.c
  • SL_SelfTest_Status_EFuse() : sl_api.h , sl_selftest.c
  • SL_SelfTest_Status_PBIST() : sl_api.h , sl_selftest.c
  • SL_SelfTest_Status_PSCON() : sl_api.h , sl_selftest.c
  • SL_SelfTest_Status_STC() : sl_api.h , sl_selftest.c
  • SL_SelfTest_STC() : sl_selftest.c , sl_api.h
  • SL_SelfTest_WaitCompletion_PBIST() : sl_selftest.c , sl_api.h
  • SL_SelfTestL2L3Interconnect() : sl_api.h , sl_selftest.c
  • SL_Set_nERROR() : sl_api.h
  • SL_SW_Reset() : sl_api.h


SafeTI™ Diagnostic Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • ESM_Application_Callback : sl_types.h


SafeTI™ Diagnostic Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _SL_ADC_Pinstatus : sl_types.h
  • _SL_AutoInitRamId : sl_types.h
  • _SL_EFuse_Error : sl_types.h
  • _sl_log_func_id : sl_log.h
  • _SL_ResetReason : sl_types.h
  • _SL_SelfTest_Type : sl_types.h


SafeTI™ Diagnostic Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • a
  • c
  • d
  • e
  • f
  • m
  • p
  • r
  • s

- a -

  • ADC_PIN_GOOD : sl_types.h
  • ADC_PIN_OPEN : sl_types.h
  • ADC_PIN_SHORTED_TO_ADVREF_HIGH : sl_types.h
  • ADC_PIN_SHORTED_TO_ADVREF_LOW : sl_types.h
  • ADC_PIN_UNDETERMINED : sl_types.h

- c -

  • CAN_ECC_TEST_MODE_1BIT : sl_types.h
  • CAN_ECC_TEST_MODE_1BIT_FAULT_INJECT : sl_types.h
  • CAN_ECC_TEST_MODE_2BIT : sl_types.h
  • CAN_ECC_TEST_MODE_2BIT_FAULT_INJECT : sl_types.h
  • CCMR4F_ERROR_FORCING_TEST : sl_types.h
  • CCMR4F_ERROR_FORCING_TEST_FAULT_INJECT : sl_types.h
  • CCMR4F_SELF_TEST : sl_types.h
  • CCMR4F_SELF_TEST_ERROR_FORCING : sl_types.h
  • CCMR5F_CPUCOMP_ERROR_FORCING_TEST : sl_types.h
  • CCMR5F_CPUCOMP_ERROR_FORCING_TEST_FAULT_INJECT : sl_types.h
  • CCMR5F_CPUCOMP_SELF_TEST : sl_types.h
  • CCMR5F_CPUCOMP_SELF_TEST_ERROR_FORCING : sl_types.h
  • CCMR5F_INMCOMP_ERROR_FORCING_TEST : sl_types.h
  • CCMR5F_INMCOMP_ERROR_FORCING_TEST_FAULT_INJECT : sl_types.h
  • CCMR5F_INMCOMP_SELF_TEST : sl_types.h
  • CCMR5F_INMCOMP_SELF_TEST_ERROR_FORCING : sl_types.h
  • CCMR5F_PDCOMP_ERROR_FORCING_TEST : sl_types.h
  • CCMR5F_PDCOMP_ERROR_FORCING_TEST_FAULT_INJECT : sl_types.h
  • CCMR5F_PDCOMP_SELF_TEST : sl_types.h
  • CCMR5F_PDCOMP_SELF_TEST_ERROR_FORCING : sl_types.h
  • CCMR5F_VIMCOMP_ERROR_FORCING_TEST : sl_types.h
  • CCMR5F_VIMCOMP_ERROR_FORCING_TEST_FAULT_INJECT : sl_types.h
  • CCMR5F_VIMCOMP_SELF_TEST : sl_types.h
  • CCMR5F_VIMCOMP_SELF_TEST_ERROR_FORCING : sl_types.h

- d -

  • DMA_ECC_TEST_MODE_1BIT : sl_types.h
  • DMA_ECC_TEST_MODE_1BIT_FAULT_INJECT : sl_types.h
  • DMA_ECC_TEST_MODE_2BIT : sl_types.h
  • DMA_ECC_TEST_MODE_2BIT_FAULT_INJECT : sl_types.h

- e -

  • EFUSE_ERROR_AUTOLOAD_1 : sl_types.h
  • EFUSE_ERROR_AUTOLOAD_2 : sl_types.h
  • EFUSE_ERROR_AUTOLOAD_2B_ERR : sl_types.h
  • EFUSE_ERROR_AUTOLOAD_INTRPTD : sl_types.h
  • EFUSE_ERROR_NONE : sl_types.h
  • EFUSE_ERROR_PROG_CTRL_ITER : sl_types.h
  • EFUSE_ERROR_PROG_W_D_ITER : sl_types.h
  • EFUSE_ERROR_PROG_W_PROTECT : sl_types.h
  • EFUSE_ERROR_RED_REP_ROW : sl_types.h
  • EFUSE_ERROR_TIMEOUT : sl_types.h
  • EFUSE_ERROR_UNPROG_BIT_SET : sl_types.h
  • EFUSE_SELF_TEST_AUTOLOAD : sl_types.h
  • EFUSE_SELF_TEST_ECC : sl_types.h
  • EFUSE_SELF_TEST_STUCK_AT_ZERO : sl_types.h

- f -

  • FEE_ECC_ADDR_TAG_REG_MODE : sl_types.h
  • FEE_ECC_DATA_CORR_MODE : sl_types.h
  • FEE_ECC_MALFUNCTION_MODE1 : sl_types.h
  • FEE_ECC_MALFUNCTION_MODE2 : sl_types.h
  • FEE_ECC_SYN_REPORT_MODE : sl_types.h
  • FEE_ECC_TEST_MODE_1BIT : sl_types.h
  • FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT : sl_types.h
  • FEE_ECC_TEST_MODE_2BIT : sl_types.h
  • FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT : sl_types.h
  • FLASH_ADDRESS_ECC_FAULT_INJECT : sl_types.h
  • FLASH_ADDRESS_ECC_SELF_TEST : sl_types.h
  • FLASH_ADDRESS_PARITY_FAULT_INJECT : sl_types.h
  • FLASH_ADDRESS_PARITY_SELF_TEST : sl_types.h
  • FLASH_ECC_ADDR_TAG_REG_MODE : sl_types.h
  • FLASH_ECC_TEST_MODE_1BIT : sl_types.h
  • FLASH_ECC_TEST_MODE_2BIT : sl_types.h
  • FLASH_ECC_TEST_MODE_2BIT_FAULT_INJECT : sl_types.h
  • FUNC_ID_ST_ADC : sl_log.h
  • FUNC_ID_ST_CAN : sl_log.h
  • FUNC_ID_ST_CCMR4F : sl_log.h
  • FUNC_ID_ST_CCMR4F_STATUS : sl_log.h
  • FUNC_ID_ST_CCMR5F : sl_log.h
  • FUNC_ID_ST_CCMR5F_STATUS : sl_log.h
  • FUNC_ID_ST_DMA : sl_log.h
  • FUNC_ID_ST_EFUSE : sl_log.h
  • FUNC_ID_ST_FLASH : sl_log.h
  • FUNC_ID_ST_L2L3INTERCONNECT : sl_log.h
  • FUNC_ID_ST_PBIST : sl_log.h
  • FUNC_ID_ST_PBIST_STATUS : sl_log.h
  • FUNC_ID_ST_PSCON : sl_log.h
  • FUNC_ID_ST_SPI : sl_log.h
  • FUNC_ID_ST_SRAM : sl_log.h
  • FUNC_ID_ST_STC : sl_log.h

- m -

  • MIBSPI_ECC_TEST_MODE_1BIT : sl_types.h
  • MIBSPI_ECC_TEST_MODE_1BIT_FAULT_INJECT : sl_types.h
  • MIBSPI_ECC_TEST_MODE_2BIT : sl_types.h
  • MIBSPI_ECC_TEST_MODE_2BIT_FAULT_INJECT : sl_types.h

- p -

  • PBIST_EXECUTE : sl_types.h
  • PBIST_EXECUTE_OVERRIDE : sl_types.h
  • PSCON_ERROR_FORCING : sl_types.h
  • PSCON_ERROR_FORCING_FAULT_INJECT : sl_types.h
  • PSCON_PMA_TEST : sl_types.h
  • PSCON_SELF_TEST : sl_types.h
  • PSCON_SELF_TEST_ERROR_FORCING : sl_types.h
  • PSCON_SELF_TEST_ERROR_FORCING_FAULT_INJECT : sl_types.h

- r -

  • RAMTYPE_DCAN1_RAM : sl_types.h
  • RAMTYPE_DCAN2_RAM : sl_types.h
  • RAMTYPE_DCAN3_RAM : sl_types.h
  • RAMTYPE_DCAN4_RAM : sl_types.h
  • RAMTYPE_DMA_RAM : sl_types.h
  • RAMTYPE_FTU_RAM : sl_types.h
  • RAMTYPE_HET_TU1 : sl_types.h
  • RAMTYPE_HET_TU2 : sl_types.h
  • RAMTYPE_MIBADC1_RAM : sl_types.h
  • RAMTYPE_MIBADC2_RAM : sl_types.h
  • RAMTYPE_MIBSPI1_RAM : sl_types.h
  • RAMTYPE_MIBSPI2_RAM : sl_types.h
  • RAMTYPE_MIBSPI3_RAM : sl_types.h
  • RAMTYPE_MIBSPI4_RAM : sl_types.h
  • RAMTYPE_MIBSPI5_RAM : sl_types.h
  • RAMTYPE_NHET1 : sl_types.h
  • RAMTYPE_NHET2 : sl_types.h
  • RAMTYPE_RAM : sl_types.h
  • RAMTYPE_VIM : sl_types.h
  • RESET_TYPE_CPU : sl_types.h
  • RESET_TYPE_DEBUG : sl_types.h
  • RESET_TYPE_EXTRST : sl_types.h
  • RESET_TYPE_EXTRST_NERROR : sl_types.h
  • RESET_TYPE_ICEPICK : sl_types.h
  • RESET_TYPE_OSC_FAILURE : sl_types.h
  • RESET_TYPE_POWERON : sl_types.h
  • RESET_TYPE_SWRST : sl_types.h
  • RESET_TYPE_UNKNOWN : sl_types.h
  • RESET_TYPE_WATCHDOG : sl_types.h

- s -

  • SRAM_ECC_1BIT_FAULT_INJECTION : sl_types.h
  • SRAM_ECC_2BIT_FAULT_INJECT : sl_types.h
  • SRAM_ECC_ERROR_FORCING_1BIT : sl_types.h
  • SRAM_ECC_ERROR_FORCING_2BIT : sl_types.h
  • SRAM_ECC_ERROR_PROFILING : sl_types.h
  • SRAM_ECC_ERROR_PROFILING_FAULT_INJECT : sl_types.h
  • SRAM_PAR_ADDR_CTRL_SELF_TEST : sl_types.h
  • SRAM_RADECODE_DIAGNOSTICS : sl_types.h
  • STC1_COMPARE_SELFCHECK : sl_types.h
  • STC1_RUN : sl_types.h
  • STC_COMPARE_SELFCHECK : sl_types.h
  • STC_RUN : sl_types.h


SafeTI™ Diagnostic Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • e
  • f
  • l
  • n
  • p
  • s
  • t

- e -

  • ERR_TYPE_ENTRY_CON : sl_log.h
  • ERR_TYPE_PARAM : sl_log.h
  • ESM_G1ERR_B0TCM_CORRERR : sl_types.h
  • ESM_G1ERR_B1TCM_CORRERR : sl_types.h
  • ESM_G1ERR_CAN1_ECC_SBERR : sl_types.h
  • ESM_G1ERR_CAN1_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_CAN2_ECC_SBERR : sl_types.h
  • ESM_G1ERR_CAN2_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_CAN3_ECC_SBERR : sl_types.h
  • ESM_G1ERR_CAN3_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_CAN4_ECC_SBERR : sl_types.h
  • ESM_G1ERR_CAN4_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_CCMR4_SELFTEST : sl_types.h
  • ESM_G1ERR_CCMR5_OPERATING_STATUS : sl_types.h
  • ESM_G1ERR_CCMR5_SELFTEST : sl_types.h
  • ESM_G1ERR_CLOCKMON_INTR : sl_types.h
  • ESM_G1ERR_DCC1_ERR : sl_types.h
  • ESM_G1ERR_DCC2_ERR : sl_types.h
  • ESM_G1ERR_DMA_ECC_SBERR : sl_types.h
  • ESM_G1ERR_DMA_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_EEPROM_CORRERR : sl_types.h
  • ESM_G1ERR_EEPROM_UNCORRERR : sl_types.h
  • ESM_G1ERR_EFUSE_ERR_OTHER : sl_types.h
  • ESM_G1ERR_EFUSE_SELTEST_ERR : sl_types.h
  • ESM_G1ERR_EPC_SERR : sl_types.h
  • ESM_G1ERR_FMC_CORR : sl_types.h
  • ESM_G1ERR_L2RAMW_CORRERR : sl_types.h
  • ESM_G1ERR_PLL1_SLIP : sl_types.h
  • ESM_G1ERR_PLL2_SLIP : sl_types.h
  • ESM_G1ERR_PSCON_COMPARE_ERR : sl_types.h
  • ESM_G1ERR_PSCON_SELTEST_ERR : sl_types.h
  • ESM_G1ERR_SPI1_ECC_SBERR : sl_types.h
  • ESM_G1ERR_SPI1_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_SPI2_ECC_SBERR : sl_types.h
  • ESM_G1ERR_SPI2_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_SPI3_ECC_SBERR : sl_types.h
  • ESM_G1ERR_SPI3_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_SPI4_ECC_SBERR : sl_types.h
  • ESM_G1ERR_SPI4_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_SPI5_ECC_SBERR : sl_types.h
  • ESM_G1ERR_SPI5_ECC_UNCORR : sl_types.h
  • ESM_G1ERR_VIMRAM_PARITY : sl_types.h
  • ESM_G2ERR_B0TCM_ADDPAR : sl_types.h
  • ESM_G2ERR_B0TCM_UNCORR : sl_types.h
  • ESM_G2ERR_B1TCM_ADDPAR : sl_types.h
  • ESM_G2ERR_B1TCM_UNCORR : sl_types.h
  • ESM_G2ERR_CCMR4_COMP : sl_types.h
  • ESM_G2ERR_CCMR5_CPUCOMP_ERR : sl_types.h
  • ESM_G2ERR_CCMR5_INMCOMP_ERR : sl_types.h
  • ESM_G2ERR_CCMR5_PDCOMP_ERR : sl_types.h
  • ESM_G2ERR_CCMR5_VIMCOMP_ERR : sl_types.h
  • ESM_G2ERR_CR5_BUSERR : sl_types.h
  • ESM_G2ERR_EPC_UNCORR : sl_types.h
  • ESM_G2ERR_FLASH_LIVLCK : sl_types.h
  • ESM_G2ERR_FMC_UNCORR : sl_types.h
  • ESM_G2ERR_L2RAMW_UNCORR_B : sl_types.h
  • ESM_G2ERR_RTI_WWD_NMI : sl_types.h
  • ESM_G3ERR_B0TCM_ECC_UNCORR : sl_types.h
  • ESM_G3ERR_B1TCM_ECC_UNCORR : sl_types.h
  • ESM_G3ERR_EFUSE_AUTOLOAD_ERR : sl_types.h
  • ESM_G3ERR_FMC_UNCORR : sl_types.h

- f -

  • FLASHECC_DEFAULT : sl_types.h
  • FLASHECC_E0FEN : sl_types.h
  • FLASHECC_EOCV : sl_types.h
  • FLASHECC_EPEN : sl_types.h
  • FLASHECC_EZCV : sl_types.h
  • FLASHECC_EZFEN : sl_types.h
  • FUNC_ENTRY_COND_CHECK_ENABLED : sl_config.h
  • FUNC_RESULT_LOG_ENABLED : sl_config.h
  • FUNCTION_PARAM_CHECK_ENABLED : sl_config.h
  • FUNCTION_PROFILING_ENABLED : sl_config.h

- l -

  • LOG_ERROR_BUFFER_COUNT : sl_config.h
  • LOG_RESULT_BUFFER_COUNT : sl_config.h

- n -

  • NERROR_HOLD_DELAY : sl_config.h

- p -

  • PBIST_RAMGROUP_01_PBIST_ROM : sl_types.h
  • PBIST_RAMGROUP_02_STC_ROM : sl_types.h
  • PBIST_RAMGROUP_03_DCAN1 : sl_types.h
  • PBIST_RAMGROUP_04_DCAN2 : sl_types.h
  • PBIST_RAMGROUP_05_DCAN3 : sl_types.h
  • PBIST_RAMGROUP_06_ESRAM1 : sl_types.h
  • PBIST_RAMGROUP_07_MIBSPI1 : sl_types.h
  • PBIST_RAMGROUP_08_MIBSPI3 : sl_types.h
  • PBIST_RAMGROUP_09_MIBSPI5 : sl_types.h
  • PBIST_RAMGROUP_10_VIM : sl_types.h
  • PBIST_RAMGROUP_11_MIBADC1 : sl_types.h
  • PBIST_RAMGROUP_12_DMA : sl_types.h
  • PBIST_RAMGROUP_13_N2HET1 : sl_types.h
  • PBIST_RAMGROUP_14_HETTU1 : sl_types.h
  • PBIST_RAMGROUP_15_RTP : sl_types.h
  • PBIST_RAMGROUP_16_FRAY : sl_types.h
  • PBIST_RAMGROUP_17_FRAY : sl_types.h
  • PBIST_RAMGROUP_18_MIBADC2 : sl_types.h
  • PBIST_RAMGROUP_19_N2HET2 : sl_types.h
  • PBIST_RAMGROUP_20_HETTU2 : sl_types.h
  • PBIST_RAMGROUP_21_ESRAM5 : sl_types.h
  • PBIST_RAMGROUP_22_ESRAM6 : sl_types.h
  • PBIST_RAMGROUP_23_ETHERNET1 : sl_types.h
  • PBIST_RAMGROUP_24_ETHERNET2 : sl_types.h
  • PBIST_RAMGROUP_25_ETHERNET3 : sl_types.h
  • PBIST_RAMGROUP_26_USB1 : sl_types.h
  • PBIST_RAMGROUP_27_USB2 : sl_types.h
  • PBIST_RAMGROUP_28_ESRAM8 : sl_types.h
  • PBIST_RAMGROUP_29_RSVD : sl_types.h
  • PBISTALGO_DOWN1A_RED_1PORT : sl_types.h
  • PBISTALGO_DOWN1A_RED_2PORT : sl_types.h
  • PBISTALGO_DTXN2_1PORT : sl_types.h
  • PBISTALGO_DTXN2_2PORT : sl_types.h
  • PBISTALGO_FLIP10_1PORT : sl_types.h
  • PBISTALGO_FLIP10_2PORT : sl_types.h
  • PBISTALGO_IDDQ2_1PORT : sl_types.h
  • PBISTALGO_IDDQ2_2PORT : sl_types.h
  • PBISTALGO_IDDQ_1PORT : sl_types.h
  • PBISTALGO_IDDQ_2PORT : sl_types.h
  • PBISTALGO_IDDQROWSTRIPE2_1PORT : sl_types.h
  • PBISTALGO_IDDQROWSTRIPE2_2PORT : sl_types.h
  • PBISTALGO_IDDQROWSTRIPE_1PORT : sl_types.h
  • PBISTALGO_IDDQROWSTRIPE_2PORT : sl_types.h
  • PBISTALGO_MAP_COLUMN_1PORT : sl_types.h
  • PBISTALGO_MAP_COLUMN_2PORT : sl_types.h
  • PBISTALGO_MAPCOLUMN_1PORT : sl_types.h
  • PBISTALGO_MAPCOLUMN_2PORT : sl_types.h
  • PBISTALGO_MARCH13N_1PORT : sl_types.h
  • PBISTALGO_MARCH13N_2PORT : sl_types.h
  • PBISTALGO_MARCH13N_RED_1PORT : sl_types.h
  • PBISTALGO_MARCH13N_RED_2PORT : sl_types.h
  • PBISTALGO_PMOS_OP_SLICE1_1PORT : sl_types.h
  • PBISTALGO_PMOS_OP_SLICE1_2PORT : sl_types.h
  • PBISTALGO_PMOS_OP_SLICE2_2PORT : sl_types.h
  • PBISTALGO_PMOS_OPEN_1PORT : sl_types.h
  • PBISTALGO_PMOS_OPEN_2PORT : sl_types.h
  • PBISTALGO_PRECHARGE_1PORT : sl_types.h
  • PBISTALGO_PRECHARGE_2PORT : sl_types.h
  • PBISTALGO_RETENTION2_1PORT : sl_types.h
  • PBISTALGO_RETENTION2_2PORT : sl_types.h
  • PBISTALGO_RETENTION_1PORT : sl_types.h
  • PBISTALGO_RETENTION_2PORT : sl_types.h
  • PBISTALGO_TRIPLE_READ_FAST_READ : sl_types.h
  • PBISTALGO_TRIPLE_READ_SLOW_READ : sl_types.h

- s -

  • SRAM_END : sl_config.h
  • SRAM_START : sl_config.h
  • STACK_SIZE_MODE_ABT : sl_config.h
  • STACK_SIZE_MODE_FIQ : sl_config.h
  • STACK_SIZE_MODE_IRQ : sl_config.h
  • STACK_SIZE_MODE_SVC : sl_config.h
  • STACK_SIZE_MODE_SYS : sl_config.h
  • STACK_SIZE_MODE_UND : sl_config.h

- t -

  • TESTTYPE_MAX : sl_types.h
  • TESTTYPE_MIN : sl_types.h


SafeTI™ Diagnostic Library: Related Pages

Related Pages
Here is a list of all related documentation pages:
Configuration items
Build
References
Safety manual to API mapping
Safety manual to API mapping: TMS570LC43x/RM57Lx devices


SafeTI™ Diagnostic Library: safety_library/include/sl_api.h Source File

  • File List
  • Globals
  • safety_library
  • include
sl_api.h
Go to the documentation of this file.
1 /*******************************************************************************
2 **+--------------------------------------------------------------------------+**
3 **| |**
4 **| Copyright (c) 2012 Texas Instruments Incorporated |**
5 **| ALL RIGHTS RESERVED |**
6 **| |**
7 **| Permission is hereby granted to licensees of Texas Instruments |**
8 **| Incorporated (TI) products to use this computer program for the sole |**
9 **| purpose of implementing a licensee product based on TI products. |**
10 **| No other rights to reproduce, use, or disseminate this computer |**
11 **| program, whether in part or in whole, are granted. |**
12 **| |**
13 **| TI makes no representation or warranties with respect to the |**
14 **| performance of this computer program, and specifically disclaims |**
15 **| any responsibility for any damages, special or consequential, |**
16 **| connected with the use of this program. |**
17 **| |**
18 **+--------------------------------------------------------------------------+**
19 *******************************************************************************/
32 #ifndef __SL_API_H__
33 #define __SL_API_H__
34
37 #include <sl_types.h>
38 #include <sl_config.h>
39 #include <sl_log.h>
40 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
41 #include <reg_bitdefn_ccmr4f.h>
42 #endif
43 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
44 #include <reg_bitdefn_ccmr5f.h>
45 #endif
46
47 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
48 #include <reg_bitdefn_dcc.h>
49 #endif
50 #include <reg_bitdefn_efc.h>
51 #include <reg_bitdefn_esm.h>
52 #include <reg_bitdefn_f021flash.h>
53 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
54 #include <reg_bitdefn_iomm.h>
55 #endif
56 #include <reg_bitdefn_pbist.h>
57
58 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_)
59 #include <reg_bitdefn_pmm.h>
60 #endif
61
62 #include <reg_bitdefn_rti.h>
63 #include <reg_bitdefn_stc.h>
64 #include <reg_bitdefn_system.h>
65
66 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
67 #include <reg_bitdefn_tcmram.h>
68 #endif
69
70 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
71 #include <reg_bitdefn_l2ramw.h>
72 #include <reg_bitdefn_dma.h>
73 #include <reg_bitdefn_can.h>
74 #include <reg_bitdefn_mibspi.h>
75 #include <reg_bitdefn_epc.h>
76 #endif
77
78 #include <reg_bitdefn_vim.h>
79 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
80 #include <reg_bitdefn_adc.h>
81 #endif
82
84 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
85
121 void SL_Init_R4Registers (void);
122 #endif
123 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
124
160 void SL_Init_R5Registers (void);
161 #endif
162
163 #ifndef EXTERNAL_SP_INIT
164
204 void SL_Init_StackPointers (void);
205 #endif
206
255 boolean SL_Init_Memory (SL_AutoInitRamId ramSet);
256
257 /* Not needed for R5 based devices, as ECC is always enabled for memory accesses
258 * in R5. */
259 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
260
299 boolean SL_Init_ECCFlash (uint16 secThreshold, uint16 ctrlFlags);
300 #endif
301
302 /* Not needed for R5 based devices, as ECC is always enabled for memory accesses
303 * in R5. */
304 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
305
345 boolean SL_Init_ECCTCMRAM (uint16 threshold, boolean enableErrIntGen);
346 #endif
347
348
408 SL_ResetReason SL_Init_ResetReason(void);
409
410
411
461 boolean SL_SelfTest_SRAM(SL_SelfTestType testType, boolean bMode, SL_SelfTest_Result * sram_stResult);
462
463
464
523 boolean SL_SelfTest_Flash (SL_SelfTestType testType, boolean bMode, SL_SelfTest_Result * flash_stResult);
524
525
526 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
527
571 boolean SL_SelfTest_FEE (SL_SelfTestType testType, boolean bMode, SL_SelfTest_Result * fee_stResult);
572 #endif
573
574
865 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
866 boolean SL_SelfTest_PBIST (register SL_SelfTestType testType, register uint32 ramGroup, register uint32 algoInfo);
867 #endif
868 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
869 boolean SL_SelfTest_PBIST (register SL_SelfTestType testType, register uint64 ramGroup, register uint32 algoInfo);
870 #endif
871
872
916 boolean SL_SelfTest_Status_PBIST(SL_PBIST_FailInfo * param1);
917
959 boolean SL_SelfTest_WaitCompletion_PBIST(void);
960
1001 boolean SL_SelfTest_PBIST_StopExec(void);
1002
1003 /* TODO: not yet tested on TMS570LC43x/RM57L */
1004 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_)
1005
1077 boolean SL_SelfTest_PSCON (SL_SelfTestType testType, boolean mode, SL_PSCON_FailInfo * param1);
1078
1079
1080
1121 boolean SL_SelfTest_Status_PSCON (SL_PSCON_FailInfo * param1);
1122 #endif
1123
1124
1125
1183 boolean SL_SelfTest_STC(register SL_SelfTestType testType, register boolean bMode, register SL_STC_Config * config);
1184
1185
1186
1228 boolean SL_SelfTest_Status_STC (SL_STC_FailInfo * failInfostc);
1229
1230
1285 boolean SL_SelfTest_EFuse (SL_SelfTestType testType, boolean bMode, SL_EFuse_Config * config);
1286
1287
1318 boolean SL_SelfTest_Status_EFuse (SL_EFuse_FailInfo * failInfoefuse);
1319
1320 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
1321
1379 boolean SL_SelfTest_CCMR4F (SL_SelfTestType testType, boolean bMode, SL_CCMR4F_FailInfo * config);
1380 #endif
1381
1382 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
1383
1441 boolean SL_SelfTest_CCMR5F (SL_SelfTestType testType, boolean bMode, SL_CCMR5F_FailInfo * config);
1442 #endif
1443
1444 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
1445
1488 boolean SL_SelfTest_Status_CCMR4F (SL_CCMR4F_FailInfo * failInfoccmr4f);
1489 #endif
1490
1491 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
1492
1538 boolean SL_SelfTest_Status_CCMR5F (SL_SelfTestType diagnostic, SL_CCMR5F_FailInfo * failInfoccmr5f);
1539 #endif
1540
1541
1572 void SL_SW_Reset(void);
1573
1574
1575
1611 uint64 SL_CRC_Calculate(uint64 * startAddr, uint32 count64);
1612
1613
1614
1653 void SL_ESM_Init(ESM_Application_Callback appCallback);
1654
1655 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
1656
1704 boolean SL_SelfTest_ADC(SL_SelfTestType testType, boolean mode, SL_ADC_Config * config, SL_ADC_Pinstatus * pinstatus);
1705 #endif
1706
1707
1736 void SL_Clear_nERROR(void);
1737
1738
1739
1763 void SL_Set_nERROR(void);
1764
1765
1766
1790 boolean SL_ESM_nERROR_Active(void);
1791
1792
1793
1822 boolean SL_Init_ResetReason_XInfo (SL_ResetReason_XInfo * rrXInfo);
1823
1824 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
1825
1857 boolean SL_SelfTestL2L3Interconnect(SL_SelfTestType testType);
1858 #endif
1859
1860 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
1861
1906 boolean SL_adcCalibration(sl_adcBASE_t * adc, uint32 * offset_error);
1907 #endif
1908
1909
1910 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
1911
1930 boolean SL_SelfTest_DMA(SL_SelfTestType testType);
1931
1951 boolean SL_SelfTest_CAN(SL_SelfTestType testType, SL_DCAN_Instance instance);
1952
1973 boolean SL_SelfTest_MibSPI(SL_SelfTestType testType, SL_MIBSPI_Instance instance);
1974
1975
1976 #endif
1977
1979 uint32 _SL_Get_DataFault_Status(void);
1980 uint32 _SL_Get_DataFault_Address(void);
1981 #endif /* __SL_API_H__ */
SL_SelfTest_Status_CCMR4F
boolean SL_SelfTest_Status_CCMR4F(SL_CCMR4F_FailInfo *failInfoccmr4f)
Returns the self test result for the previous CCRM4F selftest execution(SL_SelfTest_CCMR4F).To be used whenever the API SL_SelfTest_CCMR4F is called in asynchronous mode i.e. when the parameter bMode of SL_SelfTest_CCMR4F is FALSE.
Definition: sl_selftest.c:2973
SL_Set_nERROR
void SL_Set_nERROR(void)
Function sets the nERROR pin active.
Definition: sl_misc.c:52
SL_SelfTest_PBIST_StopExec
boolean SL_SelfTest_PBIST_StopExec(void)
This function stops the PBIST controller from executing further.
Definition: sl_selftest.c:1842
SL_Init_Memory
boolean SL_Init_Memory(SL_AutoInitRamId ramSet)
Hardware intialization of memories.
Definition: sl_init.c:136
SL_SelfTest_Status_CCMR5F
boolean SL_SelfTest_Status_CCMR5F(SL_SelfTestType diagnostic, SL_CCMR5F_FailInfo *failInfoccmr5f)
Returns the self test result for the previous CCRM4F selftest execution(SL_SelfTest_CCMR5F).To be used whenever the API SL_SelfTest_CCMR5F is called in asynchronous mode i.e. when the parameter bMode of SL_SelfTest_CCMR5F is FALSE.
Definition: sl_selftest.c:3045
SL_SelfTest_Status_PBIST
boolean SL_SelfTest_Status_PBIST(SL_PBIST_FailInfo *param1)
Provides status information on the previous PBIST execution.
Definition: sl_selftest.c:1752
SL_adcCalibration
boolean SL_adcCalibration(sl_adcBASE_t *adc, uint32 *offset_error)
Computes offset error using Calibration mode Below is the flowchart for the SL_adcCalibration.
Definition: sl_selftest.c:3148
SL_ESM_nERROR_Active
boolean SL_ESM_nERROR_Active(void)
Function returns the status of the nERRORpin.
Definition: sl_esm.c:70
SL_PSCON_FailInfo
PSCON failure information. Used in with SL_SelfTest_PSCON_FailInfo API.
ESM_Application_Callback
void(* ESM_Application_Callback)(uint32 grp_channel, uint32 param1, uint32 param2, uint32 param3)
Definition for ESM Application call back type.
Definition: sl_types.h:452
SL_SelfTest_CAN
boolean SL_SelfTest_CAN(SL_SelfTestType testType, SL_DCAN_Instance instance)
Perform a test of the SECDED ECC in CAN .
Definition: sl_selftest.c:3881
SL_Init_R4Registers
void SL_Init_R4Registers(void)
Initializes Cortex-R4F CPU's internal registers.
sl_types.h
File contains the types used by the SafeTI™ Hercules™ Diagnostic Library APIs.
SL_SelfTest_CCMR4F
boolean SL_SelfTest_CCMR4F(SL_SelfTestType testType, boolean bMode, SL_CCMR4F_FailInfo *config)
Executes self-tests on Core Compare Module (CCM).
Definition: sl_selftest.c:2509
SL_SelfTest_MibSPI
boolean SL_SelfTest_MibSPI(SL_SelfTestType testType, SL_MIBSPI_Instance instance)
Perform a test of the SECDED ECC in MibSPI .
Definition: sl_selftest.c:4257
SL_SelfTest_WaitCompletion_PBIST
boolean SL_SelfTest_WaitCompletion_PBIST(void)
Provides information regarding whether PBIST is active or not.
Definition: sl_selftest.c:1826
SL_ResetReason_XInfo
Provides extended information of the previous reset (using shadow registers)
SL_Init_StackPointers
void SL_Init_StackPointers(void)
Initializes CPU's stack pointer for SVC, FIQ, IRQ, ABT, UND & SYS modes.
SL_STC_FailInfo
STC failure information. Used in conjunction with SL_SelfTest_STC_Status API.
sl_config.h
SafeTI™ Hercules™ Diagnostic Library configuration items.
SL_EFuse_FailInfo
EFuse Self-test failure information.
sl_log.h
API's for logging(errors,results) and profiling of functions.
SL_STC_Config
STC Configuration information to be used with SL_SelfTest_STC API.
SL_SW_Reset
void SL_SW_Reset(void)
This function generates an internal warm reset(nRST). This is done by writing appropriate control bi...
Definition: sl_misc.c:12
SL_SelfTest_FEE
boolean SL_SelfTest_FEE(SL_SelfTestType testType, boolean bMode, SL_SelfTest_Result *fee_stResult)
Executes diagnostic tests on F021 Flash.
Definition: sl_selftest.c:1259
SL_Init_R5Registers
void SL_Init_R5Registers(void)
Initializes Cortex-R5F CPU's internal registers.
SL_SelfTest_ADC
boolean SL_SelfTest_ADC(SL_SelfTestType testType, boolean mode, SL_ADC_Config *config, SL_ADC_Pinstatus *pinstatus)
It does the selftest on the required adc pin and provides the information on status of the Pin...
Definition: sl_selftest.c:3281
SL_SelfTestL2L3Interconnect
boolean SL_SelfTestL2L3Interconnect(SL_SelfTestType testType)
It does the Fault injection on L2(Switched central resource) and L3(Peripheral central resource) inte...
Definition: sl_selftest.c:3546
SL_SelfTest_Status_EFuse
boolean SL_SelfTest_Status_EFuse(SL_EFuse_FailInfo *failInfoefuse)
Retrieves the status of the previous EFuse self-test execution.
Definition: sl_selftest.c:2440
SL_Init_ResetReason_XInfo
boolean SL_Init_ResetReason_XInfo(SL_ResetReason_XInfo *rrXInfo)
Function is used to return extended information on the reset reason.
Definition: sl_init.c:308
SL_SelfTest_Status_STC
boolean SL_SelfTest_Status_STC(SL_STC_FailInfo *failInfostc)
Returns the status of previously executed CPU self-test via STC.
Definition: sl_selftest.c:1967
SL_ESM_Init
void SL_ESM_Init(ESM_Application_Callback appCallback)
Initializes the ESM module handing in the SafeTI™ Hercules™ Diagnostic Library. ...
Definition: sl_esm.c:62
SL_Init_ECCFlash
boolean SL_Init_ECCFlash(uint16 secThreshold, uint16 ctrlFlags)
Enables detection of Flash ECC errors on Cortex-R4F.
Definition: sl_init.c:100
SL_SelfTest_DMA
boolean SL_SelfTest_DMA(SL_SelfTestType testType)
Perform a test of the SECDED ECC in DMA .
Definition: sl_selftest.c:3613
SL_SelfTest_Status_PSCON
boolean SL_SelfTest_Status_PSCON(SL_PSCON_FailInfo *param1)
Returns the status for previous PSCON self-test execution .
Definition: sl_selftest.c:2266
SL_SelfTest_SRAM
boolean SL_SelfTest_SRAM(SL_SelfTestType testType, boolean bMode, SL_SelfTest_Result *sram_stResult)
Executes diagnostic tests on TCM RAM SECDED logic.
Definition: sl_selftest.c:51
SL_SelfTest_Flash
boolean SL_SelfTest_Flash(SL_SelfTestType testType, boolean bMode, SL_SelfTest_Result *flash_stResult)
Executes diagnostic tests on F021 Flash.
Definition: sl_selftest.c:744
SL_CRC_Calculate
uint64 SL_CRC_Calculate(uint64 *startAddr, uint32 count64)
This function calculates the CRC of specified memory (& length) using the hardware CRC implementing t...
Definition: sl_misc.c:27
SL_SelfTest_STC
boolean SL_SelfTest_STC(register SL_SelfTestType testType, register boolean bMode, register SL_STC_Config *config)
Executes CPU Logic Built-In Self Test using Self-Test Controller.
Definition: sl_selftest.c:1858
SL_SelfTest_EFuse
boolean SL_SelfTest_EFuse(SL_SelfTestType testType, boolean bMode, SL_EFuse_Config *config)
This function executes self tests on the eFuse structures.
Definition: sl_selftest.c:2305
SL_Init_ResetReason
SL_ResetReason SL_Init_ResetReason(void)
Provides source of last reset.
Definition: sl_init.c:184
SL_SelfTest_PBIST
boolean SL_SelfTest_PBIST(register SL_SelfTestType testType, register uint32 ramGroup, register uint32 algoInfo)
Executes PBIST tests on RAM groups with different algorithms.
SL_Init_ECCTCMRAM
boolean SL_Init_ECCTCMRAM(uint16 threshold, boolean enableErrIntGen)
Enables/Disables detection of ECC errors on TCM SRAM on Cortex-R4F.
Definition: sl_init.c:36
SL_SelfTest_PSCON
boolean SL_SelfTest_PSCON(SL_SelfTestType testType, boolean mode, SL_PSCON_FailInfo *param1)
Provides interface to run PSCON self tests.
Definition: sl_selftest.c:2067
_SL_Get_DataFault_Status
uint32 _SL_Get_DataFault_Status(void)
SL_SelfTest_CCMR5F
boolean SL_SelfTest_CCMR5F(SL_SelfTestType testType, boolean bMode, SL_CCMR5F_FailInfo *config)
Executes self-tests on Core Compare Module (CCM).
Definition: sl_selftest.c:2707
SL_Clear_nERROR
void SL_Clear_nERROR(void)
Function clears the nERROR (de-activates) signal.
Definition: sl_misc.c:45
Generated on Fri Feb 6 2015 03:20:29 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: safety_library/include/sl_config.h Source File

  • File List
  • Globals
  • safety_library
  • include
sl_config.h
Go to the documentation of this file.
1 /*******************************************************************************
2 **+--------------------------------------------------------------------------+**
3 **| |**
4 **| Copyright (c) 2012 Texas Instruments Incorporated |**
5 **| ALL RIGHTS RESERVED |**
6 **| |**
7 **| Permission is hereby granted to licensees of Texas Instruments |**
8 **| Incorporated (TI) products to use this computer program for the sole |**
9 **| purpose of implementing a licensee product based on TI products. |**
10 **| No other rights to reproduce, use, or disseminate this computer |**
11 **| program, whether in part or in whole, are granted. |**
12 **| |**
13 **| TI makes no representation or warranties with respect to the |**
14 **| performance of this computer program, and specifically disclaims |**
15 **| any responsibility for any damages, special or consequential, |**
16 **| connected with the use of this program. |**
17 **| |**
18 **+--------------------------------------------------------------------------+**
19 *******************************************************************************/
30 #ifndef __SL_CONFIG_H__
31 #define __SL_CONFIG_H__
32
33
34 #ifndef EXTERNAL_SP_INIT
35
39 #define SL_REG_INIT_VAL 0u
40
46 #define STACK_SIZE_MODE_SVC 1024u
47 #define STACK_SIZE_MODE_FIQ 1024u
48 #define STACK_SIZE_MODE_IRQ 1024u
49 #define STACK_SIZE_MODE_ABT 1024u
50 #define STACK_SIZE_MODE_UND 1024u
51 #define STACK_SIZE_MODE_SYS 1024u
53 #endif
54
64 #define NERROR_HOLD_DELAY (uint32)10u
76 #define SRAM_START (uint32)0x08000000u
77 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
78 #define SRAM_END (uint32)0x0807FFFFu
79 #endif
80 #if defined(_TMS570LS31x_) || defined(_RM48x_)
81 #define SRAM_END (uint32)0x0803FFFFu
82 #endif
83 #if defined(_TMS570LS12x_) || defined(_RM46x_)
84 #define SRAM_END (uint32)0x0802FFFFu
85 #endif
86 #if defined(_RM42x_) || defined(_TMS570LS04x_)
87 #define SRAM_END (uint32)0x08007FFFu
88 #endif
89
90
93 #if 1
94
103 #define FUNCTION_PARAM_CHECK_ENABLED 1u
104 #define FUNC_ENTRY_COND_CHECK_ENABLED 1u
105 #define FUNC_RESULT_LOG_ENABLED 0u
107 #endif
108
115 #if(FUNC_RESULT_LOG_ENABLED == 1)
116 #define LOG_RESULT_BUFFER_COUNT 32u
117 #else
118 #define LOG_RESULT_BUFFER_COUNT 0u
119 #endif
120 #if defined(FUNCTION_PARAM_CHECK_ENABLED) || defined(FUNC_ENTRY_COND_CHECK_ENABLED)
121 #define LOG_ERROR_BUFFER_COUNT 32u
122 #else
123 #define LOG_ERROR_BUFFER_COUNT 0u
124 #endif
125
127 #if 1
128
137 #define FUNCTION_PROFILING_ENABLED 0u
139 #endif
140 #endif /* __SL_CONFIG_H__ */
141
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SafeTI™ Diagnostic Library: safety_library/include/sl_log.h Source File

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sl_log.h
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1 /*******************************************************************************
2 **+--------------------------------------------------------------------------+**
3 **| |**
4 **| Copyright (c) 2012 Texas Instruments Incorporated |**
5 **| ALL RIGHTS RESERVED |**
6 **| |**
7 **| Permission is hereby granted to licensees of Texas Instruments |**
8 **| Incorporated (TI) products to use this computer program for the sole |**
9 **| purpose of implementing a licensee product based on TI products. |**
10 **| No other rights to reproduce, use, or disseminate this computer |**
11 **| program, whether in part or in whole, are granted. |**
12 **| |**
13 **| TI makes no representation or warranties with respect to the |**
14 **| performance of this computer program, and specifically disclaims |**
15 **| any responsibility for any damages, special or consequential, |**
16 **| connected with the use of this program. |**
17 **| |**
18 **+--------------------------------------------------------------------------+**
19 *******************************************************************************/
29 #ifndef SL_LOG_H_
30 #define SL_LOG_H_
31 #include <sl_api.h>
32
39 #define ERR_TYPE_ENTRY_CON 0x00000001u
40 #define ERR_TYPE_PARAM 0x00000002u
49 typedef enum _sl_log_func_id{
50 FUNC_ID_ST_SRAM=0xA,
51 FUNC_ID_ST_FLASH,
52 FUNC_ID_ST_ADC,
53 FUNC_ID_ST_PBIST,
54 FUNC_ID_ST_PBIST_STATUS,
55 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
56 FUNC_ID_ST_CCMR4F,
57 FUNC_ID_ST_CCMR4F_STATUS,
58 #endif
59 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
60 FUNC_ID_ST_CCMR5F,
61 FUNC_ID_ST_CCMR5F_STATUS,
62 #endif
63 FUNC_ID_ST_PSCON,
64 FUNC_ID_ST_STC,
65 FUNC_ID_ST_EFUSE,
66 /* Unavoidable warning - trailing comma - Due to use of macros */
67 FUNC_ID_ST_L2L3INTERCONNECT,
68 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
69 FUNC_ID_ST_DMA,
70 FUNC_ID_ST_CAN,
71 FUNC_ID_ST_SPI
72 #endif
73 } SL_Log_FuncId;
75 #if FUNC_RESULT_LOG_ENABLED
76
92 void SL_Log_Result(SL_Log_FuncId fnId, SL_SelfTestType log_testType, SL_SelfTest_Result log_stResult, uint32 errNum);
93 #endif
94
95
111 void SL_Log_Error(SL_Log_FuncId fnId, uint32 errType, uint32 errNum);
126 typedef struct __SL_Profile_Struct {
127 uint32 last_entrytick;
128 uint32 last_exittick;
129 uint32 error_creation_tick;
130 uint32 execution_count;
131 uint32 cumilative_execution_tick;
132 uint32 esm_entrytick;
133 uint32 esm_exittick;
134 uint32 aborthandler_entrytick;
135 uint32 aborthandler_exittick;
136 } _SL_Profile_Struct;
137
143 typedef struct __SL_Profile_Pbist_Struct {
144 uint32 last_entrytick;
145 uint32 last_exittick;
146 uint32 execution_count;
147 uint32 cumilative_execution_tick;
148 } _SL_Profile_Pbist_Struct;
151 #define PBIST_MEM_MAX (uint32)29u
152 #define PBIST_ALGO_MAX (uint32)30u
153
154 #if FUNCTION_PROFILING_ENABLED
155 /*these variables will be defined in the sl_log.c and if necessary they can be used externally*/
156 extern _SL_Profile_Struct SL_Profile_Struct[TESTTYPE_MAX - TESTTYPE_MIN];
157 extern _SL_Profile_Pbist_Struct SL_Pbist_Profile_Struct[PBIST_MEM_MAX][PBIST_ALGO_MAX];
158 extern uint32 SL_Active_Profile_Testtype;
159
175 void SL_Init_Profiling(void);
176
191 void SL_Start_Profiling(SL_SelfTestType profile_testyype);
192
208 void SL_Stop_Profiling(SL_SelfTestType profile_testyype);
209
225 void SL_Record_Errorcreationtick(SL_SelfTestType profile_testyype);
226
242 boolean SL_Start_Profiling_PBIST(register uint32 ramGroup, register uint32 algoInfo);
243
259 boolean SL_Stop_Profiling_PBIST(register uint32 ramGroup, register uint32 algoInfo);
260 #endif
261 #endif /* SL_LOG_H_ */
FUNC_ID_ST_CCMR5F_STATUS
Definition: sl_log.h:61
FUNC_ID_ST_ADC
Definition: sl_log.h:52
FUNC_ID_ST_L2L3INTERCONNECT
Definition: sl_log.h:67
sl_api.h
Main API files for Hercules SafeTI™ Hercules™ Diagnostic Library.
FUNC_ID_ST_SRAM
Definition: sl_log.h:50
FUNC_ID_ST_FLASH
Definition: sl_log.h:51
FUNC_ID_ST_PBIST
Definition: sl_log.h:53
FUNC_ID_ST_CCMR4F_STATUS
Definition: sl_log.h:57
FUNC_ID_ST_PSCON
Definition: sl_log.h:63
FUNC_ID_ST_SPI
Definition: sl_log.h:71
FUNC_ID_ST_DMA
Definition: sl_log.h:69
FUNC_ID_ST_CAN
Definition: sl_log.h:70
FUNC_ID_ST_EFUSE
Definition: sl_log.h:65
FUNC_ID_ST_PBIST_STATUS
Definition: sl_log.h:54
SL_Log_Error
void SL_Log_Error(SL_Log_FuncId fnId, uint32 errType, uint32 errNum)
This function logs the errors that were captured by the SafeTI™ Hercules™ Diagnostic library API in...
Definition: sl_log.c:284
_SL_Profile_Pbist_Struct
structure for storing the profiling information of PBIST tests on various ramgroups fir different alg...
_SL_Profile_Struct
structure for storing the profiling information of each testtype.
TESTTYPE_MIN
#define TESTTYPE_MIN
Definition: sl_types.h:842
TESTTYPE_MAX
#define TESTTYPE_MAX
Definition: sl_types.h:848
FUNC_ID_ST_CCMR4F
Definition: sl_log.h:56
FUNC_ID_ST_STC
Definition: sl_log.h:64
FUNC_ID_ST_CCMR5F
Definition: sl_log.h:60
Generated on Fri Feb 6 2015 03:20:29 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: safety_library/source/sl_priv.h Source File

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sl_priv.h
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1 /*******************************************************************************
2 **+--------------------------------------------------------------------------+**
3 **| **** |**
4 **| **** |**
5 **| ******o*** |**
6 **| ********_///_**** |**
7 **| ***** /_//_/ **** |**
8 **| ** ** (__/ **** |**
9 **| ********* |**
10 **| **** |**
11 **| *** |**
12 **| |**
13 **| Copyright (c) 2012 Texas Instruments Incorporated |**
14 **| ALL RIGHTS RESERVED |**
15 **| |**
16 **| Permission is hereby granted to licensees of Texas Instruments |**
17 **| Incorporated (TI) products to use this computer program for the sole |**
18 **| purpose of implementing a licensee product based on TI products. |**
19 **| No other rights to reproduce, use, or disseminate this computer |**
20 **| program, whether in part or in whole, are granted. |**
21 **| |**
22 **| TI makes no representation or warranties with respect to the |**
23 **| performance of this computer program, and specifically disclaims |**
24 **| any responsibility for any damages, special or consequential, |**
25 **| connected with the use of this program. |**
26 **| |**
27 **+--------------------------------------------------------------------------+**
28 *******************************************************************************/
37 #ifndef __SL_PRIV_H__
38 #define __SL_PRIV_H__
39
40 #include <sl_types.h>
41 #include <sl_config.h>
42 #include <sl_api.h>
43
44 #include <sl_reg_system.h>
45
46
47
48
49 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
50 #define BIT(n) ((uint32)((uint32)1u <<(n)))
51
52 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
53 #define BIT_SET(y, mask) ((y) |= (mask))
54
55 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
56 #define BIT_CLEAR(y, mask) ((y) &= ~(mask))
57
58 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
59 #define BIT_FLIP(y, mask) ((y) ^= (mask))
60
61 /* Create a bitmask of length \a len.*/
62 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
63 #define BIT_MASK(len) (uint32)(BIT(len)-(uint32)1u)
64
65 /* Create a bitfield mask of length \a starting at bit \a start.*/
66 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
67 #define BF_MASK(start, len) (BIT_MASK(len)<<(start))
68
69 /* Prepare a bitmask for insertion or combining.*/
70 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
71 #define BF_PREP(x, start, len) (((x)&BIT_MASK(len)) << (start))
72
73 /*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Use of ternary operator is allowed" */
74 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
75 #define GET_ESM_BIT_NUM(x) ((x)<(uint32)32U? (BIT((x))): ((x)<(uint32)64u?(BIT(((x)-((uint32)32U)))):(BIT(((x)-((uint32)64u))))))
76 /* Extract a bitfield of length \a len starting at bit \a start from \a y.
77 * y is the register
78 * start is the starting bit of the field
79 * len is the length of the field*/
80 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
81 #define BF_GET(y, start, len) ((uint32)(((uint32)((y)>>(start))) & BIT_MASK(len)))
82
83 /*Insert a new bitfield value \a x into \a y.
84 * y is the register
85 * x is the value of the field
86 * start is the starting bit of the field
87 * len is the length of the field*/
88 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
89 #define BF_SET(y, x, start, len) \
90 ( (y) = ((y) & (~(BF_MASK((start),(len))))) | BF_PREP((x),(start),(len)))
91
92
93 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
94 #define _SELFTEST_SRAMECC_MIN ((SL_SelfTestType)SRAM_ECC_ERROR_FORCING_1BIT)
95 #define _SELFTEST_SRAMECC_MAX ((SL_SelfTestType)SRAM_RADECODE_DIAGNOSTICS)
96
97 #define _SELFTEST_FLASHECC_MIN ((SL_SelfTestType)FLASH_ECC_ADDR_TAG_REG_MODE)
98 #define _SELFTEST_FLASHECC_MAX ((SL_SelfTestType)FLASH_ECC_TEST_MODE_2BIT_FAULT_INJECT)
99
100 #define _SELFTEST_FEEECC_MIN ((SL_SelfTestType)FEE_ECC_DATA_CORR_MODE)
101 #define _SELFTEST_FEEECC_MAX ((SL_SelfTestType)FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT)
102
103 #define _SELFTEST_PBIST_MIN ((SL_SelfTestType)PBIST_EXECUTE)
104 #define _SELFTEST_PBIST_MAX ((SL_SelfTestType)PBIST_EXECUTE_OVERRIDE)
105
106 #define _SELFTEST_STC_MIN ((SL_SelfTestType)STC_RUN)
107 #define _SELFTEST_STC_MAX ((SL_SelfTestType)STC_COMPARE_SELFCHECK)
108
109 #define _SELFTEST_PSCON_MIN (SL_SelfTestType)(PSCON_SELF_TEST)
110 #define _SELFTEST_PSCON_MAX ((SL_SelfTestType)PSCON_PMA_TEST)
111
112 #define _SELFTEST_EFUSE_MIN ((SL_SelfTestType)EFUSE_SELF_TEST_AUTOLOAD)
113 #define _SELFTEST_EFUSE_MAX ((SL_SelfTestType)EFUSE_SELF_TEST_STUCK_AT_ZERO)
114
115 #define _SELFTEST_CCMR4F_MIN ((SL_SelfTestType)CCMR4F_SELF_TEST)
116 #define _SELFTEST_CCMR4F_MAX ((SL_SelfTestType)CCMR4F_SELF_TEST_ERROR_FORCING)
117
118 #define _SELFTEST_L2L3INTERCONNECT_MIN ((SL_SelfTestType)L2INTERCONNECT_FAULT_INJECT)
119 #define _SELFTEST_L2L3INTERCONNECT_MAX ((SL_SelfTestType)L3INTERCONNECT_FAULT_INJECT)
120 #endif
121
122 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
123 #define _SELFTEST_SRAMECC_MIN ((SL_SelfTestType)SRAM_ECC_ERROR_FORCING_1BIT)
124 #define _SELFTEST_SRAMECC_MAX ((SL_SelfTestType)SRAM_ECC_ERROR_FORCING_2BIT)
125
126 #define _SELFTEST_FLASHECC_MIN ((SL_SelfTestType)FLASH_ECC_TEST_MODE_1BIT)
127 #define _SELFTEST_FLASHECC_MAX ((SL_SelfTestType)FLASH_ECC_TEST_MODE_2BIT)
128
129 #define _SELFTEST_PBIST_MIN ((SL_SelfTestType)PBIST_EXECUTE)
130 #define _SELFTEST_PBIST_MAX ((SL_SelfTestType)PBIST_EXECUTE_OVERRIDE)
131
132 #define _SELFTEST_PSCON_MIN (SL_SelfTestType)(PSCON_SELF_TEST)
133 #define _SELFTEST_PSCON_MAX ((SL_SelfTestType)PSCON_PMA_TEST)
134
135 #define _SELFTEST_EFUSE_MIN ((SL_SelfTestType)EFUSE_SELF_TEST_AUTOLOAD)
136 #define _SELFTEST_EFUSE_MAX ((SL_SelfTestType)EFUSE_SELF_TEST_STUCK_AT_ZERO)
137
138 #define _SELFTEST_CCMR5F_MIN ((SL_SelfTestType)CCMR5F_CPUCOMP_SELF_TEST)
139 #define _SELFTEST_CCMR5F_MAX ((SL_SelfTestType)CCMR5F_INMCOMP_SELF_TEST_ERROR_FORCING)
140
141 #define _SELFTEST_DMA_MIN ((SL_SelfTestType)DMA_ECC_TEST_MODE_1BIT)
142 #define _SELFTEST_DMA_MAX ((SL_SelfTestType)DMA_ECC_TEST_MODE_2BIT_FAULT_INJECT)
143
144 #define _SELFTEST_CAN_MIN ((SL_SelfTestType)CAN_ECC_TEST_MODE_1BIT)
145 #define _SELFTEST_CAN_MAX ((SL_SelfTestType)CAN_ECC_TEST_MODE_2BIT_FAULT_INJECT)
146
147 #define DCAN_MIN 1
148 #define DCAN_MAX 4
149
150 #define _SELFTEST_STC_MIN ((SL_SelfTestType)STC1_RUN)
151 #define _SELFTEST_STC_MAX ((SL_SelfTestType)STC2_COMPARE_SELFCHECK)
152
153 #endif
154
155
156 #define ARM_MODE_USR (0x10u)
157 #define ARM_MODE_FIQ (0x11u)
158 #define ARM_MODE_IRQ (0x12u)
159 #define ARM_MODE_SVC (0x13u)
160 #define ARM_MODE_ABT (0x17u)
161 #define ARM_MODE_UND (0x1Bu)
162 #define ARM_MODE_SYS (0x1Fu)
163
164 #define CCMR4F_EFT_EXEC 0u
165 #define CCMR4F_STEFT_EXEC 1u
166 #define CCMR4F_PSCON_PMA 2u
167
168 #define ADC_APPROXIMATION_THRESHOLD 5u
169 #define ADC_FIFO_SIZE 1u
170 #define ADC_POWERDOWN_MODE (0x00000100U)
171 #define ADC_ENABLE (0x00000001U)
172
173 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
174 #define ALL_PBIST_RAM_GROUPS (PBIST_RAMGROUP_01_PBIST_ROM |\
175 PBIST_RAMGROUP_02_STC_ROM |\
176 PBIST_RAMGROUP_03_DCAN1 |\
177 PBIST_RAMGROUP_04_DCAN2 |\
178 PBIST_RAMGROUP_05_DCAN3 |\
179 PBIST_RAMGROUP_06_ESRAM1 |\
180 PBIST_RAMGROUP_07_MIBSPI1 |\
181 PBIST_RAMGROUP_08_MIBSPI3 |\
182 PBIST_RAMGROUP_09_MIBSPI5 |\
183 PBIST_RAMGROUP_10_VIM |\
184 PBIST_RAMGROUP_11_MIBADC1 |\
185 PBIST_RAMGROUP_12_DMA |\
186 PBIST_RAMGROUP_13_N2HET1 |\
187 PBIST_RAMGROUP_14_HETTU1 |\
188 PBIST_RAMGROUP_15_RTP |\
189 PBIST_RAMGROUP_16_FRAY |\
190 PBIST_RAMGROUP_17_FRAY |\
191 PBIST_RAMGROUP_18_MIBADC2 |\
192 PBIST_RAMGROUP_19_N2HET2 |\
193 PBIST_RAMGROUP_20_HETTU2 |\
194 PBIST_RAMGROUP_21_ESRAM5 |\
195 PBIST_RAMGROUP_22_ESRAM6 |\
196 PBIST_RAMGROUP_23_ETHERNET1 |\
197 PBIST_RAMGROUP_24_ETHERNET2 |\
198 PBIST_RAMGROUP_25_ETHERNET3 |\
199 PBIST_RAMGROUP_26_USB1 |\
200 PBIST_RAMGROUP_27_USB2 |\
201 PBIST_RAMGROUP_28_ESRAM8 |\
202 PBIST_RAMGROUP_29_RSVD)
203
204 #define ALL_PBISALGO (PBISTALGO_TRIPLE_READ_SLOW_READ |\
205 PBISTALGO_TRIPLE_READ_FAST_READ |\
206 PBISTALGO_MARCH13N_RED_2PORT |\
207 PBISTALGO_MARCH13N_RED_1PORT |\
208 PBISTALGO_DOWN1A_RED_2PORT |\
209 PBISTALGO_DOWN1A_RED_1PORT |\
210 PBISTALGO_MAPCOLUMN_2PORT |\
211 PBISTALGO_MAPCOLUMN_1PORT |\
212 PBISTALGO_PRECHARGE_2PORT |\
213 PBISTALGO_PRECHARGE_1PORT |\
214 PBISTALGO_DTXN2_2PORT |\
215 PBISTALGO_DTXN2_1PORT |\
216 PBISTALGO_PMOS_OPEN_2PORT |\
217 PBISTALGO_PMOS_OPEN_1PORT |\
218 PBISTALGO_PMOS_OP_SLICE1_2PORT |\
219 PBISTALGO_PMOS_OP_SLICE2_2PORT |\
220 PBISTALGO_FLIP10_2PORT |\
221 PBISTALGO_FLIP10_1PORT |\
222 PBISTALGO_IDDQ_2PORT |\
223 PBISTALGO_IDDQ_1PORT |\
224 PBISTALGO_RETENTION_2PORT |\
225 PBISTALGO_RETENTION_1PORT |\
226 PBISTALGO_IDDQ2_2PORT |\
227 PBISTALGO_IDDQ2_1PORT |\
228 PBISTALGO_RETENTION2_2PORT |\
229 PBISTALGO_RETENTION2_1PORT |\
230 PBISTALGO_IDDQROWSTRIPE_2PORT |\
231 PBISTALGO_IDDQROWSTRIPE_1PORT |\
232 PBISTALGO_IDDQROWSTRIPE2_2PORT |\
233 PBISTALGO_IDDQROWSTRIPE2_1PORT)
234 #endif
235 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
236 #define ALL_PBIST_RAM_GROUPS (PBIST_RAMGROUP_01_PBIST_ROM |\
237 PBIST_RAMGROUP_02_STC1_1_ROM_R5 |\
238 PBIST_RAMGROUP_03_STC1_2_ROM_R5 |\
239 PBIST_RAMGROUP_04_STC2_ROM_NHET |\
240 PBIST_RAMGROUP_05_AWM1 |\
241 PBIST_RAMGROUP_06_DCAN1 |\
242 PBIST_RAMGROUP_07_DCAN2 |\
243 PBIST_RAMGROUP_08_DMA |\
244 PBIST_RAMGROUP_09_HTU1 |\
245 PBIST_RAMGROUP_10_MIBSPI1 |\
246 PBIST_RAMGROUP_11_MIBSPI2 |\
247 PBIST_RAMGROUP_12_MIBSPI3 |\
248 PBIST_RAMGROUP_13_NHET1 |\
249 PBIST_RAMGROUP_14_VIM |\
250 PBIST_RAMGROUP_15_RSVD |\
251 PBIST_RAMGROUP_16_RTP |\
252 PBIST_RAMGROUP_17_ATB |\
253 PBIST_RAMGROUP_18_AWM2 |\
254 PBIST_RAMGROUP_19_DCAN3 |\
255 PBIST_RAMGROUP_20_DCAN4 |\
256 PBIST_RAMGROUP_21_HTU2 |\
257 PBIST_RAMGROUP_22_MIBSPI4 |\
258 PBIST_RAMGROUP_23_MIBSPI5 |\
259 PBIST_RAMGROUP_24_NHET2 |\
260 PBIST_RAMGROUP_25_FTU |\
261 PBIST_RAMGROUP_26_FRAY_INBUF_OUTBUF |\
262 PBIST_RAMGROUP_27_CPGMAC_STATE_RXADDR |\
263 PBIST_RAMGROUP_28_CPGMAC_STAT_FIFO |\
264 PBIST_RAMGROUP_29_L2RAMW |\
265 PBIST_RAMGROUP_30_L2RAMW |\
266 PBIST_RAMGROUP_31_R5_ICACHE |\
267 PBIST_RAMGROUP_32_R5DCACHE |\
268 PBIST_RAMGROUP_33_RSVD |\
269 PBIST_RAMGROUP_34_RSVD |\
270 PBIST_RAMGROUP_35_FRAY_TRBUF_MSGRAM |\
271 PBIST_RAMGROUP_36_CPGMAC_CPPI |\
272 PBIST_RAMGROUP_37_R5_DCACHE_DIRTY |\
273 PBIST_RAMGROUP_38_RSVD)
274
275 #define ALL_PBISALGO (PBISTALGO_TRIPLE_READ_SLOW_READ |\
276 PBISTALGO_TRIPLE_READ_FAST_READ |\
277 PBISTALGO_MARCH13N_2PORT |\
278 PBISTALGO_MARCH13N_1PORT |\
279 PBISTALGO_DOWN2_1PORT |\
280 PBISTALGO_DOWN2_2PORT |\
281 PBISTALGO_MARCH_DIS_INC_1PORT |\
282 PBISTALGO_MARCH_DIS_INC_2PORT |\
283 PBISTALGO_MARCH_DIS_DEC_1PORT |\
284 PBISTALGO_MARCH_DIS_DEC_2PORT |\
285 PBISTALGO_MARCH_DIS_INC_1PORT_1 |\
286 PBISTALGO_MARCH_DIS_INC_2PORT_1 |\
287 PBISTALGO_MARCH_DIS_DEC_1PORT_1 |\
288 PBISTALGO_MARCH_DIS_DEC_2PORT_1 |\
289 PBISTALGO_MAP_COLUMN_1PORT |\
290 PBISTALGO_MAP_COLUMN_2PORT |\
291 PBISTALGO_PRECHARGE_1PORT |\
292 PBISTALGO_PRECHARGE_2PORT |\
293 PBISTALGO_FLIP10_1PORT |\
294 PBISTALGO_FLIP10_2PORT |\
295 PBISTALGO_DTXN2_1PORT |\
296 PBISTALGO_DTXN2_2PORT |\
297 PBISTALGO_PMOS_OP_SLICE1_1PORT |\
298 PBISTALGO_PMOS_OP_SLICE1_2PORT |\
299 PBISTALGO_PMOS_OP_SLICE2_2PORT)
300 #endif
301
302 #define ST_BOUNDARY_VALUE ((uint32)(EFC_BOUNDARY_SELF_TEST_ERR | EFC_BOUNDARY_SINGLE_BIT_ERR | \
303 EFC_BOUNDARY_INSTR_ERR | EFC_BOUNDARY_AUTOLOAD_ERR))
304 #define ST_PIN_VALUE ((uint32)(EFC_PINS_AUTOLOAD_ERR | EFC_PINS_INSTR_ERR | \
305 EFC_PINS_SINGLE_BIT_ERR | EFC_PINS_SELF_TEST_ERROR))
306
307
308 #define ROM_CLK_SRC_HCKL_DIV_2 1u
309 #define ENABLE_OVERRIDE 1u
310 #define DISABLE_OVERRIDE 0u
311 #define ALG_RAM_FROM_ROM 3u
312 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
313 #define VBUS_CLK_CYCLES 64u
314 #endif
315 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
316 #define VBUS_CLK_CYCLES 32u
317 #endif
318
319 /*Bit Fields*/
320 #define BF_ROM_DIV_START 8u
321 #define BF_ROM_DIV_LENGTH 2u
322
323 /*Bit Fields*/
324 #define BF_MSTGENA_START 0u
325 #define BF_MSTGENA_LENGTH 4u
326 #define ENABLE_MEM_STEST_CTRL 0xau
327 #define DISABLE_MEM_STEST_CTRL 0x5u
328
329 /*Bit Fields*/
330 #define BF_MINITGENA_START 0u
331 #define BF_MINITGENA_LENGTH 4u
332 #define ENABLE_GLOB_MEM_HW_INIT 0xau
333 #define DISABLE_GLOB_MEM_HW_INIT 0x5u
334
335 /*Bit Fields*/
336 #define BF_MINIDONE_START 8u
337 #define BF_MINIDONE_LENGTH 1u
338 #define MEM_HW_INIT_COMPLETE (uint32)1u
339 #define MEM_HW_INIT_INCOMPLETE 0u
340
341 /*Bit Fields*/
342 #define BF_EPSF_START 0u
343 #define BF_EPSF_LENGTH 1u
344
345 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
346 /*Bit Fields*/
347 #define BF_CCMR4_CMP_ERROR 2u
348 #define BF_CCMR4_CMP_ERROR_LENGTH 1u
349 #define BF_CCMR4_STEST_ERROR 31u
350 #define BF_CCMR4_STEST_ERROR_LENGTH 1u
351 #endif
352 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
353 #define BF_CCMR5_CPUCOMP_ERROR 2u
354 #define BF_CCMR5_VIMCOMP_ERROR 25u
355 #define BF_CCMR5_PDCOMP_ERROR 28u
356 #define BF_CCMR5_INMCOMP_ERROR 26u
357 #define BF_CCMR5_CMP_ERROR_LENGTH 1u
358 #define BF_CCMR5_STEST_ERROR 31u
359 #define BF_CCMR5_STEST_ERROR_LENGTH 1u
360 #endif
361
362 /*Bit Fields*/
363 #define BF_SERR_EN_START 0u
364 #define BF_SERR_EN_LEN 1u
365 #define SERR_ENABLE 1u
366 #define SERR_DISABLE 0u
367
368 /*Bit Fields*/
369 #define BF_ECC_DETECT_EN_START 0u
370 #define BF_ECC_DETECT_EN_LEN 4u
371 #define ECC_DETECT_ENABLE 5u
372 #define ECC_DETECT_DISABLE 0u
373
374 /*Bit Fields*/
375 #define BF_ECC_WR_EN_START 8u
376 #define BF_ECC_WR_EN_LEN 1u
377 #define ECC_WR_ENABLE 1u
378 #define ECC_WR_DISABLE 0u
379
380 /*Bit Fields*/
381 #define BF_EDACEN_START 0u
382 #define BF_EDACEN_LEN 4u
383 #define EDAC_ENABLE_DEF 0xau
384 #define EDAC_DISABLE 5u
385
386 #define BF_EDACMODE_START 16u
387 #define BF_EDACMODE_LEN 4u
388 #define EDACMODE_DEF 0xau
389
390 #define ESM_GRP1_MASK (1U<<16U)
391 #define ESM_GRP2_MASK (2U<<16U)
392 #define ESM_GRP3_MASK (3U<<16U)
393
399 typedef enum _SL_ASC_Groups {
400 sl_adcEVTGROUP, sl_adcGROUP1, sl_adcGROUP2
401 } SL_ADC_Groups;
402
411 typedef struct _SL_ADC_Data {
412 uint32 id;
413 uint16 value;
414 } SL_ADC_Data;
415
416
417
418 /*SAFETYMCUSW 61 D MR: 8.10,8.11 <APPROVED> "This function is in asm file" */
419 void _SL_Restore_IRQ(uint32 val);
420 /*SAFETYMCUSW 61 D MR: 8.10,8.11 <APPROVED> "This function is in asm file" */
421 uint32 _SL_Disable_IRQ(void);
422 /*SAFETYMCUSW 61 D MR: 8.10,8.11 <APPROVED> "This function is in asm file" */
423 uint32 _SL_Get_ARM_Mode(void);
424 /*SAFETYMCUSW 61 D MR: 8.10,8.11 <APPROVED> "This function is in asm file" */
425 void _SL_Kickoff_STC_execution(void);
426 /*SAFETYMCUSW 61 D MR: 8.10,8.11 <APPROVED> "This function is in asm file" */
427 void _SL_Barrier_Data_Access(void);
428
429 /*SAFETYMCUSW 61 D MR: 8.10,8.11 <APPROVED> "This function is in asm file" */
430 void _SL_Init_EnableEventExport(void);
431 /*SAFETYMCUSW 61 D MR: 8.10,8.11 <APPROVED> "This function is in asm file" */
432 void _SL_Init_ECCFlash(void);
433 /*SAFETYMCUSW 61 D MR: 8.10,8.11 <APPROVED> "This function is in asm file" */
434 void _SL_Init_ECCTCMRAM(void);
435
436 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
437 boolean _SL_SelfTest_adcStartConversion_selChn(sl_adcBASE_t * adc, uint8 channel, uint32 fifo_size, uint32 group);
438 boolean _SL_SelfTest_adcGetSingleData(sl_adcBASE_t * adc, uint32 group, SL_ADC_Data * data);
439 boolean _SL_SelfTest_adcIsConversionComplete(const sl_adcBASE_t * adc, uint32 group);
440 uint16 _SL_Approximate_value(uint16 value, uint16 reference, uint8 difference);
441 #endif
442
443 uint64 _SL_CRC_Calculate(uint64 * start_addr, uint32 count_dw);
444 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
445 void _SL_SelfTest_SRAM_RAD (sl_tcramBASE_t * ramBase, SL_SelfTest_Result * rad_stResult);
446 #endif
447 boolean SL_FLAG_GET(sint32 flag_id);
448 void SL_FLAG_CLEAR(sint32 flag_id);
449 boolean SL_FLAG_SET(sint32 flag_id);
450 void _SL_HoldNClear_nError(void);
451
452
453 #ifdef LOOP_BACK_ENABLE
454 #define CAN_LOOP_BACK_MSG_SIZE 9
455 #define CAN_LOOP_BACK_MSG_BOX 34U
456 void _SL_loadDataPattern(uint16 * pptr, uint16 seed_value, uint32 psize);
457 #endif
458
459 /*SAFETYMCUSW 340 S MR:19.7 <APPROVED> "Reason - This is an advisory by MISRA.We accept this as a coding convention*/
460 #define CHECK_RANGE_RAM_PTR(x) ((((uint32)(x)) >= SRAM_START) && ((((uint32)(x)) <= ((SRAM_END-(uint32)sizeof((x)))))))
461
462 #endif /* __SL_PRIV_H__ */
sl_types.h
File contains the types used by the SafeTI™ Hercules™ Diagnostic Library APIs.
sl_api.h
Main API files for Hercules SafeTI™ Hercules™ Diagnostic Library.
sl_config.h
SafeTI™ Hercules™ Diagnostic Library configuration items.
_SL_SelfTest_SRAM_RAD
void _SL_SelfTest_SRAM_RAD(sl_tcramBASE_t *ramBase, SL_SelfTest_Result *rad_stResult)
Definition: sl_priv.c:25
Generated on Fri Feb 6 2015 03:20:29 for SafeTI™ Diagnostic Library by doxygen 1.8.7


SafeTI™ Diagnostic Library: safety_library/include/sl_types.h Source File

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sl_types.h
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1 /*******************************************************************************
2 **+--------------------------------------------------------------------------+**
3 **| |**
4 **| Copyright (c) 2012 Texas Instruments Incorporated |**
5 **| ALL RIGHTS RESERVED |**
6 **| |**
7 **| Permission is hereby granted to licensees of Texas Instruments |**
8 **| Incorporated (TI) products to use this computer program for the sole |**
9 **| purpose of implementing a licensee product based on TI products. |**
10 **| No other rights to reproduce, use, or disseminate this computer |**
11 **| program, whether in part or in whole, are granted. |**
12 **| |**
13 **| TI makes no representation or warranties with respect to the |**
14 **| performance of this computer program, and specifically disclaims |**
15 **| any responsibility for any damages, special or consequential, |**
16 **| connected with the use of this program. |**
17 **| |**
18 **+--------------------------------------------------------------------------+**
19 *******************************************************************************/
30 #ifndef __SL_TYPES_H__
31 #define __SL_TYPES_H__
32
33 #include "sl_sys_common.h"
34 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
35 #include "reg_bitdefn_adc.h" /* \todo Need to remove this dependency */
36 #endif
37
38
39
46 #define FLASHECC_E0FEN (uint32)(1U << 10)
47 #define FLASHECC_EZFEN (uint32)(1U << 9)
48 #define FLASHECC_EPEN (uint32)(1U << 8)
49 #define FLASHECC_EOCV (uint32)(1U << 5)
50 #define FLASHECC_EZCV (uint32)(1U << 4)
51 #define FLASHECC_DEFAULT (uint32)(F021F_FEDACCTRL1_E0FEN | F021F_FEDACCTRL1_EZFEN)
64 #define ESM_G3ERR_EFUSE_AUTOLOAD_ERR (uint32)(1u)
67 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
68 #define ESM_G3ERR_B0TCM_ECC_UNCORR (uint32)(3u)
72 #define ESM_G3ERR_B1TCM_ECC_UNCORR (uint32)(5u)
76 #define ESM_G3ERR_FMC_UNCORR (uint32)(7u)
80 #define ESM_G2ERR_CCMR4_COMP (uint32)(2u)
82 #define ESM_G2ERR_B0TCM_UNCORR (uint32)(6u)
86 #define ESM_G2ERR_B1TCM_UNCORR (uint32)(8u)
90 #define ESM_G2ERR_B0TCM_ADDPAR (uint32)(10u)
94 #define ESM_G2ERR_B1TCM_ADDPAR (uint32)(12u)
98 #define ESM_G2ERR_FMC_UNCORR (uint32)(4u)
102 #define ESM_G2ERR_FLASH_LIVLCK (uint32)(16u)
105 #define ESM_G2ERR_RTI_WWD_NMI (uint32)(24u)
109 #define ESM_G1ERR_FMC_CORR (uint32)(6u)
112 #define ESM_G1ERR_PLL1_SLIP (uint32)(10u)
114 #define ESM_G1ERR_CLOCKMON_INTR (uint32)(11u)
116 #define ESM_G1ERR_VIMRAM_PARITY (uint32)(15u)
118 #define ESM_G1ERR_B0TCM_CORRERR (uint32)(26u)
121 #define ESM_G1ERR_B1TCM_CORRERR (uint32)(28u)
124 #define ESM_G1ERR_DCC1_ERR (uint32)(30u)
126 #define ESM_G1ERR_CCMR4_SELFTEST (uint32)(31u)
128 #define ESM_G1ERR_EEPROM_CORRERR (uint32)(35u)
131 #define ESM_G1ERR_EEPROM_UNCORRERR (uint32)(36u)
134 #define ESM_G1ERR_PSCON_COMPARE_ERR (uint32)(38u)
137 #define ESM_G1ERR_PSCON_SELTEST_ERR (uint32)(39u)
140 #define ESM_G1ERR_PLL2_SLIP (uint32)(42u)
142 #define ESM_G1ERR_DCC2_ERR (uint32)(62u)
144 #endif
145 #define ESM_G1ERR_EFUSE_ERR_OTHER (uint32)(40u)
148 #define ESM_G1ERR_EFUSE_SELTEST_ERR (uint32)(41u)
153 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
154 #define ESM_G2ERR_CCMR5_CPUCOMP_ERR (uint32)(2u)
156 #define ESM_G2ERR_CCMR5_VIMCOMP_ERR (uint32)(25u)
158 #define ESM_G2ERR_CCMR5_INMCOMP_ERR (uint32)(26u)
160 #define ESM_G2ERR_CCMR5_PDCOMP_ERR (uint32)(28u)
162 #define ESM_G2ERR_CR5_BUSERR (uint32)(3u)
164 #define ESM_G2ERR_L2RAMW_UNCORR_B (uint32)(7u)
167 #define ESM_G1ERR_L2RAMW_CORRERR (uint32)(26u)
169 #define ESM_G2ERR_EPC_UNCORR (uint32)(21u)
172 #define ESM_G1ERR_EPC_SERR (uint32)(4u)
175 #define ESM_G1ERR_CCMR5_SELFTEST (uint32)(31u)
178 #define ESM_G1ERR_CCMR5_OPERATING_STATUS (uint32)(92u)
182 #define ESM_G1ERR_DMA_ECC_SBERR (uint32)(82u)
185 #define ESM_G1ERR_DMA_ECC_UNCORR (uint32)(3u)
189 #define ESM_G1ERR_CAN1_ECC_SBERR (uint32)(73u)
192 #define ESM_G1ERR_CAN1_ECC_UNCORR (uint32)(21u)
195 #define ESM_G1ERR_CAN2_ECC_SBERR (uint32)(74u)
198 #define ESM_G1ERR_CAN2_ECC_UNCORR (uint32)(23u)
201 #define ESM_G1ERR_CAN3_ECC_SBERR (uint32)(75u)
204 #define ESM_G1ERR_CAN3_ECC_UNCORR (uint32)(22u)
207 #define ESM_G1ERR_CAN4_ECC_SBERR (uint32)(76u)
210 #define ESM_G1ERR_CAN4_ECC_UNCORR (uint32)(51u)
214 #define ESM_G1ERR_SPI1_ECC_SBERR (uint32)(77u)
217 #define ESM_G1ERR_SPI2_ECC_SBERR (uint32)(78u)
220 #define ESM_G1ERR_SPI3_ECC_SBERR (uint32)(79u)
223 #define ESM_G1ERR_SPI4_ECC_SBERR (uint32)(80u)
226 #define ESM_G1ERR_SPI5_ECC_SBERR (uint32)(81u)
230 #define ESM_G1ERR_SPI1_ECC_UNCORR (uint32)(17u)
233 #define ESM_G1ERR_SPI2_ECC_UNCORR (uint32)(49u)
236 #define ESM_G1ERR_SPI3_ECC_UNCORR (uint32)(18u)
239 #define ESM_G1ERR_SPI4_ECC_UNCORR (uint32)(50u)
242 #define ESM_G1ERR_SPI5_ECC_UNCORR (uint32)(24u)
245 #endif
246
343 /*SAFETYMCUSW 298 S MR:- <APPROVED> Comment_1*/
344 typedef void (* ESM_Application_Callback) (uint32 grp_channel, uint32 param1, uint32 param2, uint32 param3);
345
346
347
354 typedef enum _SL_ResetReason {
355 RESET_TYPE_UNKNOWN = 0u,
356 RESET_TYPE_POWERON = 1u,
357 RESET_TYPE_OSC_FAILURE = 2u,
358 RESET_TYPE_WATCHDOG = 3u,
359 RESET_TYPE_DEBUG = 4u,
360 RESET_TYPE_ICEPICK = 5u,
361 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
362 RESET_TYPE_CPU = 6u,
363 #endif
364 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
365 RESET_TYPE_CPU0 = 6u,
366 RESET_TYPE_CPU1 = 10u,
367 #endif
368 RESET_TYPE_SWRST = 7u,
369 RESET_TYPE_EXTRST = 8u,
370 RESET_TYPE_EXTRST_NERROR = 9u
371 }SL_ResetReason;
372
379 typedef enum _SL_DCAN_Instance
380 {
381 SL_DCAN1 = 1,
382 SL_DCAN2,
383 SL_DCAN3,
384 SL_DCAN4
385 } SL_DCAN_Instance;
386
393 typedef enum _SL_MIBSPI_Instance
394 {
395 SL_MIBSPI1 = 1,
396 SL_MIBSPI2,
397 SL_MIBSPI3,
398 SL_MIBSPI4,
399 SL_MIBSPI5
400 } SL_MIBSPI_Instance;
401
402
409 typedef struct _SL_ResetReason_XInfo{
410 boolean nError;
411 uint32 esmGrp2Status;
412 uint32 esmGrp3Status;
413 } SL_ResetReason_XInfo;
414
415
416
424 typedef enum _SL_AutoInitRamId {
425 RAMTYPE_RAM = 0x00000001u,
427 RAMTYPE_DMA_RAM = 0x00000002u,
429 RAMTYPE_VIM = 0x00000004u,
431 RAMTYPE_NHET1 = 0x00000008u,
432 RAMTYPE_HET_TU1 = 0x00000010u
433 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
434 ,
435 RAMTYPE_NHET2 = 0x00008000u,
436 RAMTYPE_HET_TU2 = 0x00010000u,
438 RAMTYPE_DCAN1_RAM = 0x00000020u,
439 RAMTYPE_DCAN2_RAM = 0x00000040u,
440 RAMTYPE_DCAN3_RAM = 0x00000400u,
441 RAMTYPE_DCAN4_RAM = 0x00100000u,
443 RAMTYPE_MIBSPI1_RAM = 0x00000080u,
444 RAMTYPE_MIBSPI2_RAM = 0x00040000u,
445 RAMTYPE_MIBSPI3_RAM = 0x00000800u,
446 RAMTYPE_MIBSPI4_RAM = 0x00080000u,
447 RAMTYPE_MIBSPI5_RAM = 0x00001000u,
449 RAMTYPE_MIBADC1_RAM = 0x00000100u,
450 RAMTYPE_MIBADC2_RAM = 0x00004000u
451 #endif
452 #if defined(_TMS570LC43x_)
453 ,
454 RAMTYPE_FTU_RAM = 0x00002000u
455 #endif
456 } SL_AutoInitRamId;
457
458
459 #if defined(_TMS570LC43x_)
460 #define ALL_RAMTYPE_IDS (uint32)(RAMTYPE_RAM | \
461 RAMTYPE_DMA_RAM | \
462 RAMTYPE_VIM | \
463 RAMTYPE_NHET1 | \
464 RAMTYPE_NHET2 | \
465 RAMTYPE_HET_TU1 | \
466 RAMTYPE_HET_TU2 | \
467 RAMTYPE_DCAN1_RAM | \
468 RAMTYPE_DCAN2_RAM | \
469 RAMTYPE_DCAN3_RAM | \
470 RAMTYPE_DCAN4_RAM | \
471 RAMTYPE_MIBADC1_RAM | \
472 RAMTYPE_MIBADC2_RAM | \
473 RAMTYPE_MIBSPI1_RAM | \
474 RAMTYPE_MIBSPI2_RAM | \
475 RAMTYPE_MIBSPI3_RAM | \
476 RAMTYPE_MIBSPI4_RAM | \
477 RAMTYPE_MIBSPI5_RAM | \
478 RAMTYPE_FTU_RAM)
479 #endif
480 #if defined(_RM57Lx_)
481 #define ALL_RAMTYPE_IDS (uint32)(RAMTYPE_RAM | \
482 RAMTYPE_DMA_RAM | \
483 RAMTYPE_VIM | \
484 RAMTYPE_NHET1 | \
485 RAMTYPE_NHET2 | \
486 RAMTYPE_HET_TU1 | \
487 RAMTYPE_HET_TU2 | \
488 RAMTYPE_DCAN1_RAM | \
489 RAMTYPE_DCAN2_RAM | \
490 RAMTYPE_DCAN3_RAM | \
491 RAMTYPE_DCAN4_RAM | \
492 RAMTYPE_MIBADC1_RAM | \
493 RAMTYPE_MIBADC2_RAM | \
494 RAMTYPE_MIBSPI1_RAM | \
495 RAMTYPE_MIBSPI2_RAM | \
496 RAMTYPE_MIBSPI3_RAM | \
497 RAMTYPE_MIBSPI4_RAM | \
498 RAMTYPE_MIBSPI5_RAM)
499 #endif
500
508 typedef enum _SL_SelfTest_Type {
509 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
510 SRAM_ECC_ERROR_FORCING_1BIT = 0xA0,
511 SRAM_ECC_1BIT_FAULT_INJECTION,
512 SRAM_ECC_ERROR_FORCING_2BIT,
513 SRAM_ECC_2BIT_FAULT_INJECT,
514 SRAM_PAR_ADDR_CTRL_SELF_TEST,
515 SRAM_ECC_ERROR_PROFILING,
516 SRAM_ECC_ERROR_PROFILING_FAULT_INJECT,
517 SRAM_RADECODE_DIAGNOSTICS,
519 FEE_ECC_DATA_CORR_MODE,
520 FEE_ECC_SYN_REPORT_MODE,
521 FEE_ECC_MALFUNCTION_MODE1,
522 FEE_ECC_MALFUNCTION_MODE2,
523 FEE_ECC_ADDR_TAG_REG_MODE,
524 FEE_ECC_TEST_MODE_1BIT,
525 FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT,
526 FEE_ECC_TEST_MODE_2BIT,
527 FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT,
529 FLASH_ECC_ADDR_TAG_REG_MODE,
530 /*FLASH_ECC_PIPELINE_BUF_PAR_MODE, < Pipeline buffer parity diagnostic mode <NOT IMPLEMENTED IN THIS RELEASE> */
531 FLASH_ADDRESS_ECC_SELF_TEST,
532 FLASH_ADDRESS_ECC_FAULT_INJECT,
533 FLASH_ADDRESS_PARITY_SELF_TEST,
534 FLASH_ADDRESS_PARITY_FAULT_INJECT,
535 FLASH_ECC_TEST_MODE_1BIT,
536 FLASH_ECC_TEST_MODE_2BIT,
537 FLASH_HARD_ERROR_LIVELOCK,
538 FLASH_ECC_TEST_MODE_2BIT_FAULT_INJECT,
540 PBIST_EXECUTE,
541 PBIST_EXECUTE_OVERRIDE,
543 STC_RUN,
544 STC_COMPARE_SELFCHECK,
546 PSCON_SELF_TEST,
547 PSCON_ERROR_FORCING,
548 PSCON_ERROR_FORCING_FAULT_INJECT,
549 PSCON_SELF_TEST_ERROR_FORCING,
550 PSCON_SELF_TEST_ERROR_FORCING_FAULT_INJECT,
551 PSCON_PMA_TEST,
553 EFUSE_SELF_TEST_AUTOLOAD,
554 EFUSE_SELF_TEST_ECC,
555 EFUSE_SELF_TEST_STUCK_AT_ZERO,
556 CCMR4F_SELF_TEST,
557 CCMR4F_ERROR_FORCING_TEST,
558 CCMR4F_ERROR_FORCING_TEST_FAULT_INJECT,
559 CCMR4F_SELF_TEST_ERROR_FORCING,
560 L2INTERCONNECT_FAULT_INJECT,
561 L3INTERCONNECT_FAULT_INJECT
562 #endif
563 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
564 SRAM_ECC_ERROR_FORCING_1BIT = 0xA0A0,
568 SRAM_ECC_ERROR_FORCING_2BIT,
573 FLASH_ECC_TEST_MODE_1BIT,
577 FLASH_ECC_TEST_MODE_2BIT,
582 PBIST_EXECUTE,
587 PBIST_EXECUTE_OVERRIDE,
594 EFUSE_SELF_TEST_AUTOLOAD,
597 EFUSE_SELF_TEST_ECC,
599 EFUSE_SELF_TEST_STUCK_AT_ZERO,
603 CCMR5F_CPUCOMP_SELF_TEST,
606 CCMR5F_CPUCOMP_ERROR_FORCING_TEST,
609 CCMR5F_CPUCOMP_ERROR_FORCING_TEST_FAULT_INJECT,
614 CCMR5F_CPUCOMP_SELF_TEST_ERROR_FORCING,
617 CCMR5F_VIMCOMP_SELF_TEST,
620 CCMR5F_VIMCOMP_ERROR_FORCING_TEST,
623 CCMR5F_VIMCOMP_ERROR_FORCING_TEST_FAULT_INJECT,
628 CCMR5F_VIMCOMP_SELF_TEST_ERROR_FORCING,
631 CCMR5F_PDCOMP_SELF_TEST,
634 CCMR5F_PDCOMP_ERROR_FORCING_TEST,
637 CCMR5F_PDCOMP_ERROR_FORCING_TEST_FAULT_INJECT,
643 CCMR5F_PDCOMP_SELF_TEST_ERROR_FORCING,
646 CCMR5F_INMCOMP_SELF_TEST,
650 CCMR5F_INMCOMP_ERROR_FORCING_TEST,
654 CCMR5F_INMCOMP_ERROR_FORCING_TEST_FAULT_INJECT,
660 CCMR5F_INMCOMP_SELF_TEST_ERROR_FORCING,
665 STC1_RUN,
667 STC1_COMPARE_SELFCHECK,
670 STC2_RUN,
671 STC2_COMPARE_SELFCHECK,
673 DMA_ECC_TEST_MODE_1BIT,
678 DMA_ECC_TEST_MODE_2BIT,
682 DMA_ECC_TEST_MODE_1BIT_FAULT_INJECT,
686 DMA_ECC_TEST_MODE_2BIT_FAULT_INJECT,
691 CAN_ECC_TEST_MODE_1BIT,
695 CAN_ECC_TEST_MODE_2BIT,
699 CAN_ECC_TEST_MODE_1BIT_FAULT_INJECT,
703 CAN_ECC_TEST_MODE_2BIT_FAULT_INJECT,
708 MIBSPI_ECC_TEST_MODE_1BIT,
712 MIBSPI_ECC_TEST_MODE_2BIT,
716 MIBSPI_ECC_TEST_MODE_1BIT_FAULT_INJECT,
720 MIBSPI_ECC_TEST_MODE_2BIT_FAULT_INJECT
724 #endif
725
726 } SL_SelfTestType;
727
733 /*SAFETYMCUSW 79 S MR:19.4 <APPROVED> Comment_2*/
734 #define TESTTYPE_MIN SRAM_ECC_ERROR_FORCING_1BIT
735 /*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - Reviewed and the value assigned is an enumeration"*/
736 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
737 #define TESTTYPE_MAX L3INTERCONNECT_FAULT_INJECT
738 #endif
739 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
740 #define TESTTYPE_MAX MIBSPI_ECC_TEST_MODE_2BIT
741 #endif
742
749 typedef enum _SL_SelfTest_Result {
750 ST_FAIL = 0xAB,
751 ST_PASS = 0xCD
752 } SL_SelfTest_Result;
753
754
763 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
764 #define PBIST_RAMGROUP_01_PBIST_ROM (uint32)0x00000001u
765 #define PBIST_RAMGROUP_02_STC_ROM (uint32)0x00000002u
766 #define PBIST_RAMGROUP_03_DCAN1 (uint32)0x00000004u
767 #define PBIST_RAMGROUP_04_DCAN2 (uint32)0x00000008u
768 #define PBIST_RAMGROUP_05_DCAN3 (uint32)0x00000010u
769 #define PBIST_RAMGROUP_06_ESRAM1 (uint32)0x00000020u
770 #define PBIST_RAMGROUP_07_MIBSPI1 (uint32)0x00000040u
771 #define PBIST_RAMGROUP_08_MIBSPI3 (uint32)0x00000080u
772 #define PBIST_RAMGROUP_09_MIBSPI5 (uint32)0x00000100u
773 #define PBIST_RAMGROUP_10_VIM (uint32)0x00000200u
774 #define PBIST_RAMGROUP_11_MIBADC1 (uint32)0x00000400u
775 #define PBIST_RAMGROUP_12_DMA (uint32)0x00000800u
776 #define PBIST_RAMGROUP_13_N2HET1 (uint32)0x00001000u
777 #define PBIST_RAMGROUP_14_HETTU1 (uint32)0x00002000u
778 #define PBIST_RAMGROUP_15_RTP (uint32)0x00004000u
779 #define PBIST_RAMGROUP_16_FRAY (uint32)0x00008000u
780 #define PBIST_RAMGROUP_17_FRAY (uint32)0x00010000u
781 #define PBIST_RAMGROUP_18_MIBADC2 (uint32)0x00020000u
782 #define PBIST_RAMGROUP_19_N2HET2 (uint32)0x00040000u
783 #define PBIST_RAMGROUP_20_HETTU2 (uint32)0x00080000u
784 #define PBIST_RAMGROUP_21_ESRAM5 (uint32)0x00100000u
785 #define PBIST_RAMGROUP_22_ESRAM6 (uint32)0x00200000u
786 #define PBIST_RAMGROUP_23_ETHERNET1 (uint32)0x00400000u
787 #define PBIST_RAMGROUP_24_ETHERNET2 (uint32)0x00800000u
788 #define PBIST_RAMGROUP_25_ETHERNET3 (uint32)0x01000000u
789 #define PBIST_RAMGROUP_26_USB1 (uint32)0x02000000u
790 #define PBIST_RAMGROUP_27_USB2 (uint32)0x04000000u
791 #define PBIST_RAMGROUP_28_ESRAM8 (uint32)0x08000000u
792 #define PBIST_RAMGROUP_29_RSVD (uint32)0x10000000u
793 #endif
794 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
795 #define PBIST_RAMGROUP_01_PBIST_ROM (uint64)0x0000000001u
796 #define PBIST_RAMGROUP_02_STC1_1_ROM_R5 (uint64)0x0000000002u
797 #define PBIST_RAMGROUP_03_STC1_2_ROM_R5 (uint64)0x0000000004u
798 #define PBIST_RAMGROUP_04_STC2_ROM_NHET (uint64)0x0000000008u
799 #define PBIST_RAMGROUP_05_AWM1 (uint64)0x0000000010u
800 #define PBIST_RAMGROUP_06_DCAN1 (uint64)0x0000000020u
801 #define PBIST_RAMGROUP_07_DCAN2 (uint64)0x0000000040u
802 #define PBIST_RAMGROUP_08_DMA (uint64)0x0000000080u
803 #define PBIST_RAMGROUP_09_HTU1 (uint64)0x0000000100u
804 #define PBIST_RAMGROUP_10_MIBSPI1 (uint64)0x0000000200u
805 #define PBIST_RAMGROUP_11_MIBSPI2 (uint64)0x0000000400u
806 #define PBIST_RAMGROUP_12_MIBSPI3 (uint64)0x0000000800u
807 #define PBIST_RAMGROUP_13_NHET1 (uint64)0x0000001000u
808 #define PBIST_RAMGROUP_14_VIM (uint64)0x0000002000u
809 #define PBIST_RAMGROUP_15_RSVD (uint64)0x0000004000u
810 #define PBIST_RAMGROUP_16_RTP (uint64)0x0000008000u
811 #define PBIST_RAMGROUP_17_ATB (uint64)0x0000010000u
812 #define PBIST_RAMGROUP_18_AWM2 (uint64)0x0000020000u
813 #define PBIST_RAMGROUP_19_DCAN3 (uint64)0x0000040000u
814 #define PBIST_RAMGROUP_20_DCAN4 (uint64)0x0000080000u
815 #define PBIST_RAMGROUP_21_HTU2 (uint64)0x0000100000u
816 #define PBIST_RAMGROUP_22_MIBSPI4 (uint64)0x0000200000u
817 #define PBIST_RAMGROUP_23_MIBSPI5 (uint64)0x0000400000u
818 #define PBIST_RAMGROUP_24_NHET2 (uint64)0x0000800000u
819 #define PBIST_RAMGROUP_25_FTU (uint64)0x0001000000u
820 #define PBIST_RAMGROUP_26_FRAY_INBUF_OUTBUF (uint64)0x0002000000u
821 #define PBIST_RAMGROUP_27_CPGMAC_STATE_RXADDR (uint64)0x0004000000u
822 #define PBIST_RAMGROUP_28_CPGMAC_STAT_FIFO (uint64)0x0008000000u
823 #define PBIST_RAMGROUP_29_L2RAMW (uint64)0x0010000000u
824 #define PBIST_RAMGROUP_30_L2RAMW (uint64)0x0020000000u
825 #define PBIST_RAMGROUP_31_R5_ICACHE (uint64)0x0040000000u
826 #define PBIST_RAMGROUP_32_R5DCACHE (uint64)0x0080000000u
827 #define PBIST_RAMGROUP_33_RSVD (uint64)0x0100000000u
828 #define PBIST_RAMGROUP_34_RSVD (uint64)0x0200000000u
829 #define PBIST_RAMGROUP_35_FRAY_TRBUF_MSGRAM (uint64)0x0400000000u
830 #define PBIST_RAMGROUP_36_CPGMAC_CPPI (uint64)0x0800000000u
831 #define PBIST_RAMGROUP_37_R5_DCACHE_DIRTY (uint64)0x1000000000u
832 #define PBIST_RAMGROUP_38_RSVD (uint64)0x2000000000u
833 #endif
834
847 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
848 #define PBISTALGO_TRIPLE_READ_SLOW_READ (uint32)0x00000001u
849 #define PBISTALGO_TRIPLE_READ_FAST_READ (uint32)0x00000002u
850 #define PBISTALGO_MARCH13N_RED_2PORT (uint32)0x00000004u
851 #define PBISTALGO_MARCH13N_RED_1PORT (uint32)0x00000008u
852 #define PBISTALGO_DOWN1A_RED_2PORT (uint32)0x00000010u
853 #define PBISTALGO_DOWN1A_RED_1PORT (uint32)0x00000020u
854 #define PBISTALGO_MAPCOLUMN_2PORT (uint32)0x00000040u
855 #define PBISTALGO_MAPCOLUMN_1PORT (uint32)0x00000080u
856 #define PBISTALGO_PRECHARGE_2PORT (uint32)0x00000100u
857 #define PBISTALGO_PRECHARGE_1PORT (uint32)0x00000200u
858 #define PBISTALGO_DTXN2_2PORT (uint32)0x00000400u
859 #define PBISTALGO_DTXN2_1PORT (uint32)0x00000800u
860 #define PBISTALGO_PMOS_OPEN_2PORT (uint32)0x00001000u
861 #define PBISTALGO_PMOS_OPEN_1PORT (uint32)0x00002000u
862 #define PBISTALGO_PMOS_OP_SLICE1_2PORT (uint32)0x00004000u
863 #define PBISTALGO_PMOS_OP_SLICE2_2PORT (uint32)0x00008000u
864 #define PBISTALGO_FLIP10_2PORT (uint32)0x00010000u
865 #define PBISTALGO_FLIP10_1PORT (uint32)0x00020000u
866 #define PBISTALGO_IDDQ_2PORT (uint32)0x00040000u
867 #define PBISTALGO_IDDQ_1PORT (uint32)0x00080000u
868 #define PBISTALGO_RETENTION_2PORT (uint32)0x00100000u
869 #define PBISTALGO_RETENTION_1PORT (uint32)0x00200000u
870 #define PBISTALGO_IDDQ2_2PORT (uint32)0x00400000u
871 #define PBISTALGO_IDDQ2_1PORT (uint32)0x00800000u
872 #define PBISTALGO_RETENTION2_2PORT (uint32)0x01000000u
873 #define PBISTALGO_RETENTION2_1PORT (uint32)0x02000000u
874 #define PBISTALGO_IDDQROWSTRIPE_2PORT (uint32)0x04000000u
875 #define PBISTALGO_IDDQROWSTRIPE_1PORT (uint32)0x08000000u
876 #define PBISTALGO_IDDQROWSTRIPE2_2PORT (uint32)0x10000000u
877 #define PBISTALGO_IDDQROWSTRIPE2_1PORT (uint32)0x20000000u
878 #endif
879 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
880 #define PBISTALGO_TRIPLE_READ_SLOW_READ (uint32)0x00000001u
881 #define PBISTALGO_TRIPLE_READ_FAST_READ (uint32)0x00000002u
882 #define PBISTALGO_MARCH13N_2PORT (uint32)0x00000004u
883 #define PBISTALGO_MARCH13N_1PORT (uint32)0x00000008u
884 #define PBISTALGO_DOWN2_1PORT (uint32)0x00000010u
885 #define PBISTALGO_DOWN2_2PORT (uint32)0x00000020u
886 #define PBISTALGO_MARCH_DIS_INC_1PORT (uint32)0x00000040u
887 #define PBISTALGO_MARCH_DIS_INC_2PORT (uint32)0x00000080u
888 #define PBISTALGO_MARCH_DIS_DEC_1PORT (uint32)0x00000100u
889 #define PBISTALGO_MARCH_DIS_DEC_2PORT (uint32)0x00000200u
890 #define PBISTALGO_MARCH_DIS_INC_1PORT_1 (uint32)0x00000400u
891 #define PBISTALGO_MARCH_DIS_INC_2PORT_1 (uint32)0x00000800u
892 #define PBISTALGO_MARCH_DIS_DEC_1PORT_1 (uint32)0x00001000u
893 #define PBISTALGO_MARCH_DIS_DEC_2PORT_1 (uint32)0x00002000u
894 #define PBISTALGO_MAP_COLUMN_1PORT (uint32)0x00004000u
895 #define PBISTALGO_MAP_COLUMN_2PORT (uint32)0x00008000u
896 #define PBISTALGO_PRECHARGE_1PORT (uint32)0x00010000u
897 #define PBISTALGO_PRECHARGE_2PORT (uint32)0x00020000u
898 #define PBISTALGO_FLIP10_1PORT (uint32)0x00040000u
899 #define PBISTALGO_FLIP10_2PORT (uint32)0x00080000u
900 #define PBISTALGO_DTXN2_1PORT (uint32)0x00100000u
901 #define PBISTALGO_DTXN2_2PORT (uint32)0x00200000u
902 #define PBISTALGO_PMOS_OP_SLICE1_1PORT (uint32)0x00400000u
903 #define PBISTALGO_PMOS_OP_SLICE1_2PORT (uint32)0x00800000u
904 #define PBISTALGO_PMOS_OP_SLICE2_2PORT (uint32)0x01000000u
905 #endif
906
915 typedef struct _SL_PBIST_FailInfo {
916 SL_SelfTest_Result stResult;
917 uint8 port0FailCount;
918 uint8 port1FailCount;
919 uint16 port0FailAddress;
920 uint16 port1FailAddress;
921 uint32 port0FailData;
922 uint32 port1FailData;
923 } SL_PBIST_FailInfo;
924
925
926
932 typedef struct _SL_STC_Config {
933 uint8 stcClockDiv;
934 uint16 intervalCount;
935 boolean restartInterval0;
936 uint32 timeoutCounter;
937 } SL_STC_Config;
938
939
940
946 typedef struct _SL_STC_FailInfo {
947 SL_SelfTest_Result stResult;
948 SL_SelfTest_Result CPU1Failure;
949 SL_SelfTest_Result CPU2Failure;
950 SL_SelfTest_Result TimeOutFailure;
951 } SL_STC_FailInfo;
952
953
954 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
955
960 typedef struct _SL_PSCON_FailInfo {
961 SL_SelfTest_Result stResult;
962 uint32 pdFailure;
963 uint32 mdFailure;
964 } SL_PSCON_FailInfo;
965 #endif
966
974 typedef enum _SL_EFuse_Error {
975 EFUSE_ERROR_NONE = 0u,
976 EFUSE_ERROR_TIMEOUT = 1u,
977 EFUSE_ERROR_AUTOLOAD_1 = 2u,
978 EFUSE_ERROR_AUTOLOAD_2 = 3u,
979 EFUSE_ERROR_AUTOLOAD_INTRPTD = 4u,
980 EFUSE_ERROR_AUTOLOAD_2B_ERR = 5u,
981 EFUSE_ERROR_PROG_W_PROTECT = 6u,
982 EFUSE_ERROR_PROG_W_D_ITER = 7u,
983 EFUSE_ERROR_PROG_CTRL_ITER = 8u,
984 EFUSE_ERROR_UNPROG_BIT_SET = 9u,
985 EFUSE_ERROR_RED_REP_ROW =10u
986 }SL_EFuse_Error;
987
988
989
995 typedef struct _SL_EFuse_FailInfo {
996 SL_SelfTest_Result stResult;
997 SL_EFuse_Error failInfo;
998 } SL_EFuse_FailInfo;
999
1000
1007 typedef struct _SL_EFuse_Config {
1008 uint32 numPatterns;
1009 uint32 seedSignature;
1010 SL_EFuse_FailInfo failInfo;
1011 } SL_EFuse_Config;
1012
1013 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
1014 typedef enum _SL_CCMR4F_Error {
1015 CCMR4F_ST_ERR_COMPARE_MATCH = 1u,
1016 CCMR4F_ST_ERR_COMPARE_MISMATCH = 2u
1017 } SL_CCMR4F_Error;
1018
1019 typedef struct _SL_CCMR4F_FailInfo {
1020 SL_SelfTest_Result stResult;
1021 SL_CCMR4F_Error failInfo;
1022 }SL_CCMR4F_FailInfo;
1023 #endif
1024 #if defined(_TMS570LC43x_) || defined(_RM57Lx_)
1025 typedef enum _SL_CCMR5F_Error {
1026 CCMR5F_ST_ERR_COMPARE_MATCH = 1u,
1027 CCMR5F_ST_ERR_COMPARE_MISMATCH = 2u
1028 } SL_CCMR5F_Error;
1029
1030 typedef struct _SL_CCMR5F_FailInfo {
1031 SL_SelfTest_Result stResult;
1032 SL_CCMR5F_Error failInfo;
1033 }SL_CCMR5F_FailInfo;
1034 #endif
1035
1036 #if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
1037
1043 typedef struct _SL_ADC_Config {
1044 sl_adcBASE_t* adcbase;
1045 uint8 adc_channel;
1046 } SL_ADC_Config;
1047
1053 typedef enum _SL_ADC_Pinstatus {
1054 ADC_PIN_GOOD,
1055 ADC_PIN_SHORTED_TO_ADVREF_HIGH,
1056 ADC_PIN_SHORTED_TO_ADVREF_LOW,
1057 ADC_PIN_OPEN,
1058 ADC_PIN_UNDETERMINED
1059 } SL_ADC_Pinstatus;
1060 #endif
1061 #endif /* __SL_TYPES_H__ */
1062
1063 /*Comment_1:
1064 * "Reason - ESM callback changes at runtime"*/
1065
1066 /*Comment_2:
1067 * "Reason - Reviewed and the value assigned is an enumeration"*/
RESET_TYPE_DEBUG
Definition: sl_types.h:467
CCMR5F_CPUCOMP_ERROR_FORCING_TEST
Definition: sl_types.h:714
CCMR5F_PDCOMP_ERROR_FORCING_TEST
Definition: sl_types.h:742
CCMR5F_INMCOMP_ERROR_FORCING_TEST
Definition: sl_types.h:758
RAMTYPE_DMA_RAM
Definition: sl_types.h:535
ADC_PIN_GOOD
Definition: sl_types.h:1162
PSCON_SELF_TEST_ERROR_FORCING_FAULT_INJECT
Definition: sl_types.h:658
PSCON_ERROR_FORCING_FAULT_INJECT
Definition: sl_types.h:656
CAN_ECC_TEST_MODE_2BIT
Definition: sl_types.h:803
CCMR5F_VIMCOMP_ERROR_FORCING_TEST_FAULT_INJECT
Definition: sl_types.h:731
EFUSE_ERROR_AUTOLOAD_1
Definition: sl_types.h:1085
CCMR5F_CPUCOMP_ERROR_FORCING_TEST_FAULT_INJECT
Definition: sl_types.h:717
_SL_EFuse_Error
_SL_EFuse_Error
Definition: sl_types.h:1082
_SL_SelfTest_Type
_SL_SelfTest_Type
Definition: sl_types.h:616
RESET_TYPE_ICEPICK
Definition: sl_types.h:468
CCMR4F_ERROR_FORCING_TEST_FAULT_INJECT
Definition: sl_types.h:666
SRAM_RADECODE_DIAGNOSTICS
Definition: sl_types.h:625
FEE_ECC_SYN_REPORT_MODE
Definition: sl_types.h:628
CCMR5F_PDCOMP_SELF_TEST_ERROR_FORCING
Definition: sl_types.h:751
SL_PSCON_FailInfo
PSCON failure information. Used in with SL_SelfTest_PSCON_FailInfo API.
ESM_Application_Callback
void(* ESM_Application_Callback)(uint32 grp_channel, uint32 param1, uint32 param2, uint32 param3)
Definition for ESM Application call back type.
Definition: sl_types.h:452
RAMTYPE_HET_TU2
Definition: sl_types.h:544
RAMTYPE_DCAN2_RAM
Definition: sl_types.h:547
FLASH_ECC_TEST_MODE_1BIT
Definition: sl_types.h:643
EFUSE_ERROR_AUTOLOAD_2B_ERR
Definition: sl_types.h:1088
EFUSE_ERROR_TIMEOUT
Definition: sl_types.h:1084
MIBSPI_ECC_TEST_MODE_1BIT
Definition: sl_types.h:816
CAN_ECC_TEST_MODE_2BIT_FAULT_INJECT
Definition: sl_types.h:811
EFUSE_ERROR_PROG_W_D_ITER
Definition: sl_types.h:1090
FLASH_ADDRESS_PARITY_FAULT_INJECT
Definition: sl_types.h:642
RAMTYPE_FTU_RAM
Definition: sl_types.h:562
ADC_PIN_SHORTED_TO_ADVREF_HIGH
Definition: sl_types.h:1163
PSCON_SELF_TEST
Definition: sl_types.h:654
FLASH_ECC_TEST_MODE_2BIT_FAULT_INJECT
Definition: sl_types.h:646
CCMR5F_PDCOMP_ERROR_FORCING_TEST_FAULT_INJECT
Definition: sl_types.h:745
RAMTYPE_MIBSPI1_RAM
Definition: sl_types.h:551
RAMTYPE_DCAN3_RAM
Definition: sl_types.h:548
EFUSE_ERROR_UNPROG_BIT_SET
Definition: sl_types.h:1092
RAMTYPE_DCAN1_RAM
Definition: sl_types.h:546
RESET_TYPE_EXTRST_NERROR
Definition: sl_types.h:478
ADC_PIN_UNDETERMINED
Definition: sl_types.h:1166
DMA_ECC_TEST_MODE_1BIT
Definition: sl_types.h:781
PBIST_EXECUTE
Definition: sl_types.h:648
PSCON_SELF_TEST_ERROR_FORCING
Definition: sl_types.h:657
CCMR4F_ERROR_FORCING_TEST
Definition: sl_types.h:665
MIBSPI_ECC_TEST_MODE_1BIT_FAULT_INJECT
Definition: sl_types.h:824
EFUSE_ERROR_AUTOLOAD_INTRPTD
Definition: sl_types.h:1087
SL_ResetReason_XInfo
Provides extended information of the previous reset (using shadow registers)
FEE_ECC_TEST_MODE_2BIT
Definition: sl_types.h:634
DMA_ECC_TEST_MODE_2BIT_FAULT_INJECT
Definition: sl_types.h:794
SL_STC_FailInfo
STC failure information. Used in conjunction with SL_SelfTest_STC_Status API.
SL_EFuse_FailInfo
EFuse Self-test failure information.
EFUSE_SELF_TEST_STUCK_AT_ZERO
Definition: sl_types.h:663
EFUSE_SELF_TEST_ECC
Definition: sl_types.h:662
ADC_PIN_SHORTED_TO_ADVREF_LOW
Definition: sl_types.h:1164
EFUSE_ERROR_RED_REP_ROW
Definition: sl_types.h:1093
CCMR4F_SELF_TEST
Definition: sl_types.h:664
EFUSE_ERROR_AUTOLOAD_2
Definition: sl_types.h:1086
SRAM_ECC_ERROR_FORCING_1BIT
Definition: sl_types.h:618
RAMTYPE_RAM
Definition: sl_types.h:533
SL_STC_Config
STC Configuration information to be used with SL_SelfTest_STC API.
FEE_ECC_ADDR_TAG_REG_MODE
Definition: sl_types.h:631
ADC_PIN_OPEN
Definition: sl_types.h:1165
FLASH_ADDRESS_ECC_SELF_TEST
Definition: sl_types.h:639
SRAM_ECC_ERROR_PROFILING_FAULT_INJECT
Definition: sl_types.h:624
MIBSPI_ECC_TEST_MODE_2BIT_FAULT_INJECT
Definition: sl_types.h:828
FLASH_ADDRESS_ECC_FAULT_INJECT
Definition: sl_types.h:640
CAN_ECC_TEST_MODE_1BIT_FAULT_INJECT
Definition: sl_types.h:807
DMA_ECC_TEST_MODE_2BIT
Definition: sl_types.h:786
FLASH_ADDRESS_PARITY_SELF_TEST
Definition: sl_types.h:641
PSCON_PMA_TEST
Definition: sl_types.h:659
RAMTYPE_MIBADC2_RAM
Definition: sl_types.h:558
RESET_TYPE_CPU
Definition: sl_types.h:470
EFUSE_ERROR_PROG_W_PROTECT
Definition: sl_types.h:1089
EFUSE_SELF_TEST_AUTOLOAD
Definition: sl_types.h:661
CCMR5F_PDCOMP_SELF_TEST
Definition: sl_types.h:739
SRAM_ECC_ERROR_FORCING_2BIT
Definition: sl_types.h:620
SRAM_ECC_2BIT_FAULT_INJECT
Definition: sl_types.h:621
RAMTYPE_MIBSPI4_RAM
Definition: sl_types.h:554
FLASH_ECC_TEST_MODE_2BIT
Definition: sl_types.h:644
FEE_ECC_MALFUNCTION_MODE2
Definition: sl_types.h:630
CCMR5F_CPUCOMP_SELF_TEST
Definition: sl_types.h:711
FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT
Definition: sl_types.h:633
CCMR5F_VIMCOMP_SELF_TEST
Definition: sl_types.h:725
CCMR5F_VIMCOMP_SELF_TEST_ERROR_FORCING
Definition: sl_types.h:736
RESET_TYPE_EXTRST
Definition: sl_types.h:477
_SL_AutoInitRamId
_SL_AutoInitRamId
Definition: sl_types.h:532
RAMTYPE_NHET2
Definition: sl_types.h:543
RESET_TYPE_UNKNOWN
Definition: sl_types.h:463
STC1_RUN
Definition: sl_types.h:773
FEE_ECC_DATA_CORR_MODE
Definition: sl_types.h:627
CCMR5F_INMCOMP_SELF_TEST_ERROR_FORCING
Definition: sl_types.h:768
DMA_ECC_TEST_MODE_1BIT_FAULT_INJECT
Definition: sl_types.h:790
RAMTYPE_HET_TU1
Definition: sl_types.h:540
FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT
Definition: sl_types.h:635
STC1_COMPARE_SELFCHECK
Definition: sl_types.h:775
SRAM_PAR_ADDR_CTRL_SELF_TEST
Definition: sl_types.h:622
_SL_ADC_Pinstatus
_SL_ADC_Pinstatus
Definition: sl_types.h:1161
MIBSPI_ECC_TEST_MODE_2BIT
Definition: sl_types.h:820
RAMTYPE_MIBSPI3_RAM
Definition: sl_types.h:553
_SL_ResetReason
_SL_ResetReason
Definition: sl_types.h:462
RESET_TYPE_POWERON
Definition: sl_types.h:464
RAMTYPE_DCAN4_RAM
Definition: sl_types.h:549
RAMTYPE_VIM
Definition: sl_types.h:537
FLASH_ECC_ADDR_TAG_REG_MODE
Definition: sl_types.h:637
FEE_ECC_TEST_MODE_1BIT
Definition: sl_types.h:632
PSCON_ERROR_FORCING
Definition: sl_types.h:655
CCMR5F_INMCOMP_ERROR_FORCING_TEST_FAULT_INJECT
Definition: sl_types.h:762
CCMR5F_CPUCOMP_SELF_TEST_ERROR_FORCING
Definition: sl_types.h:722
EFUSE_ERROR_PROG_CTRL_ITER
Definition: sl_types.h:1091
STC_RUN
Definition: sl_types.h:651
RAMTYPE_MIBADC1_RAM
Definition: sl_types.h:557
RESET_TYPE_WATCHDOG
Definition: sl_types.h:466
STC_COMPARE_SELFCHECK
Definition: sl_types.h:652
CCMR5F_INMCOMP_SELF_TEST
Definition: sl_types.h:754
EFUSE_ERROR_NONE
Definition: sl_types.h:1083
SRAM_ECC_1BIT_FAULT_INJECTION
Definition: sl_types.h:619
RAMTYPE_NHET1
Definition: sl_types.h:539
RAMTYPE_MIBSPI2_RAM
Definition: sl_types.h:552
RESET_TYPE_OSC_FAILURE
Definition: sl_types.h:465
RAMTYPE_MIBSPI5_RAM
Definition: sl_types.h:555
PBIST_EXECUTE_OVERRIDE
Definition: sl_types.h:649
CCMR5F_VIMCOMP_ERROR_FORCING_TEST
Definition: sl_types.h:728
CCMR4F_SELF_TEST_ERROR_FORCING
Definition: sl_types.h:667
SRAM_ECC_ERROR_PROFILING
Definition: sl_types.h:623
RESET_TYPE_SWRST
Definition: sl_types.h:476
CAN_ECC_TEST_MODE_1BIT
Definition: sl_types.h:799
FEE_ECC_MALFUNCTION_MODE1
Definition: sl_types.h:629
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